M12L128168A-7TIG

ESMT SDRAM M12L128168A Operation temperature condition -40°C ~85°C 2M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION PRODUCT NO. M12L128168A-5TIG M12L128168A-5BIG M12L128168A-6TIG M12L128168A-6BIG M12L128168A-7TIG M12L128168A-7BIG MAX FREQ. PACKAGE COMMENTS 200MHz 200MHz 166MHz 166MHz 143MHz 143MHz TSOP II BGA TSOP II BGA TSOP II BGA Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read single write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) GENERAL DESCRIPTION The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Pin Arrangement (Top View) VDD DQ0 VDDQ DQ1 DQ2 V S SQ DQ3 DQ4 VDDQ DQ5 DQ6 V S SQ DQ7 VDD LDQM WE CAS RAS CS A13 A12 A10 /AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS DQ15 V S SQ DQ14 DQ13 VDDQ DQ12 DQ11 V S SQ DQ10 DQ9 VDDQ DQ8 V SS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 V SS 1 A VSS 2 DQ15 3 VSSQ 4 5 6 7 VDDQ 8 DQ0 9 VDD B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE CAS RAS WE G NC A11 A9 A13 A12 CS H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 1/43 ESMT BLOCK DIAGRAM CLK CKE Address Mode Register Clock Generator Bank D Bank C Bank B Row Address Buffer & Refresh Counter Row Decoder M12L128168A Operation temperature condition -40°C ~85°C Bank A Sense Amplifier Command Decoder Control Logic L(U)DQM CS RAS CAS WE Column Address Buffer & Counter Column Decoder Input & Output Buffer Latch Circuit Data Control Circuit DQ PIN DESCRIPTION PIN CLK CS CKE A0 ~ A11 A12 , A13 RAS NAME System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe INPUT FUNCTION Active on the positive going edge to sample all inputs Disables or enables device operation by masking or enabling all inputs except CLK , CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior new command. Disable input buffers for power down in standby. Row / column address are multiplexed on the same pins. Row address : RA0~RA11, column address : CA0~CA8 Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. (Enables row access & precharge.) Latches column address on the positive going edge of the CLK with CAS low. (Enables column access.) Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs / outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. CAS WE Column Address Strobe Write Enable Data Input / Output Mask Data Input / Output Power Supply / Ground Data Output Power / Ground No Connection L(U)DQM DQ0 ~ DQ15 VDD / VSS VDDQ / VSSQ N.C Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 2/43 ESMT M12L128168A Operation temperature condition -40°C ~85°C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current Note : Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Unit V V °C W mA Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITION Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -40 to 85 °C ) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Note: Symbol VDD, VDDQ VIH VIL VOH VOL IIL IOL Min 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 5 5 Unit V V V V V μA μA Note 1 2 IOH = -2mA IOL = 2mA 3 4 1. VIH(max) = 4.6V AC for pulse width ≤ 10ns acceptable. 2. VIL(min) = -1.5V AC for pulse width ≤ 10ns acceptable. 3. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V. 4. Dout is disabled , 0V ≤ VOUT ≤ VDD. CAPACITANCE (VDD = 3.3V, TA = 25 °C , f = 1MHZ) Parameter Input capacitance (A0 ~ A11, A13 ~ A12) Input capacitance (CLK, CKE, CS , RAS , CAS , WE & L(U)DQM) Data input/output capacitance (DQ0 ~ DQ15) COUT 2 6.5 pF Symbol CIN1 CIN2 Min 2.5 2.5 Max 4 4 Unit pF pF Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 3/43 ESMT DC CHARACTERISTICS Recommended operating condition unless otherwise noted，TA = -40 to 85 °C Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS Active Standby Current in power-down mode ICC3P ICC3PS ICC3N Test Condition CAS Latency M12L128168A Operation temperature condition -40°C ~85°C Version -5 170 -6 160 2 2 45 -7 140 Unit mA mA Note 1,2 Burst Length = 1, tRC ≥ tRC(min), IOL = 0 mA CKE ≤ VIL(max), tcc = tCK(MIN) CKE & CLK ≤ VIL (max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = tCK(MIN) Input signals are changed one time during 2tck CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞ input signals are stable CKE ≤ VIL(max), tCC = tCK(MIN) CKE & CLK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns Input signals are changed one time during 2clks All other pins ≥ VDD-0.2V or ≤ 0.2V CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ input signals are stable IOL = 0 mA, Page Burst, 2 Banks activated tRC ≥ tRC(min) CKE ≤ 0.2V Precharge Standby Current in non power-down mode mA 25 6 6 55 mA mA Active Standby Current in non power-down mode (One Bank Active) Operating Current (Burst Mode) Refresh Current Self Refresh Current Note : ICC3NS ICC4 ICC5 ICC6 35 280 280 210 210 2 180 180 mA mA mA mA 1,2 1. Measured with outputs open. 2. Input signals are changed one time during 2 CLKS. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 4/43 ESMT AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V，TA = -40 to 85 °C ) Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall-time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 M12L128168A Operation temperature condition -40°C ~85°C Unit V V ns V 3.3V 1200 Output 870 Ω 50pF Vtt = 1.4V Ω VOH (DC) =2.4V , IOH = -2 mA VOL (DC) =0.4V , IOL = 2 mA Output Z0 =50 50 Ω Ω 50pF (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Version Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time @ Operating @ Auto refresh Symbol -5 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRFC(min) tCDL(min) tRDL(min) tBDL(min) tREF(max) 53 55 10 15 15 38 -6 12 18 18 40 100 58 60 1 2 1 64 63 70 -7 14 20 20 42 ns ns ns ns us ns ns tCK tCK tCK ms 1 1,5 2 2 2 6 1 1 1 1 Unit Note Row cycle time Last data in to col. address delay Last data in to row precharge Last data in to burst stop Refresh period (4,096 rows) Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 5/43 ESMT Version Parameter Col. address to col. address delay Number of valid Output data Symbol -5 tCCD(min) -6 1 2 1 M12L128168A Operation temperature condition -40°C ~85°C Unit -7 tCK ea Note 3 4 CAS latency = 3 CAS latency = 2 Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. A new command may be given tRFC after self refresh exit. 6. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6 μ s.) AC CHARACTERISTICS (AC operating condition unless otherwise noted) Parameter CAS latency = 3 CAS latency = 2 CAS latency = 3 CAS latency = 2 CAS latency = 3 CAS latency = 2 Symbol MIN CLK cycle time CLK to valid output delay Output data hold time CLK high pulsh width CLK low pulsh width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z Note : CAS latency = 3 CAS latency = 2 tCC 5 10 -5 MAX 1000 4.5 6 2 2 2 2 1.5 1 1 4.5 6 2.5 2.5 2.5 2.5 1.5 1 1 5.4 6 MIN 6 10 -6 MAX 1000 5.4 6 2.5 2.5 2.5 2.5 1.5 1 1 5.4 6 MIN 7 10 -7 MAX 1000 5.4 6 ns 1 Unit Note tSAC ns 1,2 tOH tCH tCL tSS tSH tSLZ tSHZ ns ns ns ns ns ns ns 2 3 3 3 3 2 - 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered. 3. Assumed input rise and fall time (tr & tf) =1ns. If tr & tf is longer than 1ns. transient time compensation should be considered. i.e., [(tr + tf)/2 – 1] ns should be added to the parameter. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 6/43 ESMT SIMPLIFIED TRUTH TABLE COMMAND Register Refresh Mode Register set Auto Refresh Entry Self Refresh Exit Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DQM No Operating Command L H H X H L H CKEn-1 H H L H H CKEn X H L H X X CS RAS CAS L L L H L L L L H X L H L L H X H L WE M12L128168A Operation temperature condition -40°C ~85°C DQM X X X X X X L H H X H H A13 A11 A10/AP A12 A9~A0 OP CODE X X V V Row Address Column L Address H (A0~A8) Column L Address H (A0~A8) X L H X Note 1,2 3 3 3 3 4 4,5 4 4,5 6 H H H X X X L L L H L X H L H L H H L X V X X H X V X X H L H H X V X X H X V X H L L L X V X X H X V X H X X X V Burst Stop Precharge V X Clock Suspend or Active Power Down H L H L H L X X X X X X V X X X 7 (V = Valid , X = Don’t Care. H = Logic High , L = Logic Low ) Note : 1.OP Code : Operating Code A0~A11 & A13~A12 : Program keys. (@ MRS) 2.MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3.Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge of command is meant by “Auto”. Auto/self refresh can be issued only at all banks idle state. 4.A13~A12 : Bank select addresses. If A13 and A12 are “Low” at read ,write , row active and precharge ,bank A is selected. If A13 is “Low” and A12 is “High” at read ,write , row active and precharge ,bank B is selected. If A13 is “High” and A12 is “Low” at read ,write , row active and precharge ,bank C is selected. If A13 and A12 are “High” at read ,write , row active and precharge ,bank D is selected If A10/AP is “High” at row precharge , A13 and A12 is ignored and all banks are selected. 5.During burst read or write with auto precharge. new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6.Burst stop command is valid at every burst length. 7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2) Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 7/43 ESMT MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address Function A13~A12 RFU A11~A10/AP RFU A9 W.B.L. A8 TM A7 A6 A5 A4 M12L128168A Operation temperature condition -40°C ~85°C A3 BT A2 A1 A0 CAS Latency Burst Length Test Mode A8 0 0 1 1 A7 0 1 0 1 Type Mode Register Set Reserved Reserved Reserved A6 0 0 0 0 1 1 1 1 CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Burst Type A3 0 1 Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 1 2 4 8 Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved Full Page Length : 512 POWER UP SEQUENCE 1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the inputs. 2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. Note : 1. RFU(Reserved for future use) should stay “0” during MRS cycle. 2. If A9 is high during MRS cycle, “ Burst Read single write” function will be enabled. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 8/43 ESMT BURST SEQUENCE (BURST LENGTH = 4) Initial Adrress A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 Sequential M12L128168A Operation temperature condition -40°C ~85°C Interleave 1 0 3 2 2 3 0 1 3 2 1 0 BURST SEQUENCE (BURST LENGTH = 8) Initial A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 Sequential Interleave Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 9/43 ESMT DEVICE OPERATIONS CLOCK (CLK) The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper functionality and Icc specifications. M12L128168A Operation temperature condition -40°C ~85°C POWER-UP 1.Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at the inputs. 2.Maintain stable power, stable clock and NOP input condition for minimum of 200us. 3.Issue precharge commands for both banks of the devices. 4.Issue 2 or more auto-refresh commands. 5.Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. CLOCK ENABLE(CKE) The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least “1CLK + tSS” before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS , RAS , CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A11 and A13~A12 in the same cycle as CS , RAS , CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields into depending on functionality. The burst length field uses A0~A2, burst type uses A3, CAS latency (read latency from column address) use A4~A6, vendor specific options or test mode use A7~A8, A10/AP~A11 and A13~A12. The write burst length is programmed using A9. A7~A8, A10/AP~A11 and A13~A12 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies. BANK ADDRESSES (A13~A12) This SDRAM is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. The A13~A12 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The banks addressed A13~A12 are latched at bank active, read, write, mode register set and precharge operations. ADDRESS INPUTS (A0~A11) The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (A0~A11). The 12 row addresses are latched along with RAS and A13~A12 during bank active command. The 9 bit column addresses are latched along with CAS , WE and A13~A12 during read or with command. NOP and DEVICE DESELECT When RAS , CAS and WE are high , The SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS , CAS , WE and all the address inputs are ignored. BANK ACTIVATE The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of bank activation. tRCD is the internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 10/43 ESMT DEVICE OPERATIONS (Continued) dividing tRCD(min) with cycle time of the clock and then rounding of the result to the next higher integer. The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS (max) and tRAS(max) can be calculated similar to tRCD specification. M12L128168A Operation temperature condition -40°C ~85°C DQM OPERATION The DQM is used mask input and output operations. It works similar to OE during operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is required. Please refer to DQM timing diagram also. PRECHARGE The precharge is performed on an active bank by asserting low on clock cycles required between bank activate and clock cycles required between bank activate and CS , RAS , WE and A10/AP with valid A13~A12 of the bank to be procharged. The precharge command can be asserted anytime after tRAS(min) is satisfy from the bank active command in the desired bank. tRP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing tRP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS(max). Therefore, each bank has to be precharge with tRAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state. BURST READ The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and RAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. AUTO PRECHARGE The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS(min) and “tRP” for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst write by asserting high on A10/AP, the bank is precharge command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state. BURST WRITE The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS , CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be complete by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and precharge the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also. FOUR BANKS PRECHARGE Four banks can be precharged at the same time by using Precharge all command. Asserting low on CS , RAS , and WE with high on A10/AP after all banks have satisfied tRAS(min) requirement, performs precharge on all banks. At the end of tRP after performing precharge all, all banks are in idle state. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 11/43 ESMT DEVICE OPERATIONS (Continued) AUTO REFRESH The storage cells of SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS , RAS and CAS with high on CKE and WE . The auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRFC(min). The minimum number of clock cycles required can be calculated by driving tRFC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP’s until the auto refresh operation is completed. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us. M12L128168A Operation temperature condition -40°C ~85°C SELF REFRESH The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS , RAS , CAS and CKE with high on WE . Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the refresh. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation. It is recommended to use burst 4096 auto refresh cycles immediately before and after self refresh. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 12/43 ESMT COMMANDS M12L128168A Operation temperature condition -40°C ~85°C Mode register set command ( CS , RAS , CAS , WE = Low) The M12L128168A has a mode register that defines how the device operates. In this command, A0 through A13 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2CLK following this command, the M12L128168A cannot accept any other commands. CLK CKE CS RAS CAS WE A12, A13 A10 Add Fig. 1 Mode register set command H Activate command ( CS , RAS = Low, CAS , WE = High) The M12L128168A has four banks, each with 4,096 rows. This command activates the bank selected by A12 and A13 (BS) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM’s RAS falling. CLK CKE CS RAS CAS WE (Bank select) H A12, A13 A10 Add Row Row Fig. 2 Row address strobe and bank active command Precharge command ( CS , RAS , WE = Low, CAS = High ) This command begins precharge operation of the bank selected by A12 and A13 (BS). When A10 is High, all banks are precharged, regardless of A12 and A13. When A10 is Low, only the bank selected by A12 and A13 is precharged. After this command, the M12L128168A can’t accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM’s RAS rising. CLK CKE CS RAS CAS WE A12, A13 A10 (Bank select) (Precharge select) H Add Fig. 3 Precharge command Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 13/43 ESMT Write command ( CS , CAS , WE = Low, RAS = High) If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst can be input with this command with subsequent data on following clocks. M12L128168A Operation temperature condition -40°C ~85°C CLK CKE CS RAS CAS WE A12, A13 H (Bank select) A10 Add Col. Fig. 4 Column address and write command CLK Read command ( CS , CAS = Low, RAS , WE = High) Read data is available after CAS latency requirements have been met. This command sets the burst start address given by the column address. CKE CS RAS CAS WE A12, A13 (Bank select) H A10 Add Col. Fig. 5 Column address and read command CLK CBR (auto) refresh command CKE H ( CS , RAS , CAS = Low, WE , CKE = High) This command is a request to begin the CBR refresh operation. The refresh address is generated internally. Before executing CBR refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or activate command), the M12L128168A cannot accept any other command. CS RAS CAS WE A12, A13 (Bank select) A10 Add Fig. 6 Auto refresh command Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 14/43 ESMT Self refresh entry command ( CS , RAS , CAS , CKE = Low , WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the M12L128168A exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged. M12L128168A Operation temperature condition -40°C ~85°C CLK CKE CS RAS CAS WE A12, A13 (Bank select) A10 Add Fig. 7 Self refresh entry command Burst stop command ( CS , WE = Low, RAS , CAS = High) CLK CKE CS H This command terminates the current burst operation. Burst stop is valid at every burst length. RAS CAS WE A12, A13 (Bank select) A10 Add Fig. 8 Burst stop command CLK No operation ( CS = Low , RAS , CAS , WE = High) This command is not a execution command. No operations begin or terminate by this command. CKE CS RAS CAS WE A12, A13 (Bank select) H A10 Add Fig. 9 No operation Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 15/43 ESMT BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During W rite (BL=4) M12L128168A Operation temperature condition -40°C ~85°C 2) Clock Suspended During Read (BL=4) CLK CMD WR RD CKE Internal CLK DQ(CL2) DQ(CL3) D0 D1 D1 Masked by CKE D2 D3 D3 Q0 Q1 Q2 Q3 D0 D2 Q1 Q2 Q3 Q0 Not W ritten Suspe nded Dout 2. DQM Operation 1)Write Mask (BL=4) 2)Read Mask (BL=4) CLK CMD WR RD DQM Ma s k e d b y D Q M Ma s k e d b y D Q M Hi-Z DQ(CL2) DQ(CL3) D0 D1 D1 D3 D3 Q0 Q2 Q1 Q3 D0 Hi-Z Q2 Q3 DQ M t o D at a- i n M as k = 0 DQ M to D at a- ou t M ask = 2 *Note2 3)DQM with clcok su sp end ed (F ull Page Read ) CLK CMD CKE Internal CLK DQM Q0 Hi- Z RD DQ( CL2 ) DQ(CL3) Q2 Q1 Hi- Z Q4 Hi- Z Q6 Q5 Q7 Q6 Q8 Q7 Hi-Z Hi-Z Q3 Hi-Z *Note : 1. CKE to CLK disable/enable = 1CLK. 2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”. 3. DQM masks both data-in and data-out. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 16/43 ESMT 3. CAS Interrupt (I) M12L128168A Operation temperature condition -40°C ~85°C *N ote1 1)R ea d i nt er ru pt ed by R ead (B L =4) CL K C MD ADD DQ ( C L 2 ) D Q ( CL 3 ) C CD *N ot e 2 RD A RD B QA0 QB0 QA0 QB1 QB0 QB2 QB1 QB3 QB2 QB3 t 2) Wr i t e i n t er ru pt e d b y W ri t e (B L= 2) 3 )W ri t e in t er rup t ed b y R e ad (B L=2 ) CLK C MD WR WR * No t e 2 WR RD *N ote 2 t CC D A DD DQ A tC CD A B DB 0 D B1 DQ ( C L 2 ) D Q ( CL 3 ) B DB0 DB1 DB 0 DB1 DA0 DA0 DA 0 CDL * No t e 3 CDL * No t e 3 t t *Note : 1. By “interrupt” is meant to stop burst read/write by external before the end of burst. By ” CAS interrupt ”, to stop burst read/write by CAS access ; read and write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (=1CLK) Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 17/43 ESMT 4. CAS Interrupt (II) : Read Interrupted by Write & DQM M12L128168A Operation temperature condition -40°C ~85°C ( a) CL =2 , B L= 4 CLK i)CMD DQM WR RD DQ ii)CMD DQM D0 RD D1 WR D2 D3 DQ iii)CMD DQM Hi-Z D0 D1 WR D2 D3 RD DQ iv)CMD DQM Hi-Z D0 D1 WR D2 D3 RD DQ Q0 HH - - Z i iZ *Note1 D0 D1 D2 D3 Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 18/43 ESMT (b) CL =3 ,B L= 4 CLK i)CMD DQM DQ RD WR M12L128168A Operation temperature condition -40°C ~85°C D0 D1 WR D2 D3 ii)CMD DQM DQ RD D0 D1 D2 D3 iii)CMD DQM RD WR DQ iv)CMD DQM DQ v)CM D DQM DQ RD RD D0 D1 WR D2 D3 Hi-Z D0 D1 WR D2 D3 Q0 Hi-Z *Note1 D0 D1 D2 D3 *Note : 1. To prevent bus contention, there should be at least one gap between data in and data out. 5. Write Interrupted by Precharge & DQM C LK CMD WR PRE * N ot e 3 *N o te 2 DQ M DQ D0 D1 D2 D3 tR D L ( m in ) M asked by DQM *Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 19/43 ESMT 6. Precharge M12L128168A Operation temperature condition -40°C ~85°C 1) Nor mal W rit e (B L=4) 2) Norm al Read (B L= 4) CLK CMD DQ WR D0 D1 D2 D3 PRE CLK CMD RD Q0 Q1 PRE Q2 CL=2 *Note2 DQ( CL2) Q3 tRDL *Note1 CMD DQ ( CL 3 ) PRE CL= 3 *Note2 Q0 Q1 Q2 Q3 . 7. Auto Precharge 1)Normal W rit e (BL=4) 2)Normal Read (BL=4) CLK CLK WR D0 D1 D2 D3 CMD RD D0 D1 D0 D2 D1 D3 D3 CMD DQ DQ( CL 2) tRDL (min ) DQ(CL3) *Note3 D2 Auto Pr ech arge st art s *Note3 Auto Pr ech arge st art s *Note : 1. tRDL : Last data in to row precharge delay. 2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 20/43 ESMT 8. Burst Stop & Interrupted by Precharge M12L128168A Operation temperature condition -40°C ~85°C 1)W rite Burst Stop (BL=8) 1)Write interrupted by precharge (BL=4) CLK CMD WR STOP CLK CMD *Note3 WR tRDL PRE *Note4 DQM DQ DQM DQ Mask Mask D0 D1 D2 D3 D4 D5 D0 D1 tBDL *Note1 2)Read Burst Stop (BL=4) 2)Read interrupted by precharge (BL=4) CLK CMD RD STOP *Note2 CLK CMD DQ(CL3) *Note2 *Note5 RD Q0 Q1 PRE Q2 Q1 Q3 Q2 Q3 DQ(CL2) DQ(CL3) Q0 Q1 Q0 Q1 DQ(CL2) Q0 9. MRS 1) Mo d e Re g is te r S e t CLK *Note4 CMD PRE MRS ACT tRP 2CLK *Note: 1. tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 2. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely. 3. Write burst is terminated. tBDL determinates the last data write. 4. DQM asserted to prevent corruption of locations D2 and D3. 5. Precharge can be issued here or earlier (satisfying tRAS min delay) with DQM. 6. PRE : All banks precharge, if necessary. MRS can be issued only at all banks precharge state. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 21/43 ESMT 10. Clock Suspend Exit & Power Down Exit 1) Cl o ck S u sp en d (= Ac t ive P ow er Do wn ) Exi t M12L128168A Operation temperature condition -40°C ~85°C 2)P ower Down (= Pr ec ha rg e Power Down ) CLK CKE Inter nal CLK CMD CLK CKE Internal CLK RD CMD tSS *Note1 tSS *Note2 NOP AC T 11. Auto Refresh & Self Refresh 1)Auto Refresh & Self Refresh *Note3 CLK *Note4 CMD *Note5 PRE AR CMD CKE tRP 2)Self Refresh *Note6 tRFC CLK *Note4 CMD PRE SR CMD CKE tRP tRFC *Note : 1. Active power down : one or more banks active state. 2. Precharge power down : all banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During tRFC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, all banks must be idle state. 5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh entry, refresh interval and refresh operation are performed internally. After self refresh entry, self refresh mode is kept while CKE is low. During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state. For the time interval of tRFC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst auto refresh (4096 cycles) is recommended. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007 Revision: 1.2 22/43