M12S16161A-7BG

ESMT SDRAM M12S16161A 512K x 16Bit x 2Banks Synchronous DRAM FEATURES JEDEC standard 2.5V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency (2 & 3 ) Burst Length (1, 2, 4, 8 & full page) Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 32ms refresh period (2K cycle) GENERAL DESCRIPTION The M12S16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. M12S16161A-6TG M12S16161A-7TG M12S16161A-6BG M12S16161A-7BG MAX Freq. 166MHz 143MHz 166MHz 143MHz PACKAGE COMMENTS TSOP(II) TSOP(II) VFBGA VFBGA Pb-free Pb-free Pb-free Pb-free PIN CONFIGURATION (TOP VIEW) 1 A VSS 2 DQ15 3 4 5 6 DQ0 7 VDD VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ N.C/RFU UDQM CLK CKE N.C A9 A8 A7 A6 A5 A4 VSS 50PIN TSOP(II) (400mil x 825mil) (0.8 mm PIN PITCH) B DQ14 VSSQ VDDQ DQ1 C DQ13 VDDQ VSSQ DQ2 D DQ12 DQ11 DQ4 DQ3 E DQ10 VSSQ VDDQ DQ5 F DQ9 VDDQ VSSQ DQ6 G DQ8 NC NC DQ7 H NC NC NC NC J NC UDQM LDQM WE K NC CLK RAS CAS L CKE NC NC CS M BA A9 NC NC N A8 A7 A0 A10 P A6 A5 A2 A1 60 Ball VFBGA (6.4x10.1mm) (0.65mm ball pitch) R VSS A4 A3 VDD Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 1/28 ESMT FUNCTIONAL BLOCK DIAGRAM M12S16161A I/O Control LWE LDQM Bank Select Data Input Register Row Buffer Refresh Counter Row Decoder Sense AMP Output Buffer 512K x 16 Address Register LRAS CLK CLK ADD 512K x 16 DQi LCBR LRAS Col. Buffer Column Decoder Latency & Burst Length LCKE Programming Register LCBR LWE LCAS LWCBR LDQM Timing Register CKE CS RAS CAS WE L(U)DQM PIN FUNCTION DESCRIPTION Pin CLK CS CKE A0 ~ A10/AP BA RAS Name System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. CAS Column Address Strobe WE Write Enable Data Input / Output Mask L(U)DQM Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 2/28 ESMT DQ0 ~ 15 VDD/VSS VDDQ/VSSQ N.C/RFU Data Input / Output Power Supply/Ground Data Output Power/Ground No Connection/ Reserved for Future Use M12S16161A Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN,VOUT VDD,VDDQ TSTG PD IOS Value -1.0 ~ 3.6 -1.0 ~ 3.6 -55 ~ + 150 0.7 50 Unit V V °C W MA Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA=0 to 70 °C ) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol VDD,VDDQ VIH VIL VOH VOL IIL IOL Min 2.375 0.8xVDDQ -0.3 VDDQ -0.2 -10 -10 Typ 2.5 0 Max 2.625 VDDQ+0.3 0.3 0.2 10 10 Unit V V V V V uA uA Note 1 2 IOH = -0.1mA IOL = -0.1mA 3 4 Note : 1.VIH (max) = 3.0V AC for pulse width ≤ 3ns acceptable. 2.VIL (min) = -1.0V AC for pulse width ≤ 3ns acceptable. 3.Any input 0V ≤ VIN ≤ VDDQ+ 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V ≤ VOUT ≤ VDDQ. CAPACITANCE (VDD = 2.5V, TA = 25 °C , f = 1MHz) Pin CLOCK RAS , CAS , WE , CS , CKE, LDQM, UDQM ADDRESS DQ0 ~DQ15 Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 4.0 5.0 5.0 6.5 Unit pF pF pF pF Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 3/28 ESMT DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70 °C Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Precharge Standby Current in non power-down mode Symbol Test Condition CAS Latency M12S16161A Version -6 115 2 2 25 -7 100 Unit Note ICC1 ICC2P ICC2PS ICC2N Burst Length = 1 tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA CKE ≤ VIL(max), tCC =15ns CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns Input signals are changed one time during 30ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable CKE ≤ VIL(max), tCC =15ns CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns Input signals are changed one time during 30ns CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞ Input signals are stable IOL= 0Ma, Page Burst All Band Activated, tCCD = tCCD (min) tRC ≥ tRC(min) CKE ≤ 0.2V 3 2 mA mA mA mA 1 ICC2NS Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) Operating Current (Burst Mode) Refresh Current Self Refresh Current ICC3P ICC3PS ICC3N ICC3NS 10 10 10 25 10 135 135 135 1 120 120 120 mA mA mA mA mA mA mA mA 2 1 ICC4 ICC5 ICC6 Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min). 2.Refresh period is 32ms. Addresses are changed only one time during tCC(min). Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 4/28 ESMT AC OPERATING TEST CONDITIONS (VDD=2.375~2.625V,TA= 0 to 70 °C ) Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 0.9 x VDDQ / 0.2 0.5 x VDDQ tr / tf = 1 / 1 0.5 x VDDQ See Fig.2 M12S16161A Unit V V ns V OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to new col. Address delay Last data in to row precharge Last data in to burst stop Col. Address to col. Address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tCDL(min) tRDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 54 1 2 1 1 2 1 Version -6 12 18 18 36 100 63 -7 14 20 20 42 Unit ns ns ns ns us ns CLK CLK CLK CLK ea 1 2 2 2 3 4 Note 1 1 1 1 Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 5/28 ESMT AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CLK cycle time CLK to valid output delay CAS Latency =3 CAS Latency =2 CAS Latency =3 CAS Latency =2 Symbol tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ -6 Min 6 8 2 2 2 2 1 1 5.5 6 Max 1000 5.5 6 Min 7 8.6 2 2.5 2.5 2 1 1 6 6 6 6 -7 Max 1000 M12S16161A Note ns ns ns ns ns ns ns ns ns Note 1 1 2 3 3 3 3 2 Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS Latency =3 CAS latency =2 *All AC parameters are measured from half to half. Note: 1.Parameters depend on programmed CAS latency. 2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3.Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 6/28 ESMT Mode Register 11 0 11 x 11 11 x 11 0 10 0 10 x 10 10 x 10 0 9 0 9 1 9 9 x 9 0 8 0 8 0 8 1 8 1 8 0 7 1 7 0 7 0 7 1 7 0 6 5 4 4 3 3 WT 3 3 v 3 WT 2 2 BL 2 2 v 2 1 1 v 1 BL 0 Use in future 6 v 6 5 4 v v 5 4 LTMODE 0 v 0 Vender Specific Mode Register Set 1 1 0 6 5 LTMODE 6 5 0 M12S16161A JEDEC Standard Test Set (refresh counter test) Burst Read and Single Write (for Write Through Cache) 4 v =Valid x =Don’t care Bit2-0 000 001 010 011 100 101 110 111 0 1 WT=0 1 2 4 8 R R R Full page Sequential Interleave WT=1 1 2 4 8 R R R R Burst length Wrap type Bits6-4 000 001 010 011 100 101 110 111 Latency mode Mode Register Write Timing CAS Latency R R 2 3 R R R R Remark R : Reserved CLOCK CKE CS RAS CAS WE A0-A11 M ode Register W rite Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 7/28 ESMT Burst Length and Sequence (Burst of Two) Starting Address (column address A0 binary) 0 1 Sequential Addressing Sequence (decimal) 0,1 1,0 M12S16161A Interleave Addressing Sequence (decimal) 0,1 1,0 (Burst of Four) Starting Address (column address A1-A0, binary) 00 01 10 11 Sequential Addressing Sequence (decimal) 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 Interleave Addressing Sequence (decimal) 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 (Burst of Eight) Starting Address (column address A2-A0, binary) 000 001 010 0 11 100 101 11 0 1 11 Sequential Addressing Sequence (decimal) 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5 7,0,1,2,3,4,5,6 Interleave Addressing Sequence (decimal) 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice. POWER UP SEQUENCE 1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs. 2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3.Issue precharge commands for all banks of the devices. 4.Issue 2 or more auto-refresh commands. 5.Issue mode register set command to initialize the mode register. Cf.)Sequence of 4 & 5 is regardless of the order. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 8/28 ESMT SIMPLIFIED TRUTH TABLE COMMAND Mode Register Set Auto Refresh Entry Self Refresh Exit CKEn-1 CKEn CS H X L H H L L L H H H X X L H L L RAS L L H X L H CAS L L H X H L WE L M12S16161A Register Refresh H H X H H DQM BA A10/AP A9~A0 Note X OP CODE 1,2 3 X X 3 X X X V V X Row Address Column L H 3 3 4 Bank Active & Row Addr. Auto Precharge Disable Read & Column Address Write & Column Address Burst Stop Precharge Clock Suspend or Active Power Down Precharge Power Down Mode Bank Selection Both Banks Entry Exit Entry Exit DQM No Operation Command Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable H H H H L H L H H H X X X L H L H L L L H L X H L H L H L H H L X V X X H X V X X H L H H X V X X H X V X H L L L X V X X H X V X H X X X X X X V L H X L H X Address (A0~A7) 4,5 Column 4 Address 4,5 (A0~A7) V X X 6 4 4 X X V X X X 7 X (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) Note: 1. OP Code: Operation Code A0~ A10/AP, BA: Program keys.(@MRS) 2. 3. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by “Auto”. Auto / self refresh can be issued only at both banks idle state. 4. BA: Bank select address. If “Low”: at read, write, row active and precharge, bank A is selected. If “High”: at read, write, row active and precharge, bank B is selected. If A10/AP is “High” at row precharge, BA ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read /write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 9/28 ESMT M12S16161A Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK tCL tCC HIGH CKE *Note1 tRAS tRC tSH CS tRCD tSH RAS tSS CAS tSS tSH ADDR Ra tSS *Note2 *Note2,3 tRP tSS tCCD tSH tSS Ca Cb tSH *Note2,3 *Note2,3 *Note4 *Note2 Cc Rb BA BS BS BS BS BS BS A10 /AP Ra *Note 3 *Note 3 *Note 3 *Note4 Rb tRAC tSAC DQ Qa tSLZ WE tSS tSS DQM tSH tOH Db tSS tSH tSH Qc Row Active Read W rite Read Precharge Row Active :D on' t Care Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 10/28 ESMT 2. Bank active & read/write are controlled by BA. M12S16161A *Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge. BA 0 1 Active & Read/Write Bank A Bank B 3.Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/AP 0 BA 0 1 1 0 1 Operation Disable auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP 0 0 1 BA 0 1 X precharge Bank A Bank B Both Banks Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 11/28 ESMT Power Up Sequence 0 CLOCK M12S16161A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High l evel is n ec es sar y CS tRP RAS tRC tRC CAS ADDR Key RAa BA Key A10 /AP Key RAa High-Z DQ WE DQM High level is necessary Precharge All Banks Auto Ref res h Auto Ref resh Mode R egis ter Set ( A- Ban k ) Row Active : Don't care Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 12/28 ESMT Read & Write Cycle at Same Bank @Burst Length = 4 0 CLOCK M12S16161A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HIGH CKE *Note1 t RC CS tRCD RAS *Note2 CAS ADDR Ra Ca0 Rb Cb0 BA A10/AP Ra Rb tO H CL=2 QC CL=3 R AC *Note3 Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 t R AC *Note3 t S AC Qa0 tS H Z tOH Qa1 Qa2 Qa3 *Note4 tRDL Db0 Db1 Db2 Db3 t t S AC tS H Z *Note4 tRDL WE DQ M Row Active (A- Bank) Read (A- Bank) Precharge (A- Bank) Row Active (A- Bank) W r ite (A-Bank) Precharge (A- Bank) : Don't care *Note: 1.Minimum row cycle times is required to complete internal DRAM operation. 2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC 4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst) Burst can’t end in Full Page Mode. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 13/28 ESMT Page Read & Write Cycle at Same Bank @ Burst Length=4 0 CLOCK CKE CS HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M12S16161A 15 16 17 18 19 tRCD RAS *Note2 CAS ADDR Ra Ca0 Cb0 Cc0 Cd0 BA A10/AP Ra tRDL CL=2 DQ Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd2 Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1 CL=3 tCDL WE *Note3 *Note1 DQM Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 14/28 ESMT Page Read Cycle at Different Bank @ Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 M12S16161A 16 17 18 19 CLOCK CKE *Note1 HIGH CS RAS *Note2 CAS ADDR RAa CAa RBb CBb CAc CBd CAe BA A10/AP RAa RBb CL=2 DQ CL=3 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 WE DQM Row Active (A-Bank) Read (A-Bank) Row Active (B-Bank) Read (B-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Precharge (A-Bank) : Don't care *Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege. 2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 15/28 ESMT Page Write Cycle at Different Bank @Burst Length = 4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M12S16161A 15 16 17 18 19 CKE HIGH CS RAS CAS *Note2 ADDR RAa CAa RBb CBb CAc CBd BA A10/AP RAa RBb DQ DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 tCDL WE tRDL *Note1 DQM Row Active (A-Bank) Row Active (B-Bank) W rite (A-Bank) W rite (B-Bank) Write (A-Bank) Write (B-Bank) Precharge (Both Banks) : Don't care *Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 16/28 ESMT Read & Write Cycle at Different Bank @ Burst Length = 4 M12S16161A 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH CS RAS CAS *Note2 ADDR RAa CAa RBb CBb CAc CBd BA A10/AP RAa RBb DQ DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 tCDL WE tRDL *Note1 DQM Row Active (A-Bank) Row Active (B-Bank) W rite (A-Bank) W rite (B-Bank) Write (A-Bank) Write (B-Bank) Precharge (Both Banks) : Don't care *Note: 1.tCDL should be met to complete write. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 17/28 ESMT Read & Write Cycle with auto Precharge @ Burst Length =4 0 CLOCK M12S16161A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HIGH CKE CS RAS CAS ADDR Ra Rb Ca Cb BA A10 /A P Ra Rb CL= 2 DQ CL=3 Qa0 Q a1 Qa2 Q a3 Db0 Db1 Db2 Db3 Q a0 Q a1 Qa2 Qa3 Db0 Db1 Db2 Db3 WE DQM Row Active ( A - Bank ) Read with Auto Precharge ( A - Bank ) Row Active ( B - Bank ) Auto Precharge Start Point ( A - Bank) W rite with Auto Pr echarge ( B- Bank ) Auto Pr echarge Star t Poin t ( B- Bank ) :D on' t Ca re *Note: 1.tCDL Should be controlled to meet minimum tRAS before internal precharge start (In the case of Burst Length=1 & 2 and BRSW mode) Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 18/28 ESMT 0 CLOCK M12S16161A Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE CS RAS CAS ADDR Ra Ca Cb Cc BA A10 /AP Ra DQ Q a0 Qa1 Q a2 Q a3 Qb0 Q b1 Dc 0 Dc2 tSHZ WE tSHZ *Note1 DQM Row Active Read Clock Suspension Read W rite DQM Read DQM W rite Cloc k Sus pension W rite DQM :Don't Car e *Note:1.DQM is needed to prevent bus contention. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 19/28 ESMT 0 CLOCK M12S16161A Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HIGH CKE CS RAS CAS ADDR RAa CAa CAb BA A10 /AP RAa *Note2 CL=2 DQ 1 1 QAb0 QAb1 QAb 2 QAb3 QAb4 QAb5 QAa0 QAa1 QAa2 QAa 3 QAa4 2 CL=3 QAa0 QAa1 QAa 2 QAa3 QAa4 2 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 WE *Note1 DQM Row Active ( A- B an k ) Read (A- Ban k) Burst Stop Read (A- Ban k) Precharge ( A- B an k ) :Don't Care *Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue. 2.About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycle”. 3.Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 20/28 ESMT 0 CLOCK M12S16161A Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH CS RAS CAS ADDR RAa CAa CAb BA A10 /AP RAa tBDL *Note2 tRDL DQ DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 WE DQM Row Active ( A- B an k ) W rite (A- Ban k ) Burst Stop W rite (A- Ban k ) Precharge ( A- B an k ) :Don't Care *Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue. 2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. Input data after Row precharge cycle will be masked internally. 3.Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 21/28 ESMT Burst Read Single bit Write Cycle @Burst Length=2 CLOCK M12S16161A *Note1 CKE HIGH CS RAS *Note2 CAS ADDR RAa CAa RBb CAb RAc CBc CAd BA A10 /AP RAa RBb RAc CL=2 DQ CL= 3 DAa0 QAb0 QAb1 DBc0 QAd0 QAd1 DAa0 QAb0 QAb1 DBc0 QAd0 QAd1 WE DQM Row Active ( A- B an k ) Row Active (B-Bank) Read with Auto Precharge (A-Bank) Row Act ive ( A- B an k ) W rite with Auto Pr echarge ( B- Bank ) Read ( A- B an k ) Precharge ( A- B an k ) W rite (A- Ban k) :Don't Care *Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set). At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length. 2.When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge command will be issued after two clock cycles. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 22/28 ESMT Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4 0 CLOCK *Note2 M12S16161A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tSS CKE *Note1 tS S *Not e3 tS S CS RAS CAS ADDR Ra Ca BA A10 /A P Ra tSHZ DQ Q a0 Qa1 Qa2 WE DQM Pr ech ar g e Pow er - Dow n Entry Row Active Precharge Power-Down Exit Read Active Power-down Exit Precharge Active Power-down Entry : Don't care *Note :1.Both banks should be in idle state prior to entering precharge power down mode. 2.CKE should be set high at least 1CLK+tss prior to Row active command. 3.Can not violate minimum refresh specification. (32ms) Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 23/28 ESMT Self Refresh Entry & Exit Cycle 0 CLOCK *Note2 *Note4 M12S16161A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRCmin *Note6 *Note1 CKE *Note3 tSS CS *Note5 RAS *Note7 CAS ADDR BA A10 /AP DQ Hi-Z Hi-Z WE DQM Sel f R ef r esh En tr y S e l f R ef r e s h E xi t Auto Refresh : Don't care *Note: TO ENTER SELF REFRESH MODE 1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE. 3. The device remains in self refresh mode as long as CKE stays “Low”. cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS Starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 24/28 ESMT Mode Register Set Cycle 0 CLOCK 1 2 3 4 5 6 M12S16161A Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 HIGH CKE HIGH CS *Note2 RAS *Note1 CAS *Note3 ADDR Key Ra tRC DQ Hi-Z Hi-Z WE DQM MRS New C om m an d Auto Ref res h New C om m an d :Don't Care *Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note: 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 25/28 ESMT PACKAGE DIMENSIONS 50-LEAD TSOP(II) SDRAM(400mil) M12S16161A Symbol A A1 A2 B B1 C C1 D E E1 L L1 e θ Min 0.051 0.95 0.30 0.30 0.12 0.10 20.82 11.56 10.03 0.40 0 Dimension in mm Nom 0.127 1.00 0.35 0.127 20.95 11.76 10.16 0.50 0.80 REF 0.80 BSC - Max 1.20 0.203 1.05 0.45 0.40 0.21 0.16 21.08 11.96 10.29 0.60 Min 0.002 0.037 0.012 0.012 0.005 0.004 0.820 0.455 0.394 0.016 8 0 Dimension in inch Nom 0.005 0.039 0.014 0.005 0.825 0.463 0.400 0.020 0.031 REF 0.031 BSC - Max 0.047 0.008 0.041 0.018 0.016 0.008 0.006 0.830 0.471 0.405 0.024 8 Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 26/28 ESMT PACKING 60-BALL DIMENSIONS SDRAM ( 6.4x10.1 mm ) M12S16161A Symbol A A1 A2 Φb D E D1 E1 e Dimension in mm Min Norm Max 1.00 0.20 0.25 0.30 0.61 0.66 0.71 0.30 0.35 0.40 6.30 6.40 6.50 10.00 10.10 10.20 3.90 9.10 0.65 Dimension in inch Min Norm Max 0.039 0.008 0.010 0.012 0.024 0.026 0.028 0.012 0.014 0.016 0.248 0.252 0.256 0.394 0.398 0.402 0.154 0.358 0.026 Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 27/28 ESMT Important Notice All rights reserved. M12S16161A No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.2 28/28