M13S128324A-5BG

ESMT DDR SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2; 2.5; 3;4 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE Data mask (DM) for write masking only VDD = 2.375V ~ 2.625V, VDDQ = 2.375V ~ 2.625V VDD = 2.5V ~ 2.7V, VDDQ = 2.5V ~ 2.7V [for speed -3.6] Auto & Self refresh 32ms refresh period (4K cycle) SSTL-2 I/O interface 144Ball FBGA and 100 pin LQFP package M13S128324A 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Ordering Information: PRODUCT NO. M13S128324A -3.6BG M13S128324A -4BG M13S128324A -5BG M13S128324A -6BG M13S128324A -4LG M13S128324A -5LG M13S128324A -6LG MAX FREQ 275MHz 250MHz 200MHz 166MHz 250MHz 200MHz 166MHz VDD 2.6V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V PACKAGE 144 Ball FBGA 144 Ball FBGA 144 Ball FBGA 144 Ball FBGA 100 pin LQFP 100 pin LQFP 100 pin LQFP COMMENTS Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 1/50 ESMT Functional Block Diagram CLK CLK CKE Address Mode Register & Extended Mode Register M13S128324A Clock Generator Bank D Bank C Bank B Row Decoder Row Address Buffer & Refresh Counter Bank A Sense Amplifier Command Decoder Control Logic CS RAS CAS WE Data Control Circuit Input & Output Buffer Latch Circuit Column Address Buffer & Refresh Counter DM Column Decoder DQ CLK, CLK DLL DQS DQS Pin Arrangement 144(12x12) FBGA 2 B C D E F G H J K L M N DQS0 DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ21 DQ22 CAS RAS CS 3 DM0 VDDQ DQ5 VDDQ DQ16 DQ18 DM2 DQ20 DQ23 WE NC NC 4 VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD NC BA0 5 DQ3 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS BA1 A0 6 DQ2 DQ1 VSSQ VSSQ VSS Thermal 7 DQ0 VDDQ VDD VSS VSS Thermal 8 DQ31 VDDQ VDD VSS VSS Thermal 9 DQ29 DQ30 VSSQ VSSQ VSS Thermal 10 DQ28 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS NC A7 11 VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD CLK A8/AP 12 DM3 VDDQ DQ26 VDDQ DQ15 DQ13 DM1 DQ11 DQ9 NC CLK CKE 13 DQS3 DQ27 DQ25 DQ24 DQ14 DQ12 DQS1 DQ10 DQ8 NC NC VREF VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS A10 A2 A1 VSS VDD A11 A3 VSS VDD A9 A4 VSS NC A5 A6 Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 2/50 ESMT Pin Arrangement M13S128324A DQ29 VSSQ DQ30 DQ31 VSS VDDQ N.C N.C N.C N.C N.C VSSQ N.C DQS VDDQ VDD DQ0 DQ1 VSSQ DQ2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 A7 A6 A5 A4 VSS A9 N.C N.C N.C N.C N.C N.C N.C A11 A10 VDD A3 A2 A1 A0 100 Pin LQFP Forward Type 20 x 14 mm 0.65 mmpin Pitch 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Pin Description (M13S128324A) Pin Name Function Address inputs - Row address A0~A11 - Column address A0~A7 A8/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power Bi- directional Data Strobe. DQS0 correspond to the data on DQ0~DQ7. DQS1 correspond to the data on DQ8~DQ15. DQS2 correspond to the data on DQ16~DQ23. DQS3 correspond to the data on DQ24~DQ31. Bi- directional Data Strobe. Pin Name Function A0~A11, BA0,BA1 DM0~DM3 DQ Mask enable in write cycle. DQ0~DQ31 RAS CAS WE CLK, CLK CKE CS VDDQ VSSQ VREF Clock input Clock enable Chip select Supply Voltage for GDQ Ground for DQ Reference Voltage for SSTL VSS VDD DQS0~DQS3 (for FBGA) DQS (for LQFP) NC No connection - - Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 3/50 ESMT Absolute Maximum Rating Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Note: Symbol VIN, VOUT VDD VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 2 50 M13S128324A Unit V V V °C W mA Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operation Condition & Specifications DC Operation Condition Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 °C ) Parameter Supply voltage I/O Supply voltage I/O Reference voltage I/O Termination voltage (system) Input logic high voltage Input logic low voltage Input Voltage Level, CLK and CLK inputs Input Differential Voltage, CLK and CLK inputs Input leakage current Output leakage current Output High Current (Normal strength driver) (VOUT =VDDQ-0.373V, min VREF, min VTT) Output Low Current (Normal strength driver) (VOUT = 0.373V) Output High Current (Weak strength driver) (VOUT =VDDQ-0.763V, min VREF, min VTT) Output Low Current (Weak strength driver) (VOUT = 0.763V) Notes: 1. 2. 3. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. VID is the magnitude of the difference between the input level on CLK and the input level on CLK . Symbol VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) II IOZ IOH IOL IOH IOL Min -3.6 2.5 2.5 -4/5/6 2.375 2.375 -3.6 2.7 2.7 Max -4/5/6 2.625 2.625 Unit V V V V V V V V 3 4 1 2 Note 0.49*VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 -2 -5 -16.8 +16.8 -9 +9 0.51*VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 2 5 μA μA mA mA mA mA 4. VIN = 0V to VDD, All other pins are not tested under VIN = 0V. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 4/50 ESMT DC Specifications Parameter Operation Current (One Bank Active) Operation Current (One Bank Active) Precharge Power-down Standby Current Idle Standby Current Active Power-down Standby Current Active Standby Current Operation Current (Read) Operation Current (Write) Auto Refresh Current Self Refresh Current Symbol Test Condition tRC = tRC (min) tCK = tCK (min) Active – Precharge Burst Length = 2 tRC = tRC (min), CL= 2.5 IOUT = 0mA, Active-Read- Precharge CKE ≤ VIL(max), tCK = tCK (min), All banks idle CKE ≥ VIH(min), CS ≥ VIH(min), tCK = tCK (min) All banks ACT, CKE ≤ VIL(max), tCK = tCK (min) One bank; Active-Precharge, tRC = tRAS(max), tCK = tCK (min) Burst Length = 2, CL= 2.5 , tCK = tCK (min), IOUT = 0mA Burst Length = 2, CL= 2.5 , tCK = tCK (min) tRC ≥ tRFC(min) CKE ≤ 0.2V -3.6 235 -4 210 M13S128324A Version -5 175 -6 145 Unit Note IDD0 mA - IDD1 245 220 190 180 mA - IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 40 135 60 150 440 470 320 3 40 120 55 130 400 430 290 3 40 115 50 120 350 380 270 3 40 95 45 110 300 330 250 3 mA mA mA mA mA mA mA mA 1 Note: 1. Enable on-chip refresh and address counters. AC Operation Conditions & Timing Specification AC Operation Conditions Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Different Voltage, CLK and CLK inputs Input Crossing Point Voltage, CLK and CLK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Min VREF + 0.35 0.7 0.5*VDDQ-0.2 Max VREF - 0.35 VDDQ+0.6 0.5*VDDQ+0.2 Unit V V V V Note 1 2 Note: 1. VID is the magnitude of the difference between the input level on CLK and the input on CLK . 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Input / Output Capacitance (VDD = 2.375V~2.625V, VDDQ =2.375V~2. 625V, TA = 25 °C , f = 1MHz) (VDD = 2.5V~2.7V, VDDQ =2.5V~2.7V, TA = 25 °C , f = 1MHz (for speed -3.6)) Parameter Input capacitance(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE ) Symbol CIN1 CIN2 COUT CIN3 Min 1 1 1 1 Max 4 5 6.5 6.5 Unit pF pF pF pF Input capacitance (CLK, CLK ) Data & DQS input/output capacitance Input capacitance (DM) Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 5/50 ESMT AC Operating Test Conditions Parameter Input reference voltage for clock (VREF) Input signal maximum peak swing Input signal minimum slew rate Input levels (VIH/VIL) Input timing measurement reference level Output timing reference level Value 0.5*VDDQ 1.5 1.0 VREF+0.35/VREF-0.35 VREF VTT M13S128324A Unit V V V/ns V V V AC Timing Parameter & Specifications (VDD = 2.375V~2.625V, VDDQ=2.375V~2.625V, TA =0 °C to 70 °C ) (VDD = 2.5V~2.7V, VDDQ =2.5V~2.7V, TA = 0 °C to 70 °C (for speed -3.6)) -3.6 Min 7.5 6.0 tCK CL3 CL4 Access time from CLK/ CLK CLK high-level width CLK low-level width Data strobe edge to clock edge Clock to first rising edge of DQS delay Data-in and DM setup time (to DQS) Data-in and DM hold time (to DQS) DQ and DM input pulse width (for each input) Input setup time (fast slew rate) Input hold time (fast slew rate) Control and Address input pulse width DQS input high pulse width DQS input low pulse width DQS falling edge to CLK rising-setup time DQS falling edge from CLK rising-hold time Data strobe edge to output data edge Data-out high-impedance window from CLK/ CLK Data-out low-impedance window from CLK/ CLK tAC tCH tCL tDQSCK tDQSS tDS tDH tDIPW tIS tIH tIPW tDQSH tDQSL tDSS tDSH tDQSQ tHZ 5.0 3.6 -0.6 0.45 0.45 -0.6 0.8 0.4 0.4 1.75 0.9 0.9 2.2 0.4 0.4 0.2 0.2 -0.7 12 12 +0.6 0.55 0.55 +0.6 1.2 0.6 0.6 0.4 +0.7 5.0 4.0 -0.7 0.45 0.45 -0.7 0.8 0.45 0.45 1.75 0.9 0.9 2.2 0.4 0.4 0.2 0.2 -0.7 12 12 +0.7 0.55 0.55 +0.7 1.2 0.6 0.6 0.4 +0.7 5.0 5.0 -0.7 0.45 0.45 -0.7 0.8 0.45 0.45 1.75 1.0 1.0 2.2 0.4 0.4 0.2 0.2 -0.7 12 12 +0.7 0.55 0.55 +0.7 1.2 0.6 0.6 0.45 +0.7 6.0 6.0 -0.7 0.45 0.45 -0.7 0.8 0.45 0.45 1.75 1.0 1.0 2.2 0.4 0.4 0.2 0.2 -0.7 12 12 +0.7 0.55 0.55 +0.7 1.2 0.6 0.6 0.45 +0.7 ns tCK tCK ns tCK ns ns ns ns ns ns tCK tCK tCK tCK ns ns Max 12 12 Min 7.5 6.0 -4 Max 12 12 Min 7.5 6.0 -5 Max 12 12 Min 7.5 6.0 -6 Max 12 12 ns Parameter CL2 CL2.5 Clock Period Symbol Unit tLZ -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 6/50 ESMT AC Timing Parameter & Specifications - continued Parameter Symbol -3.6 Min tCLmin or tCHmin tHP-0.4 11 16 18 5 4 4 3 15 2 1 0.25 0.4 0.9 0.4 0 2 200 75 (tWR/tCK) +(tRP/tCK) Max 120K ns 7.8 0.6 1.1 0.6 Min tCLmin or tCHmin tHP-0.45 10 15 17 5 4 4 3 15 2 1 0.25 0.4 0.9 0.4 0 2 200 75 (tWR/tCK) +(tRP/tCK) -4 Max 120K ns 7.8 0.6 1.1 0.6 Min tCLmin or tCHmin tHP-0.45 8 12 14 4 4 4 2 15 2 1 0.25 0.4 0.9 0.4 0 2 200 75 (tWR/tCK) +(tRP/tCK) -5 M13S128324A -6 Max 120K ns 7.8 0.6 1.1 0.6 Min tCLmin or tCHmin tHP-0.5 7 10 12 3 3 3 2 15 2 1 0.25 0.4 0.9 0.4 0 2 200 75 (tWR/tCK) +(tRP/tCK) Max 120K ns 7.8 0.6 1.1 0.6 - Unit Half Clock Period DQ-DQS output hold time ACTIVE to PRECHARGE command Row Cycle Time AUTO REFRESH Row Cycle Time ACTIVE to READ,WRITE delay PRECHARGE command period ACTIVE to READ with AUTOPRECHARGE command ACTIVE bank A to ACTIVE bank B command Write recovery time Write data in to READ command delay Col. Address to Col. Address delay Average periodic refresh interval Write preamble Write postamble DQS read preamble DQS read postamble Clock to DQS write preamble setup time Load Mode Register / Extended Mode register cycle time Exit self refresh to READ command Exit self refresh to non-READ command Autoprecharge write recovery+Precharge time tHP tQH tRAS tRC tRFC tRCD tRP tRAP tRRD tWR tWTR tCCD tREFI tWPRE tWPST tRPRE tRPST tWPRES tMRD tXSRD tXSNR tDAL ns ns tCK tCK tCK tCK tCK tCK tCK ns tCK tCK us tCK tCK tCK tCK ns tCK tCK ns tCK Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 7/50 ESMT Command Truth Table COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit L H H Auto Precharge Enable Auto Precharge Disable H Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No Operation Command L H H X H L H H H H L H X X L H L L L H L X H L H L H L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X X L H L L X CKEn-1 CKEn CS H H H X X H L H X X L H L L H X L H H X H L H X H H X X X L L L RAS L L L CAS L L L WE M13S128324A DM X X X BA0,1 A8/AP OP CODE OP CODE X A11~A9, A7~A0 Note 1,2 1,2 3 L L H 3 3 3 4 4 4 4,6 7 X 5 X V V H L V H X V X L H X Row Address L Column Address Column Address Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable Active Power Down X X V X X X 8 (V = Valid, X = Don’t Care, H = Logic High, L = Logic Low) Note: 1. OP Code: Operand Code. A0~A11 & BA0~BA1: Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 1 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by “Auto”. Auto/self refresh can be issued only at all banks precharge state. 4. BA0~BA1: Bank select addresses. If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected. If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected. If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected. 5. If A8/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 8/50 ESMT Basic Functionality Power-Up and Initialization Sequence M13S128324A The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & VREF). 2. Start clock and maintain stable condition for a minimun of 200us. 3. The minimun of 200us after stable power and clock (CLK, CLK ), apply NOP & take CKE high. 4. Issue precharge commands for all banks of the device. *1 5. Issue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the rest address pins, A1~A11 and BA1) *1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0) *2 7. Issue precharge commands for all banks of the device. 8. Issue 2 or more auto-refresh commands. 9. Issue a mode register set command with low to A8 to initialize device operation. *1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6 & 7 is regardless of the order. Po w e r u p & I n i t i a l i za t i o n S e q u e n ce 0 CL K CL K Co m ma nd prec harge Al l B a n k s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tR P E M RS tMR D MR S D l l R es et t MR D pre c ha rg e Al l B a n k s t RP 1 s t A uto R ef res h t RF C 2 n d Au t o R ef res h tR FC Mo de Reg ist er Se t tMR D An y C omm and m i n . 20 0 C y c le * When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 9/50 ESMT Mode Register Definition Mode Register Set (MRS) M13S128324A The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0 0 RFU DLL TM CAS Latency BT Burst Length Mode Register A8 0 1 DLL Reset No Yes A7 0 1 Mode Normal Test A3 0 1 Burst Type Sequential Interleave Burst Length CAS Latency BA1 BA0 0 0 0 1 Operating Mode MRS Cycle EMRS Cycle A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserve Reserve 2 3 4 Reserve 2.5 Reserve A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Latency Sequential Interleave Reserve Reserve 2 2 4 4 8 8 Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Note: RFU (Reserved for future use) must stay “0” during MRS cycle. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 10/50 ESMT Burst Address Ordering for Burst Length Burst Length 2 Starting Address (A2, A1,A0) xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 Sequential Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 M13S128324A Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 4 8 DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S32321A also support a weak drive strength option, intended for lighter load and/or point-to-point environments. Mode Register Set 0 CLK CLK *1 1 2 3 4 5 6 7 8 CO MMA ND Precharge Al l Bank s Mode Register Set Any Command tC K t R P* 2 tMRD *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 11/50 ESMT Extended Mode Register Set (EMRS) M13S128324A The extended mode register stores the data enabling or disabling DLL. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS , RAS , CAS , WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2~A5, A7~A11 and BA1 in the same cycle as CS , RAS , CAS and WE going low is written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched impedance. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0 1 RFU: Must be set “0” D.I.C RFU: Must be set “0” D.I.C DLL Extended Mode Register A6 0 0 1 1 A1 0 1 0 1 Output Driver Impedance Control Normal Weak RFU Matched Impedance A0 0 1 DLL Enable Enable Disable BA1 0 0 BA0 0 1 Operating Mode MRS Cycle EMRS Cycle Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 12/50 ESMT Precharge M13S128324A The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. Burst Selection for Precharge by Bank address bits A8/AP 0 0 0 0 1 BA1 0 0 1 1 X BA0 0 1 0 1 X Precharge Bank A Only Bank B Only Bank C Only Bank D Only All Banks NOP & Device Deselect The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and NOP the device should finish the current operation when this command is issued. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 13/50 ESMT Row Active M13S128324A The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CLK). The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min). Bank Activation Command Cycle ( CAS Latency = 3) 0 CLK CLK 1 2 Addr ess Ban k A Ro w Ad d r . Ban k A Col. Add r . Bank B Ro w Ad d r . Ban k A Ro w . Ad d r . RAS-CAS d el ay (tRCD) RAS-RAS d el ay (tRRD) Bank B Act ivat e NOP Bank A Act ivat e Command Ban k A Activate NOP Write A wi th Au t o Precharg e ROW Cycle Time (tRC) : Don't Care Read Bank This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command. Write Bank This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 14/50 ESMT Essential Functionality for DDR SDRAM Burst Read Operation M13S128324A Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst (Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM until the burst length is completed. 0 CL K CL K 1 2 3 4 5 6 7 8 CO M M A N D READ A N OP NO P NOP NO P N OP N OP N OP NO P D QS C AS L at enc y =3 DQ ' s D o u t0 Do u t 1 Do u t2 D o u t3 Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 15/50 ESMT Burst Write Operation M13S128324A The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. 0 CLK CLK 1 2 3 4 5 6 7 8 CO MM AND NO P W RITE NOP tDSH tDQSS NOP NOP NOP NOP NOP NOP tDSS DQS tWPRES Din1 Din2 tWPST DQ's Din0 Din3 Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 16/50 ESMT Read Interrupted by a Read M13S128324A A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock. 0 CLK CLK 1 2 3 4 5 6 7 8 COMMAND READ A READ B NO P NOP NO P NO P NOP NOP NO P DQS CAS Latency= 3 DQ's Dou t A 0 Dou t A 1 Dou t B 0 Dou t B 1 Dout B 2 Dou t B 3 tCCD Read Interrupted by a Write & Burst Stop To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the write operation, Burt stop command must be applied at least RU(CL) clocks ［RU means round up to the nearest integer］ before the Write command. 0 CLK CLK 1 2 3 4 5 6 7 8 COMMAND READ Bu r st S t op NOP NO P W RITE NO P NOP NOP NOP DQS CAS Latency= 3 DQ's Dou t 0 Dou t 1 Din 0 Din 1 Din 2 Din 3 Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 17/50 ESMT Read Interrupted by a Precharge M13S128324A A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency. 0 CLK CLK 1tCK COMMAND READ Prech arg e 1 2 3 4 5 6 7 8 NO P NOP NOP NOP NOP NOP NOP DQS CAS Latency= 3 DQ's Dou t 0 Dou t 1 Dou t 2 Dou t 3 Dou t 4 Dou t 5 Dou t 6 Dou t 7 Int erru pt ed by precharg e When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS precharge time). 2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after tRP. 3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above. 4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 18/50 ESMT Write Interrupted by a Write M13S128324A A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 0 CLK CL K 1tCK C OMM AN D N OP WR IT E A WR IT E B N OP NO P N OP NO P N OP N OP 1 2 3 4 5 6 7 8 D QS D Q's tCCD D in A 0 D in A 1 Di n B 0 D in B 1 Di n B 2 D in B 3 The following functionality establishes how a Write command may interrupt a Read burst. 1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer]. 2. It is illegal for a Write command to interrupt a Read with autoprecharge command. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 19/50 ESMT Write Interrupted by a Read & DM M13S128324A A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command. 0 CLK CLK 1 2 3 4 5 6 7 8 COMM AND NO P W RITE NO P NOP NOP tWTR Rea d NOP NO P NOP tDQSSmax DQ S CAS Latency= 3 DQ's tDQSSmin DQ S tWPRES CAS Latency= 3 DQ's Din 0 Din 1 Din 2 tWPRES Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dou t 0 Dou t 1 tWTR Din 3 Din 4 Din 5 Din 6 Din 7 Dou t 0 Dou t 1 DM The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the memory. 1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay is 1 clock cycle is disallowed. 2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation. 3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the SDRAM drives them during a read operation. 4. If input Write data is masked by the Read command, the DQS inputs are ignored by the SDRAM. 5. It is illegal for a Read command interrupt a Write with autoprecharge command. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 20/50 ESMT Write Interrupted by a Precharge & DM M13S128324A A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM. 0 CLK CLK 1 2 3 4 5 6 7 8 COMM AND NOP WRITE A NOP tDQSSmax NOP NOP NOP Precharge WRITE B NOP DQS tWR DQ's tDQSSmin DQS Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 tWR DQ's Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 Dinb1 DM Precharge timing for Write operations in DRAMs requires enough time to allow “Write recovery” which is the time required by a DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used to indicate the required of time between the last valid write operation and a Precharge command to the same bank. The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the SDRAM, the data path is eventually synchronizes with the address path by switching clock domains from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain. tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge that strobes in the precharge command. 1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write recovery is defined by tWR. 2. When a precharge command interrupts a Write burst operation, the data mask pin, DQ, is used to mask input data during the time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above. 4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 21/50 ESMT Burst Stop M13S128324A The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock (CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation. 0 CL K CL K 1 2 3 4 5 6 7 8 C OMMAN D READ A B u rs t S t op N OP N OP N OP N OP N OP N OP N OP D QS C A S Lat e n cy = 3 D Q' s Do u t 0 Do u t 1 The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required. 1. 2. 3. 4. 5. 6. The BST command may only be issued on the rising edge of the input clock, CLK. BST is only a valid command during Read burst. BST during a Write burst is undefined and shall not be used. BST applies to all burst lengths. BST is an undefined command during Read with autoprecharge and shall not be used. When terminating a burst Read command, the BST command must be issued LBST ( “BST Latency”) clock cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations. 7. When the burst terminates, the DQ and DQS pins are tristated. The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s). Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 22/50 ESMT DM masking M13S128324A The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe. 0 CLK CLK 1 2 3 4 5 6 7 8 CO MM AND W RITE NO P NO P NOP NOP NO P NOP NOP NOP DQS tDQSS DQ's Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 DM masked by DM = H Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 23/50 ESMT Read With Auto Precharge M13S128324A If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time (tRP) has been satisfied CL K C LK 0 1 2 3 4 5 6 7 8 C O M M A ND Ba nk A A CT I VE N OP t R AP R ea d A A ut o P re cha rg e N OP N OP N OP N OP N OP N OP D QS C A S Lat en cy = 3 D Q' s D o ut 0 Do u t 1 Do u t 2 Do u t 3 At burst read / write with auto precharge, CAS interrupt of the same bank is illegal. Write with Auto Precharge If A8 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). 0 CLK CLK 1 2 3 4 5 6 7 8 COMM AND Ban k A ACTIVE NO P W r i te A Auto Pr ec har g e NOP NO P NO P NO P NOP NOP DQ S *B an k c an be reac t ivat ed at com p let ion of t RP DQ's Dout 0 Dout 1 Dout 2 Dout 3 tWR In te rn al p re ch ar g e s tar t tRP Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 24/50 ESMT Auto Refresh & Self Refresh Auto Refresh M13S128324A An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of the clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tRFC(min). CLK CLK COMMAND PRE Au t o Refresh CMD CKE = High tRP tRFC Self Refresh A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSRD for locking of DLL. CLK CLK COMM AND Sel f Ref resh Au to Refresh Rea d CKE tXSNR tXSRD Note : After self refresh exit, input an auto refresh command immediately. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 25/50 ESMT Power Down M13S128324A Power down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CLK, CLK and CKE. For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur before a READ command can be issued. However, power-down duration is limited by the refresh requirements of the device, so in most applications, the self-refresh mode is preferred over the DLL disable power-down mode. In the power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later. CLK CLK tIS CKE tIS COMM AND VALID NOP NOP VALID No c ol um n ac es s Ent er p ow er - dow n in pr ogr am m ode Exi t po w e r - do w n m ode Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 26/50 ESMT Functional Truth Table. Current CS H L L IDLE L L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L L L L L H H L L L H L H L BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add WRITE / WRITEA Active PRE / PREA Refresh MRS RAS X H H H L L L L X H H H H L L L L X H H H CAS X H H L H H L L X H H L L H H L L X H H L WE M13S128324A Address X X BA BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 Command DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / READA NOP NOP ILLEGAL*2 ILLEGAL*2 Action X H L X H L H L X H L H L H L H L X H L H Bank Active, Latch RA NOP*4 AUTO-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto -precharge Begin Write, Latch CA, Determine Auto -precharge Bank Active/ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 ILLEGAL Bank Active/ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 27/50 ESMT Current State CS H L L L RAS X H H H CAS X H H L WE M13S128324A Address X X BA BA, CA, A8 Command DESEL NOP Burst Stop READ/READA Action NOP (Continue Burst to end) NOP (Continue Burst to end) ILLEGAL Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA, Begin new Write, Determine Auto-Precharge*3 Bank Active/ILLEGAL*2 Terminal Burst Precharge ILLEGAL ILLEGAL NOP (Continue Burst to end) NOP (Continue Burst to end) ILLEGAL READ*7 ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL Write Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL With DM=High, X H L H WRITE L L L L L H L L H L L L L X H H H H L L L L X H H H H L L L L L H H L L X H H L L H H L L X H H L L H H L L L H L H L X H L H L H L H L X H L H L H L H L BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add WRITE/WRITEA Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS READ with AUTO PRECHARGE L L L L L L H L L WRITE with AUTO PRECHARGE L L L L L L Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 28/50 ESMT Current State CS H L L PRE-CHARGIN G L L L L L H L L ROW ACTIVATING L L L L L H L L L WRITE RECOVERING L L L L L RAS X H H H L L L L X H H H L L L L X H H H H L L L L CAS X H H L H H L L X H H L H H L L X H H L L H H L L WE M13S128324A Address X X BA BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add Command DESEL NOP Burst Stop READ/WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (ROW Active after tRCD) NOP (ROW Active after tRCD) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2 ILLEGAL*2 WRITE ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL X H L X H L H L X H L X H L H L X H L H L H L H L Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 29/50 ESMT Current State CS H L L RE-FRESHING L L L L L H L L MODE REGISTER SETTING L L L L L ABBREVIATIONS: RAS X H H H L L L L X H H H L L L L CAS X H H L H H L L X H H L H H L L WE M13S128324A Address X X BA BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add Command DESEL NOP Burst Stop READ/WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL X H L X H L H L X H L X H L H L H = High Level, L = Low level, V = Valid, X = Don’t Care BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation Note: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the bank. 3. Must satisfy bus contention, bus turn around and write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL of any bank is not idle. 6. Same bank’s previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be performed. 7. Refer to “Read with Auto Precharge: for more detailed information. ILLEGAL = Device operation and / or data integrity are not guaranteed. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 30/50 ESMT Current State CKE n-1 H L L SELF-REFRESHING*1 L L L L H POWER DOWN L L H H H ALL BANKS IDLE*2 H H H H L H ANY STATE other than listed above CKE n X H H H H H L X H L H L L L L L L L H CS X H L L L L X X X X X L H L L L L L X RAS X X H H H L X X X X X L X H H H L X X CAS X X H H L X X X X X X L X H H L X X X WE M13S128324A Add X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh Exit Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down (Idle after tPDEX) NOP (Maintain Power Down) Refer to Function True Table Enter Self-Refresh Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function True Table Action X X H L X X X X X X X H X H L X X X X ABBREVIATIONS: H = High Level, L = Low level, V = Valid, X = Don’t Care Note: 1. CKE Low to High transition will re-enable CLK, CLK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from All Bank Idle state. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 31/50 ESMT Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3) tCH tCH tCK 0 CLK CLK 1 2 3 4 5 6 7 M13S128324A 8 9 10 tHP Note1 HIGH CKE CS tIS tIH RAS CAS BA0,BA1 BAa BAb A8/AP ADDR (A0~An) BAa Cb WE DQS tDQSCK tRPRE tDQSCK tDQSQ tRPST Hi-Z tDQSS tWPRE tAC Da2 Da3 tLZ DQ Da0 Da1 tHZ Hi-Z tDQSL tDQSH tWPRES tDS tDH tDS tDH Db0 Db1 Db2 tWPST Hi-Z Db3 Hi-Z tQH DM CO MMA ND READ WRITE Note: 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 32/50 ESMT Multi Bank Interleaving READ (@ BL=4, CL=3) M13S128324A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 33/50 ESMT Multi Bank Interleaving WRITE (@ BL=4) M13S128324A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 34/50 ESMT Read with Auto Precharge (@ BL=8) M13S128324A Note: 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 35/50 ESMT Write with Auto Precharge (@ BL=8) 0 CLK CLK 1 2 3 4 5 6 7 M13S128324A 8 9 10 HIGH CKE CS RAS CAS BA0,BA1 BAa BAa A8/AP Ra ADDR (A0~An) Ca Ra WE tDAL tWR DQS Auto prechar ge start No te1 tRP DQ Qa0 Qa1 Qa2 Qa3 Qa 4 Qa5 Qa6 Qa7 DM CO MMAND WRITE ACTIVE Note: 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 36/50 ESMT Read Interrupted by Precharge (@ BL=8) M13S128324A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 37/50 ESMT Read Interrupted by a Read (@ BL=8, CL=3) M13S128324A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 38/50 ESMT Read Interrupted by a Write & Burst stop (@ BL=8, CL=3) M13S128324A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 39/50 ESMT Write followed by Precharge (@ BL=4) M13S128324A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 40/50 ESMT Write Interrupted by Precharge & DM (@ BL=8) M13S128324A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 41/50 ESMT Write Interrupted by a Read (@ BL=8, CL=3) M13S128324A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 42/50 ESMT DM Function (@ BL=8) only for write M13S128324A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 43/50 ESMT Power up & Initialization Sequence 0 CLK CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 M13S128324A 16 17 18 19 20 CKE Hi gh le vel is re quired CS RAS CAS WE BA0 BA1 A8/AP A7 ADDRE SS KEY A1~A6 A0 High-Z DQ Minimum 200 Cycle tRP High-Z DQS Precha rge All Bank E MRS DLL Enable tRP tRC tRC Min imu m of 2 Refre sh Cycles are requ ire d Pre cha rge All Bank 1st Auto Refresh MRS DLL Reset 2nd Auto Refresh Any Command Mode Resister Set (P ower & Cl ock must be stable for 200us before Precharge All Bank) : Don't Care Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 44/50 ESMT Mode Register Set 0 CLK CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 M13S128324A 16 17 18 19 tCK CKE CS RAS CAS WE BA0,BA1 A8/AP ADDRESS KEY ADDR (A0~An) DM tRP High-Z DQ tMRD High-Z DQS Pre cha rg e Command All Bank Any Command Mode Register Set Command Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 45/50 ESMT Simplified State Diagram Power Applied Power On M13S128324A Precharge PREALL Self Refresh REFSX MRS EMRS MRS Idle REF A Auto Refresh REFS CKEL CKEH Active Power Down ACT Precharge PowerDown CKEH CKEL Burst Stop Bank Active Write Write Write A Write Read A Read Read Read Read Write A Read A PRE Write A PRE PRE Read A Read A PRE Precharge PREALL Automatic Sequence Command Sequence PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh Elite Semiconductor Memory Technology Inc. CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge Publication Date : Jul. 2009 Revision : 2.3 46/50 ESMT PACKING 144-BALL DIMENSIONS FBGA DDR DRAM (12x12mm) M13S128324A Symbol A A1 Φb D E D1 E1 e aaa bbb ddd eee fff MD/ME Dimension in mm Min Norm Max 1.14 1.40 0.30 0.35 0.40 0.40 0.45 0.50 11.90 12.00 12.10 11.90 12.00 12.10 8.80 8.80 0.80 0.10 0.10 0.12 0.15 0.08 12/12 Dimension in inch Min Norm Max 0.049 0.055 0.012 0.014 0.016 0.016 0.018 0.020 0.469 0.472 0.476 0.469 0.472 0.476 0.346 0.346 0.031 0.004 0.004 0.005 0.004 0.006 12/12 Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 47/50 ESMT PACKING 100-LEAD DIMENSIONS LQFP DDR SDRAM(14x20mm) M13S128324A D D1 80 81 51 50 C C1 b b1 WITH PLATING BASE METAL SEC : B-B E1 F F 100 1 e 30 GAGE PLANE 31 b E B B L L1 A2 A -C- SEATING PLANE SEC : F-F A1 y -C- Symbol A A1 A2 b b1 c c1 D D1 E E1 e y L L1 θ° Dimension in inch Min Norm Max 0.063 0.002 0.006 0.053 0.055 0.057 0.009 0.013 0.015 0.009 0.012 0.013 0.004 0.008 0.004 0.006 0.860 0.866 0.872 0.783 0.787 0.791 0.624 0.630 0.636 0.547 0.551 0.555 0.026 BSC 0.004 0.018 0.024 0.030 0.039 REF 00 3.50 70 Dimension in mm Min Norm Max 1.60 0.05 0.15 1.35 1.40 1.45 0.22 0.32 0.38 0.22 0.30 0.33 0.09 0.20 0.09 0.16 21.85 22.00 22.15 19.90 20.00 20.10 15.85 16.00 16.15 13.90 14.00 14.10 0.65 BSC 0.10 0.45 0.60 0.75 1.00 REF 00 3.50 70 Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 48/50 ESMT Revision History Revision 0.1 0.2 Date 2005.05.13 2005.08.08 Original Description M13S128324A 1. Delete Non-Pb-free of ordering information 2. Modify typing error of Pin Arrangement 1. Delete “Preliminary” at every page 2. Modify tWR from 2clk to 15ns 3. Modify tWTR from 1clk to 2clk Add -4BG spec (only for CL4) Add 100 pin LQFP package Delete BGA ball name of packing dimensions Add -3.6 speed grade Add -4(CL3) specification 1. Modify A10 to A8 on P26 2. Modify the figure on P37 Modify -4(CL3) VDD; VDDQ spec Modify PD spec Modify the description about EMRS Modify 100 Lead LQFP packing dimension Correct some type errors Add Simplified State Diagram 1. Move Revision History to the last 2. Add the specification of VIN and VID 3. Modify the specification of II 4. Add a note of self refresh operation 5. Correct Burst Length 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2006.03.08 2006.10.25 2006.11.16 2007.03.02 2007.03.12 2007.03.22 2007.03.29 2007.04.17 2007.05.02 2007.06.22 2007.08.30 2008.01.09 2008.04.07 2.3 2009.07.02 Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 49/50 ESMT Important Notice All rights reserved. M13S128324A No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2009 Revision : 2.3 50/50