M13S5121632A

ESMT DDR SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2; 2.5; 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE Data mask (DM) for write masking only VDD, VDDQ = 2.5V ~ 2.7V Auto & Self refresh 7.8us refresh interval (64ms refresh period, 8K cycle) SSTL-2 I/O interface 66pin TSOPII package M13S5121632A 8M x 16 Bit x 4 Banks Double Data Rate SDRAM Ordering information: PRODUCT ID M13S5121632A -5TG MAX FREQ 200MHz VDD 2.5V PACKAGE TSOPII COMMENTS Pb-free Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 1/47 ESMT Functional Block Diagram M13S5121632A DQ0 - 15 UDQS, LDQS DLL I/O Buffer DQS Buffer Memory Array Bank#0 Memory Array Bank#1 Memory Array Bank#2 Memory Array Bank#3 Mode Register Control Circuitry Address Buffer Clock Buffer A0-12 BA0,1 CLK CLK CKE Control Signal Butter CS RAS CAS WE DM Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 2/47 ESMT Pin Arrangement M13S5121632A x1 6 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 x 16 V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 NC V SSQ UDQS NC V REF V SS UDM CLK CLK CKE NC A 12 A 11 A9 A8 A7 A6 A5 A4 V SS 66 PIN TSOP(II) (400mil x 875mil) (0.65 mm PIN PITCH) Pin Description Pin Name Function Address inputs - Row address A0~A12 - Column address A0~ A9 A10/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power Bi-directional Data Strobe. LDQS corresponds to the data on DQ0~DQ7; UDQS correspond to the data on DQ8~DQ15. Pin Name Function DM is an input mask signal for write data. LDM corresponds to the data on DQ0~DQ7; UDM correspond to the data on DQ8~DQ15. Clock input Clock enable Chip select Supply Voltage for GDQ Ground for DQ Reference Voltage for SSTL-2 A0~A12, BA0,BA1 LDM, UDM DQ0~DQ15 RAS CAS WE CLK, CLK CKE CS VDDQ VSSQ VREF NC VSS VDD LDQS, UDQS No connection Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 3/47 ESMT Absolute Maximum Rating Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSSQ Storage temperature Power dissipation Short circuit current Note : Symbol VIN, VOUT VDD VDDQ TSTG PD IOS Value -0.5 ~ VDDQ + 0.5 -0.5 ~ 3.7 -0.5 ~ 3.7 -55 ~ +150 1500 50 M13S5121632A Unit V V V °C mW mA Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operation Condition & Specifications DC Operation Condition Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 °C ) Parameter Supply voltage I/O Supply voltage I/O Reference voltage I/O Termination voltage (system) Input logic high voltage Input logic low voltage Input Voltage Level, CLK and CLK inputs Input Differential Voltage, CLK and CLK inputs Input leakage current Output leakage current Output High Current (Normal strength driver) (VOUT =VDDQ-0.373V, min VREF, min VTT) Output Low Current (Normal strength driver) (VOUT = 0.373V) Symbol VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) II IOZ IOH IOL Min 2.5 2.5 0.49*VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 -2 -5 -16.2 +16.2 Max 2.7 2.7 0.51*VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 2 5 Unit V V V V V V V V 3 1 2 Note μA μA mA mA Notes 1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 2. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF . 3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK . Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 4/47 ESMT DC Specifications Parameter Operation Current (One Bank Active) Operation Current (One Bank Active) Precharge Power-down Standby Current Idle Standby Current Active Power-down Standby Current Active Standby Current Operation Current (Read) Operation Current (Write) Auto Refresh Current Self Refresh Current Operation Current (Four Bank Operation) Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Test Condition tRC = tRC (min), tCK = tCK (min), Active – Precharge Burst Length = 2, tRC = tRC (min), CL= 2.5, IOUT = 0mA, Active-Read- Precharge CKE ≤ VIL(max), tCK = tCK (min), All banks idle CKE ≥ VIH(min), CS ≥ VIH(min), tCK = tCK (min) All banks ACT, CKE ≤ VIL(max), tCK = tCK (min) One bank; Active-Precharge, tRC = tRAS(max), tCK = tCK (min) Burst Length = 2, CL= 2.5, tCK = tCK (min), IOUT = 0 mA Burst Length = 2, CL= 2.5, tCK = tCK (min) tRC ≥ tRFC(min) CKE ≤ 0.2V Four bank interleaving with BL=4, tRC = tRC (min), burst mode; Read with auto precharge; Address and control inputs on NOP edge are not changing. IOUT = 0 mA M13S5121632A Version -5 180 210 10 55 45 60 460 360 290 6 mA mA mA mA mA mA mA mA mA mA 1 Unit Note IDD7 630 mA Note 1. Enable on-chip refresh and address counters. AC Operation Conditions & Timing Specification AC Operation Conditions Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Different Voltage, CLK and CLK inputs Input Crossing Point Voltage, CLK and CLK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 Max Unit V V V V 1 2 Note Note 1. VID is the magnitude of the difference between the input level on CLK and the input on CLK . 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Input / Output Capacitance (VDD = 2.5V~2.7V, VDDQ = 2.5V~2.7V, TA = 25 °C , f = 1MHz) Parameter Input capacitance (A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE ) Input capacitance (CLK, CLK ) Data & DQS input/output capacitance Input capacitance (DM) Symbol CIN1 CIN2 COUT CIN3 Min 2.0 2.0 4.0 4.0 Max 3.5 3.5 5.0 5.0 Unit pF pF pF pF Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 5/47 ESMT AC Operating Test Conditions Parameter Input reference voltage for clock (VREF) Input signal maximum peak swing Input signal minimum slew rate Input levels (VIH/VIL) Input timing measurement reference level Output timing reference level Value 0.5*VDDQ 1.5 1.0 VREF+0.31/VREF-0.31 VREF VTT M13S5121632A Unit V V V/ns V V V AC Timing Parameter & Specifications (VDD = 2.5V~2.7V, VDDQ= 2.5V~2.7V, TA =0 °C ~ 70 °C ) -5 min CL2 Clock Period CL2.5 CL3 Access time from CLK/ CLK CLK high-level width CLK low-level width Data strobe edge to clock edge Clock to first rising edge of DQS delay Data-in and DM setup time (to DQS) Data-in and DM hold time (to DQS) DQ and DM input pulse width (for each input) Input setup time Input hold time DQS input high pulse width DQS input low pulse width DQS falling edge to CLK rising-setup time DQS falling edge from CLK rising-hold time Parameter Symbol 7.5 tCK 6.0 5.0 tAC tCH tCL tDQSCK tDQSS tDS tDH tDIPW tIS tIH tDQSH tDQSL tDSS tDSH tDQSQ tHZ tLZ -0.7 0.45 0.45 -0.6 0.75 0.5 0.5 1.75 0.9 0.9 0.35 0.35 0.2 0.2 -0.7 -0.7 Unit max 13 13 10 +0.7 0.55 0.55 +0.6 1.25 0.40 +0.7 +0.7 ns tCK tCK ns tCK ns ns ns ns ns tCK tCK tCK tCK ns ns ns ns Note 5 5 Data strobe edge to output data edge Data-out high-impedance window from CLK/ CLK Data-out low-impedance window from CLK/ CLK 1 1 Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 6/47 ESMT AC Timing Parameter & Specifications-continued Parameter Half Clock Period DQ-DQS output hold time Data hold skew factor ACTIVE to PRECHARGE command Row Cycle Time AUTO REFRESH Row Cycle Time ACTIVE to READ,WRITE delay PRECHARGE command period ACTIVE bank A to ACTIVE bank B command Write recovery time Write data in to READ command delay Average periodic refresh interval Write preamble Write postamble DQS read preamble DQS read postamble Clock to DQS write preamble setup time Load Mode Register / Extended Mode register cycle time Exit self refresh to READ command Exit self refresh to non-READ command Autoprecharge write recovery+Precharge time Symbol tHP tQH tQHS tRAS tRC tRFC tRCD tRP tRRD tWR tWTR tREFI tWPRE tWPST tRPRE tRPST tWPRES tMRD tXSRD tXSNR tDAL -5 min tCLmin or tCHmin tHP-tQHS 40 55 70 15 15 10 15 2 0.25 0.4 0.9 0.4 0 10 200 75 30 max 0.5 70K 7.8 0.6 1.1 0.6 Unit ns ns ns ns ns ns ns ns ns ns tCK us tCK tCK tCK tCK ns ns tCK ns ns M13S5121632A Note 4 3 2 Note : 1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ). 2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 5. For command/address and CLK & CLK slew rate > 1.0V/ns. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 7/47 ESMT Command Truth Table COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Self Refresh Entry Exit CKEn-1 CKEn CS H H H L H H X X H L H X X L L L L H L L RAS L L L H X L H CAS L L L H X H L WE M13S5121632A DM X X X X X X BA0,1 A10/AP OP CODE OP CODE X X A11,A12, A9~A0 Note 1,2 1,2 3 3 3 3 4 4 4 4,6 7 L L H H X H H Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Entry Exit Precharge Power Down Mode DM No Operation Command Entry Exit V V Row Address L H Column Address Column Address H H H H L H L H H X X X L H L H L L L H L X H L H L H L H H L X V X X H X V X X H L H H X V X X H X V X H L L L X V X X H X V X H X X X X X X V L H X V X L H X X 5 Active Power Down X X V X X X 8 X (V = Valid, X = Don’t Care, H = Logic High, L = Logic Low) 1. OP Code: Operand Code. A0~A12 & BA0~BA1: Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 1 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatic precharge without row precharge command is meant by “Auto”.. Auto/self refresh can be issued only at all banks precharge state. 4. BA0~BA1: Bank select addresses. If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected. If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected. If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected. 5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 8/47 ESMT Basic Functionality Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & VREF). 2. Start clock and maintain stable condition for a minimun of 200us. M13S5121632A 3. The minimun of 200us after stable power and clock (CLK, CLK ), apply NOP & take CKE high. 4. Issue precharge commands for all banks of the device. *1 5. Issue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the rest address pins, A1~A12 and BA1) *1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0) *2 7. Issue precharge commands for all banks of the device. 8. Issue 2 or more auto-refresh commands. 9. Issue a mode register set command with low to A8 to initialize device operation. *1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6 & 7 is regardless of the order. P o we r u p & In i t i a l i z a t i o n S e q u e n c e CLK CLK Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRP p re c ha rg e A ll B a nk s tRP E MRS MRS Dll Reset p re c ha rg e A ll B a nks 1s t A uto Re f re s h tRFC 2nd A uto Re f re s h tRFC Mode Register Set Any Command min . 200 Cycl e Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 9/47 ESMT Mode Register Definition Mode Register Set (MRS) M13S5121632A The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0 0 0 0 0 0 DLL TM CAS Latency BT Burst Length Mode Register A8 0 1 DLL Reset No Yes A7 0 1 Mode Normal Test A3 0 1 Burst Type Sequential Interleave Burst Length CAS Latency BA1 BA0 0 0 0 1 Operating Mode MRS Cycle EMRS Cycle A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserve Reserve 2 3 Reserve Reserve 2.5 Reserve Latency A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Sequential Interleave Reserve Reserve 2 2 4 4 8 8 Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 10/47 ESMT Burst Address Ordering for Burst Length Burst Length 2 Starting Address (A2, A1,A0) xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 Sequential Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 M13S5121632A Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 4 8 DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. The device also support a weak drive strength option, intended for lighter load and/or point-to-point environments. Mode Register Set 0 CLK CLK *1 1 2 3 4 5 6 7 8 COMMAND Precharg e Al l Ba n k s Mod e Register Set An y Com m an d tCK t R P* 2 *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 11/47 ESMT Extended Mode Register Set (EMRS) M13S5121632A The extended mode register stores the data enabling or disabling DLL. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS , RAS , CAS , WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0~A12 and BA1 in the same cycle as CS , RAS , CAS and WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 RFU : Must be set “0” D.I.C DLL Output Driver Strength Control 0 1 Normal Weak A0 0 1 DLL Enable Enable Disable BA1 0 0 BA0 0 1 Operaing Mode MRS Cycle EMRS Cycle Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 12/47 ESMT Precharge M13S5121632A The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. Burst Selection for Precharge by Bank address bits A10/AP 0 0 0 0 1 BA1 0 0 1 1 X BA0 0 1 0 1 X Precharge Bank A Only Bank B Only Bank C Only Bank D Only All Banks NOP & Device Deselect The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and NOP the device should finish the current operation when this command is issued. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 13/47 ESMT Row Active M13S5121632A The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CLK). The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min). Bank Activation Command Cycle ( CAS Latency = 3) 0 CLK CLK 1 2 Addr ess Ban k A Ro w Ad d r . Ban k A Col. Add r . Bank B Ro w Ad d r . Ban k A Ro w . Ad d r . RAS-CAS d el ay (tRCD) RAS-RAS d el ay (tRRD) Bank B Act ivat e NOP Bank A Act ivat e Command Ban k A Activate NOP Write A wi th Au t o Precharg e ROW Cycle Time (tRC) : Don't Care Read Bank This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command. Write Bank This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 14/47 ESMT Essential Functionality for DDR SDRAM Burst Read Operation M13S5121632A Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst (Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM until the burst length is completed. CL K CL K 0 1 2 3 4 5 6 7 8 CO M M A N D READ A N OP NO P NOP NO P N OP N OP N OP NO P D QS C AS L at enc y =3 DQ ' s D o u t0 Do u t 1 Do u t2 D o u t3 Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 15/47 ESMT Burst Write Operation M13S5121632A The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. 0 CLK CLK 1 2 3 4 5 6 7 8 CO MM AND NO P W RITE NOP tDSH NOP NOP NOP NOP NOP NOP DQS tDQSS tWPRES tDSS tWPST DQ's Din0 Din1 Din2 Din3 Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 16/47 ESMT Read Interrupted by a Read M13S5121632A A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock. 0 CLK CLK 1 2 3 4 5 6 7 8 COMMAND READ A READ B NOP NOP NOP NOP NOP NOP NOP DQS CAS Latency=3 DQ's D o u t A 0 D o u t A 1 D o u t B 0 D ou t B 1 D o u t B 2 D o u t B 3 Read Interrupted by a Write & Burst Stop To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the write operation, Burt stop command must be applied at least RU(CL) clocks ［RU means round up to the nearest integer］ before the Write command. CLK CLK 0 1 2 3 4 5 6 7 8 COMMAND READ Bu r st S t op NOP NO P W RITE NO P NOP NOP NOP DQS CAS Latency= 3 DQ's Dou t 0 Dou t 1 Din 0 Din 1 Din 2 Din 3 Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 17/47 ESMT Read Interrupted by a Precharge M13S5121632A A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency. 0 1 2 3 4 5 6 7 8 CLK CLK 1tCK COMMAND READ Prech arg e NO P NOP NOP NOP NOP NOP NOP DQS CAS Latency= 3 DQ's Dou t 0 Dou t 1 Dou t 2 Dou t 3 Dou t 4 Dou t 5 Dou t 6 Dou t 7 Int erru pt ed by precharg e When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS precharge time). 2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after tRP. 3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above. 4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 18/47 ESMT Write Interrupted by a Write M13S5121632A A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 0 CLK CLK 1tCK COMM AND NO P WRITE A WRITE B NO P NO P NO P NO P NOP NOP 1 2 3 4 5 6 7 8 DQ S DQ's Din A 0 Din A 1 Din B 0 Din B 1 Din B 2 Din B 3 The following functionality establishes how a Write command may interrupt a Read burst. 1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer]. 2. It is illegal for a Write command to interrupt a Read with autoprecharge command. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 19/47 ESMT Write Interrupted by a Read & DM M13S5121632A A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command. 0 CLK CLK 1 2 3 4 5 6 7 8 COMM AND NO P W RITE NO P NOP NOP tWTR Rea d NOP NO P NOP tDQSSmax DQ S CAS Latency= 3 DQ's tDQSSmin DQ S CAS Latency= 3 DQ's tWPRES Din 0 Din 1 Din 2 tWPRES Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dou t 0 Dou t 1 tWTR Din 3 Din 4 Din 5 Din 6 Din 7 Dou t 0 Dou t 1 DM The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the memory. 1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay is 1 clock cycle is disallowed. 2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation. 3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the SDRAM drives them during a read operation. 4. If input Write data is masked by the Read command, the DQS inputs is ignored by the SDRAM. 5. It is illegal for a Read command interrupt a Write with autoprecharge command. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 20/47 ESMT Write Interrupted by a Precharge & DM M13S5121632A A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM. 0 1 2 3 4 5 6 7 8 CLK CLK COMM AND NOP WRITE A NOP tDQSSmax NOP NOP NOP Precharge WRITE B NOP DQS tWR DQ's tDQSSmin DQS Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 tWR DQ's Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 Dinb1 DM Precharge timing for Write operations in DRAMs requires enough time to allow “Write recovery” which is the time required by a DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used to indicate the required of time between the last valid write operation and a Precharge command to the same bank. The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the SDRAM, the data path is eventually synchronizes with the address path by switching clock domains from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain. tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge that strobes in the precharge command. 1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write recovery is defined by tWR. 2. When a precharge command interrupts a Write burst operation, the data mask pin, DQ, is used to mask input data during the time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above. 4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 21/47 ESMT Burst Stop M13S5121632A The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock (CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation. 0 1 2 3 4 5 6 7 8 CL K CL K C OMMAN D READ A B u rs t S t op N OP N OP N OP N OP N OP N OP N OP D QS C A S Lat e n cy = 3 D Q' s Do u t 0 Do u t 1 The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required. 1. 2. 3. 4. 5. 6. The BST command may only be issued on the rising edge of the input clock, CLK. BST is only a valid command during Read burst. BST during a Write burst is undefined and shall not be used. BST applies to all burst lengths. BST is an undefined command during Read with autoprecharge and shall not be used. When terminating a burst Read command, the BST command must be issued LBST ( “BST Latency”) clock cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations. 7. When the burst terminates, the DQ and DQS pins are tristated. The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s). Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 22/47 ESMT DM masking M13S5121632A The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe. 0 CLK CLK 1 2 3 4 5 6 7 8 CO MM AND W RITE NO P NO P NOP NOP NO P NOP NOP NOP DQS tDQSS DQ's Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 DM masked by DM = H Read With Auto Precharge If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time (tRP) has been satisfied C LK C LK 0 1 2 3 4 5 6 7 8 CO MMA ND B a nk A AC T I VE NO P Re a d A Au to Pr e ch ar g e NO P N OP NO P NO P N OP NO P D QS C A S L a t e n cy = 3 DQ 's D out 0 D out 1 D ou t 2 D out 3 At burst read / write with auto precharge, CAS interrupt of the same bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 23/47 ESMT Write with Auto Precharge M13S5121632A If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). 0 CLK CLK 1 2 3 4 5 6 7 8 COMM AND Ban k A ACTIVE NO P W r i te A Auto Pr ec har g e NOP NO P NO P NO P NOP NOP DQ S *B an k c an be reac t ivat ed at com p let ion of t RP DQ's Dout 0 Dout 1 Dout 2 Dout 3 tWR In te rn al p re ch ar g e s tar t tRP Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of the clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tRFC(min). CLK CLK COMMAND PRE Au t o Refresh CMD CKE = High tRP tRFC Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 24/47 ESMT Self Refresh M13S5121632A A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSRD for locking of DLL. CLK CLK COMM AND Sel f Ref resh Au to Refresh Rea d CKE tXSNR tXSRD Note: 8K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. Power Down Power down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CLK, CLK and CKE. For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur before a READ command can be issued. However, power-down duration is limited by the refresh requirements of the device, so in most applications, the self-refresh mode is preferred over the DLL disable power-down mode. In the power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later. CLK CLK tIS CKE tIS COMM AND VALID NOP NOP VALID No c ol um n ac es s Ent er p ow er - dow n in pr ogr am m ode Exi t po w e r - do w n m ode Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 25/47 ESMT Functional Truth Table Current CS H L L IDLE L L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L L L L L H H L L L H L H L BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add WRITE / WRITEA Active PRE / PREA Refresh MRS RAS X H H H L L L L X H H H H L L L L X H H H CAS X H H L H H L L X H H L L H H L L X H H L WE M13S5121632A Address X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 Command DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / READA NOP NOP ILLEGAL*2 ILLEGAL*2 Action X H L X H L H L X H L H L H L H L X H L H Bank Active, Latch RA NOP*4 AUTO-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto -precharge Begin Write, Latch CA, Determine Auto -precharge Bank Active/ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 ILLEGAL Bank Active/ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 26/47 ESMT Current State CS H L L L WRITE RAS X H H H CAS X H H L WE M13S5121632A Address X X BA BA, CA, A10 Command DESEL NOP Burst Stop READ/READA Action NOP (Continue Burst to end) NOP (Continue Burst to end) ILLEGAL Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA, Begin new Write, Determine Auto-Precharge*3 Bank Active/ILLEGAL*2 Terminal Burst Precharge ILLEGAL ILLEGAL NOP (Continue Burst to end) NOP (Continue Burst to end) ILLEGAL READ*7 ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL Write Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL With DM=High, X H L H L L L L L H L L H L L L L X H H H H L L L L X H H H H L L L L L H H L L X H H L L H H L L X H H L L H H L L L H L H L X H L H L H L H L X H L H L H L H L BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add WRITE/WRITEA Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS READ with AUTO PRECHARGE L L L L L L H L L WRITE with AUTO PRECHARGE L L L L L L Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 27/47 ESMT Current State CS H L L PRE-CHARGIN G L L L L L H L L ROW ACTIVATING L L L L L H L L L WRITE RECOVERING L L L L L RAS X H H H L L L L X H H H L L L L X H H H H L L L L CAS X H H L H H L L X H H L H H L L X H H L L H H L L WE M13S5121632A Address X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add Command DESEL NOP Burst Stop READ/WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (ROW Active after tRCD) NOP (ROW Active after tRCD) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2 ILLEGAL*2 WRITE ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL X H L X H L H L X H L X H L H L X H L H L H L H L Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 28/47 ESMT Current State CS H L L RE-FRESHING L L L L L H L L MODE REGISTER SETTING L L L L L RAS X H H H L L L L X H H H L L L L CAS X H H L H H L L X H H L H H L L WE M13S5121632A Address X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code Mode-Add Command DESEL NOP Burst Stop READ/WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL X H L X H L H L X H L X H L H L ABBREVIATIONS : H = High Level, L = Low level, V = Valid, X = Don’t Care BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the bank. 3. Must satisfy bus contention, bus turn around and write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL of any bank is not idle. 6. Same bank’s previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be performed. 7. Refer to “Read with Auto Precharge: for more detailed information. ILLEGAL = Device operation and / or data integrity are not guaranteed. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 29/47 ESMT Current State CKE n-1 H L L SELF-REFRESHING* 1 L L L L H POWER DOWN L L H H H ALL BANKS IDLE*2 H H H H L H ANY STATE other than listed above CKE n X H H H H H L X H L H L L L L L L L H CS X H L L L L X X X X X L H L L L L L X RAS X X H H H L X X X X X L X H H H L X X CAS X X H H L X X X X X X L X H H L X X X WE M13S5121632A Add X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh Exit Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down (Idle after tPDEX) NOP (Maintain Power Down) Refer to Function True Table Enter Self-Refresh Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function True Table Action X X H L X X X X X X X H X H L X X X X ABBREVIATIONS : H = High Level, L = Low level, V = Valid, X = Don’t Care Note : 1. CKE Low to High transition will re-enable CLK, CLK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from All Bank Idle state. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 30/47 ESMT Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3) tCL 5 6 7 M13S5121632A tCK 0 CLK CLK 1 2 3 4 8 9 10 tHP HIGH Note1 CKE CS tIS tIH RAS CAS BA0,BA1 BAa BAb A10/ AP ADDR (A0~ An ) BAa Cb WE DQS tDQSCK tRPRE tDQSCK tDQSQ tRPST Hi-Z tDQSS tWPRE tDQSH tDQSL tWPST Hi-Z tLZ DQ Da0 Da1 Da2 tAC Da3 tHZ Hi-Z tWPRES tDS tDH tDS tDH Db0 Db1 Db2 Db3 Hi-Z tQH DM COMMAND READ WRITE Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 31/47 ESMT Multi Bank Interleaving READ (@BL=4, CL=3) M13S5121632A 0 CLK CLK 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS BA0,BA1 BAa BAb BAa BAb A10/AP Ra Rb ADDR (A 0~An) tRRD Ra Rb Ca tRCD Cb WE DQS DQ Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb 2 Qb3 DM t RCD COMMAND ACTIVE ACTIVE READ READ Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 32/47 ESMT Multi Bank Interleaving WRITE (@BL=4) 0 CLK CLK 1 2 3 4 5 6 7 M13S5121632A 8 9 10 CKE HIGH CS RAS CAS BA0,BA1 BAa BAb BAa BAb A10/AP Ra Rb tRRD ADDR (A0~An) Ra Rb Ca tRCD Cb WE DQS DQ Qa0 Qa1 Qa2 Qa 3 Qb0 Qb1 Qb2 Qb3 DM tRCD COMMAND ACTIVE ACTIVE WRITE WRITE Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 33/47 ESMT Read with Auto Precharge (@BL=8) 0 CLK CLK 1 2 3 4 5 6 7 M13S5121632A 8 9 10 CKE HIGH CS RAS CAS BA0,BA1 BAa BAa A10/AP Ra ADDR (A0~ An ) Ca Ra WE Au t o p r e ch ar g e s t a r t tRP Note1 DQS(CL=3) DQ(CL=3) Q a0 Q a1 Qa2 Q a3 Q a4 Q a5 Q a6 Q a7 DM CO MM AND READ ACTIVE Note 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 34/47 ESMT Write with Auto Precharge (@BL=8) M13S5121632A Note 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 35/47 ESMT Read Interrupted by Precharge (@BL=8) 0 CLK CLK HIGH CKE 1 2 3 4 5 6 7 M13S5121632A 8 9 10 CS RAS CAS BA0,BA1 BAa BAb A10/AP ADDR (A0~An) Ca WE DQS(CL=3) DQ(CL=3) Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 DM COMMAND READ PRE CHARGE Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 36/47 ESMT Read Interrupted by a Read (@BL=8, CL=3) 0 CLK CLK HIGH 1 2 3 4 5 6 7 M13S5121632A 8 9 10 CKE CS RAS CAS BA0,BA1 BAa BAb A10/ AP ADDR (A0~An) Ca Cb WE DQS DQ Qa0 Qa1 Qb0 Q b1 Qb2 Qb3 Qb4 Qb5 Qb6 Q b7 DM COMMAND READ READ Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 37/47 ESMT Read Interrupted by a Write & Burst stop (@BL=8, CL=3) 0 CLK CLK HIGH 1 2 3 4 5 6 7 M13S5121632A 8 9 10 CKE CS RAS CAS BA0, BA1 BAa BAb A10/ AP ADDR (A0~ An ) Ca Cb WE DQS DQ Qa0 Q a1 Q b0 Qb1 Q b2 Q b3 Q b4 Qb5 Q b6 Q b7 DM COMMAND READ Burst Stop WRITE Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 38/47 ESMT Write followed by Precharge (@BL=4) 0 CLK CLK 1 2 3 4 5 6 7 M13S5121632A 8 9 10 CKE HIGH CS RAS CAS BA0,BA1 BAa BAa A1 0 / A P ADDR (A0~ An) Ca WE tWR DQS DQ Da0 Da1 Da2 Da3 DM COMMAND WRITE PRE CHARGE Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 39/47 ESMT Write Interrupted by Precharge & DM (@BL=8) 0 CLK CLK 1 2 3 4 0 1 2 M13S5121632A 3 4 5 CKE HIGH CS RAS CAS BA0,BA1 BAa BAa BAb BAc A10 / AP ADDR (A0~ An ) Ca Cb Cc WE DQS DQ Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Dc0 Dc1 Dc2 Dc3 DM tWR COMM AND WRITE PRE CHARGE WRITE WRITE Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 40/47 ESMT Write Interrupted by a Read (@BL=8, CL=3) 0 CLK CLK 1 2 3 4 5 6 7 M13S5121632A 8 9 10 CKE HIGH CS RAS CAS BA0, BA1 BAa BAb A1 0/ AP ADDR (A0~ An ) Ca Cb WE DQ S DQ Da0 Da1 Da2 Da3 Da4 Da5 Q b0 Q b1 Q b2 Qb3 Q b4 Q b5 Ma s k ec d b y D M DM tWTR COMMAND WRITE READ Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 41/47 ESMT DM Function (@BL=8) only for write CLK CLK HIGH 0 1 2 3 4 5 6 7 M13S5121632A 8 9 10 CKE CS RAS CAS BA0,BA1 BAa A10/ AP ADDR (A0~ An) Ca WE DQS( CL= 3 ) DQ(CL=3) Qa0 Q a1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 DM COMMAND WRITE Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 42/47 ESMT Power up & Initialization Sequence CLK CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 M13S5121632A 16 17 18 19 CKE High lev el is re quired CS RAS CAS WE BA0 BA1,A9, A 11 ~ A 1 2 A10/AP A8 A7 ADDRESS KEY A1~A6 A0 High-Z Minimum 200 Cycle DQ tRP DQS Precharge All Bank tMRD tRP tR C tRC H igh-Z EMRS DLL Enable Minimum of 2 Re fresh Cycle s are required Precharge All Bank 1st Auto Refresh 2nd Auto Refresh Any Command Mode Resister Set : Don't Care (Power & Clock must be stable for 2 0 0 u s before precharge All Bank) MRS DLL Reset Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 43/47 ESMT Mode Register Set 0 CLK CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M13S5121632A 15 16 17 18 19 tCK CKE CS RAS CAS WE BA0, BA1 A10 /AP ADDR ESS KEY ADDR (A0~An) DM tRP DQ High-Z tMRD High-Z DQS Precharge Command All Ban k Any Com man d M ode R egis ter Set Command Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 44/47 ESMT PACKING 66-LEAD DIMENSIONS TSOP(II) DRAM(400mil) M13S5121632A Symbol A A1 A2 b b1 c c1 D ZD E E1 e L L1 θ° θ1° Dimension in inch Min Norm Max 0.047 0.002 0.004 0.006 0.037 0.039 0.041 0.009 0.015 0.009 0.012 0.013 0.005 0.008 0.0047 0.005 0.006 0.875 BSC 0.028 REF 0.455 0.463 0.471 0.400 BSC 0.026 BSC 0.016 0.02 0.024 0.031 REF 0° 8° 10° 15° 20° Dimension in mm Norm Max 1.2 0.05 0.1 0.15 0.95 1 1.05 0.22 0.38 0.22 0.3 0.33 0.12 0.21 0.12 0.127 0.16 22.22 BSC 0.71 REF 11.56 11.76 11.96 10.16 BSC 0.65 BSC 0.4 0.5 0.6 0.80 REF 0° 8° 10° 15° 20° Min Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 45/47 ESMT Revision History Revision 1.0 Date 2008.10.06 Original Description M13S5121632A Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 46/47 ESMT Important Notice All rights reserved. M13S5121632A No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008 Revision : 1.0 47/47