M13S64322A

ESMT Revision History Revision 0.5 (May 03, 2007) - Delete BGA ball name of packing dimensions Preliminary M13S64322A Revision 0.4 (May 14,2002) - Change AC Parameters Revision Version tRC tRP -4 13 tCK 4 tCK Rev. 0.3 -5 11 tCK 3 tCK -4 14 tCK 20 ns Rev. 0.4 -5 12 tCK 20 ns Revision 0.3 (December 13,2001) - The Max / Min value of D, D1, E, E1 (LQFP 100L PKG outline dimension) are added. Revision 0.2 (Agu 31,2001) - Changed DC Current Revision Version IDD4R IDD5 -4 330 305 Rev. 0.1 -5 260 -4 385 350 Rev. 0.2 -5 285 Revision IDD6 CKE ≦0.2 Rev. 0.1 CKE≦0.2, tCK =∞ 2.5mA Rev. 0.2 2.5mA 7mA CKE≦0.2, tCK = tCK (min) - Added 144 Ball FBGA Pin arrangement. - Added BGA 144B Package Outline. Revision 0.1 (April 11,2001) - Original Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 1/49 ESMT DDR SDRAM Preliminary M13S64322A 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bidirectional data strobe(DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2, 3, 4 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE DM0~DM3 for write masking only VDD = 2.5V ± 5%, VDDQ = 2.5V ± 5% Auto & Self refresh 15.6us refresh interval (2K / 32ms refresh) 1 DQS for QFP (4 DQS for FBGA) SSTL-2 I/O interface 100pin LQFP or QFP package (optional FBGA package, 144 balls, 0.5mm ball size, 0.8mm pitch) Operating Frequencies: Maximum Operating Frequency -4 250MHz -5 200MHz CAS Latency 3 Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 2/49 ESMT Pin Arrangement Preliminary M13S64322A DQ11 DQ13 DQ15 DQ25 DQ28 DQ27 DQ26 DQ24 DQ14 DQ12 DQ10 VDDQ VSSQ VDDQ VSSQ VDDQ VDDQ VSSQ DQ 9 DQ 8 DM 3 VREF DM 1 CKE 53 CLK CLK 80 79 78 77 76 75 74 71 VDD VSS 61 73 72 70 69 68 67 66 65 64 63 62 60 59 58 57 56 55 54 52 51 A8/AP N. C DQ29 VSSQ DQ30 DQ31 VSS VDDQ N. C N. C N. C N. C N. C VSSQ RF U DQS VDDQ VDD DQ 0 DQ 1 VSSQ DQ 2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 23 24 27 28 22 25 26 29 30 1 2 3 4 5 6 7 8 9 50 49 48 47 46 45 A7 A6 A5 A4 VSS A9 N. C N. C N. C N. C N. C N. C N. C N. C A10 VDD A3 A2 A1 A0 100 Pin LQFP Forward Type 20 x 14 mm 0.65 mmpin Pitch 44 43 42 41 40 39 38 37 36 35 34 33 32 31 VDDQ VSSQ VSSQ DQ 6 DQ 7 WE DQ 3 DQ 4 DQ 5 DQ16 DQ17 DQ18 DQ21 VDDQ VDDQ CAS DQ19 DQ20 DQ22 DQ23 VSSQ VDDQ DM 0 DM 2 RAS 144 Ball FBGA 1 A B C D E F G H J K L M DQS0 DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ21 DQ22 CAS RAS CS 2 DM0 VDDQ DQ5 VDDQ DQ16 DQ18 DM2 DQ20 DQ23 WE NC NC 3 VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD NC BA0 4 DQ3 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS BA1 A0 5 DQ2 DQ1 VSSQ VSSQ VSS Thermal 6 DQ0 VDDQ VDD VSS VSS Thermal 7 DQ31 VDDQ VDD VSS VSS Therm al VSS Therm al VSS Therm al VSS Therm al VSS VDD A9 A4 8 DQ29 DQ30 VSSQ VSSQ VSS Therm al VSS Therm al VSS Therm al VSS Therm al VSS NC A5 A6 9 DQ28 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS NC A7 10 VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD CLK A8/AP BA0 11 DM3 VDDQ DQ26 VDDQ DQ15 DQ13 DM1 DQ11 DQ9 NC CLK CKE BA1 VDD VSS CS 12 DQS3 DQ27 DQ25 DQ24 DQ14 DQ12 DQS1 DQ10 DQ8 NC NC VREF VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS A10 A2 A1 VSS VDD NC A3 Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 3/49 ESMT Pin Description (M13S64322A) Pin Name Function Address inputs -Row address A0~A10 -Column address A0~A7 A8/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power (=2.5V) Bi-directional Data Strobe (LQFP) Bi-directional Data Strobe (FBGA) Preliminary M13S64322A Pin Name Function A0~A10, BA0,BA1 DM0~DM3 DQ Mask enable in write cycle DQ0~DQ31 RAS CAS WE CLK, CLK CKE CS VDDQ VSSQ VREF NC Clock input Clock enable Chip select Supply Voltage for DQ Ground for DQ Reference Voltage for SSTL-2 No connection VSS VDD DQS DQS0~DQS3 Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 4/49 ESMT Absolute Maximum Rating Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Note : Preliminary Symbol VIN, VOUT VDD, VDDQ VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 1 50 M13S64322A Unit V V V °C W mA Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operation Condition & Specifications DC Operation Condition Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 °C ) Parameter Supply voltage I/O Supply voltage I/O Reference voltage I/O Termination voltage (system) Input logic high voltage Input logic low voltage Input Voltage Level, CLK and CLK inputs Input Differential Voltage, CLK and CLK inputs Input leakage current Output leakage current Output High Voltage (IOH=-15.2mA)) Output Low Voltage (IOL=+15.2mA) Symbol VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) II IOZ VOH VOL Min 2.375 2.375 0.49*VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 -5 -5 VTT+0.76 VTT-0.76 Max 2.625 2.625 0.51*VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 5 5 Unit V V V V V V V V 3 1 2 Note μA μA V V Notes 1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 2. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF . 3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK . Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 5/49 ESMT DC Specifications Parameter Operation Current (One Bank Active) Operation Current (One Bank Active) Precharge Power-down Standby Current Idle Standby Current Active Power-down Standby Current Active Standby Current Operation Current (Read) Operation Current (Write) Auto Refresh Current Self Refresh Current Symbol Preliminary M13S64322A Version -4 205 265 35 155 55 155 385 370 350 2.5 7 -5 175 225 35 135 55 135 330 330 285 2.5 mA 7 1 Test Condition tRC = tRC (min), tCK = tCK (min) Active - Precharge Burst = 2, tRC = tRC (min), CL=3, IOUT = 0mA, Active-Read-Precharge CKE ≤ VIL(max), tCK = tCK (min), All banks idle CKE ≥ VIH(min), CS ≥ VIH(min), tCK = tCK (min) All banks ACT, CKE ≤ VIL(max), tCK = tCK (min) One bank; Active-Precharge, tRC = tRAS(max), tCK = tCK (min) Burst=2, CL=3, tCK = tCK (min), IOUT = 0mA Burst=2, CL=3, tCK = tCK (min) tRC (min) CKE ≤ 0.2V, tCK = ∞ Unit Note IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 mA mA mA mA mA mA mA mA mA CKE ≤ 0.2V, tCK = tCK (min) Note 1. Enable on-chip refresh and address counters. AC Operation Conditions & Timing Specification AC Operation Conditions Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Different Voltage, CLK and CLK inputs Input Crossing Point Voltage, CLK and CLK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.35 VREF - 0.35 VDDQ+0.6 0.5*VDDQ+0.2 Max Unit V V V V 1 2 Note Note: 1. VID is the magnitude of the difference between the input level on CLK and the input on CLK . 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Input / Output Capacitance (VDD = 2.5V±5%, VDDQ =2.5V±5%, TA = 25 °C , f = 1MHz) Parameter Input capacitance (A0~A10, BA0~BA1, CKE, CS , RAS , CAS , WE ) Input capacitance (CLK, CLK ) Data & DQS input/output capacitance (DQ0~DQ31) Input capacitance (DM0~DM3) Elite Semiconductor Memory Technology Inc. Symbol CIN1 CIN2 COUT CIN3 Min 2.5 2.5 4.0 4.0 Max 3.5 3.5 5.5 5.5 Unit pF pF pF pF Publication Date : May. 2007 Revision : 0.5 6/49 ESMT AC Operating Test Conditions Parameter Input reference voltage for clock (VREF) Input signal maximum peak swing Input signal minimum slew rate Input levels (VIH/VIL) Input timing measurement reference level Output timing reference level Preliminary M13S64322A Value 0.5*VDDQ 1.5 1.0 VREF+0.35/VREF-0.35 VREF VTT Unit V V V/ns V V V AC Timing Parameter & Specifications (VDD = 2.5V±5%, VDDQ=2.5V±5%, TA =0 °C to 70 °C )(Note) Parameter Clock Period (CL3) (CL4) Access time from CLK/ CLK CLK high-level width CLK low-level width Data strobe edge to clock edge Clock to first rising edge of DQS delay Data-in setup time (to DQS) Data-in hold time (to DQS) DM setup time (to DQS) DM hold time (to DQS) Input setup time Input hold time DQS input high pulse width DQS input low pulse width Clock to DQS write preamble setup time Clock to DQS write preamble hold time Write postamble Data strobe edge to output data edge Half Clock Period DQ-DQS output hold time Data-out high-impedance windows from CLK/ CLK Data-out low-impedance windows from CLK/ CLK tAC tCH tCL tDQSCK tDQSS tDS tDH tDQMS tDQMH tIS tIH tDQSH tDQSL tWPRES tWPREH tWPST tDQSQ tHP tQH tHZ Symbol tCK -4 MIN 4 -0.5 0.45 0.45 -0.5 0.75 0.4 0.4 0.4 0.4 0.75 0.75 0.4 0.4 0 0.25 0.25 -0.35 tCLmin or tCHmin tHP-0.35 -0.5 0.5 0.35 0.6 0.6 0.5 1.25 MAX 10 0.5 0.55 0.55 0.5 1.25 MIN 5 -0.75 0.45 0.45 -0.75 0.75 0.4 0.4 0.4 0.4 1.1 1.1 0.4 0.4 0 0.25 0.25 -0.5 tCLmin or tCHmin tHP-0.5 -0.75 0.75 0.5 0.6 0.6 0.5 1.25 -5 MAX 10 0.75 0.55 0.55 0.75 1.25 ns ns ns tCK tCK ns tCK ns ns ns ns ns ns tCK tCK tCK tCK tCK ns ns ns ns tLZ -0.5 0.5 -0.75 0.75 ns Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 7/49 ESMT AC Timing Parameter & Specifications-continued Parameter ACTIVE to PRECHARGE command AUTO REFRESH, ACTIVE command period RAS to CAS delay for Read RAS to CAS delay for Write Preliminary M13S64322A Symbol tRAS tRC tRCDRD tRCDWR tRP tRRD tWR tWTR tLMRD tRPRE tRPST tDQSV tPDENT tPDEX tXSR tXSA tREFI -4 MIN 9tCK 14tCK 4tCK 2tCK 20 3 2 1 1 0.9 0.4 0.35 tIS+1 tCK tIS+1 tCK 200 12 15.6 tIS+2 tCK tIS+2 tCK 1.1 0.6 MAX 120,000 MIN 8tCK 12tCK 3tCK 2tCK 20 3 2 1 1 0.9 0.4 0.35 tIS+1 tCK tIS+1 tCK 200 12 -5 MAX 120,000 ns ns ns ns ns tCK tCK tCK tCK 1.1 0.6 tCK tCK tCK tIS+2 tCK tIS+2 tCK ns ns tCK tCK 15.6 us PRECHARGE command period ACTIVE bank A to ACTIVE bank B command Write recovery time Write data in to Read command delay Load Mode Register / Extended Mode register cycle time DQS read preamble DQS read postamble DQS valid window Power down entry time Power down exit time Exit self refresh to READ command Exit self refresh to non-READ command Average periodic refresh interval Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 8/49 ESMT Command Truth Table COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit L H H Auto Precharge Enable Auto Precharge Disable H Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No Operation Command L H H X H L H H H H L H X X L H L L L H L X H L H L X L CKEn-1 CKEn CS H H H X X H L H X X L H L L L L L Preliminary M13S64322A RAS L L L H X L H CAS L L L H X H L WE DM X X X BA0,1 A8/AP OP CODE OP CODE X A10~A9, A7~A0 Note 1,2 1,2 3 L L H H X H H 3 3 3 Column Address (A0~A7) Column Address (A0~A7) 4 4 4 4,6 7 X 5 X X X V V X Row Address L H L Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable H H L X V X X H X V X X H L H H X V X X H X V X H L L L X V X X H X V X H X X X X X X V H X V X L H X Active Power Down X X V X X X 8 (V = Valid, X = Don’t Care, H = Logic High, L = Logic Low) 1. OP Code: Operand Code. A0~A10 & BA0~BA1: Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 1 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by “Auto”.. Auto/self refresh can be issued only at all banks precharge state. 4. BA0~BA1 : Bank select addresses. If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected. If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected. If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected. 5. If A8/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 9/49 ESMT Basic Functionality Power-Up and Initialization Sequence Preliminary M13S64322A The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & VREF). 2. Start clock and maintain stable condition for a minimun of 200us. 3. The minimun of 200us after stable power and clock (CLK, CLK ), apply NOP & take CKE high. *1 *1 *2 4. Issue precharge commands for all banks of the device. 5. Issue EMRS to enable DLL. 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL. 7. Issue precharge commands for all banks of the device. 8. Issue 2 or more auto-refresh commands. 9. Issue a mode register set command with low to A8 to initialize device operation. *1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6 & 7 is regardless of the order. P o we r u p & I n i t i a l i z a t i o n S e q u e n c e 0 CLK CLK Command p re c ha rg e A ll B ank s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRP E MRS MRS D ll Reset p r e c ha r g e A ll B a nks tRP 1st A uto Re f re s h tRC 2nd A uto Re f re s h tRC Mode Register Set Any C omma nd min . 200 Cy cl e Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 10/49 ESMT Mode Register Definition Mode Register Set (MRS) Preliminary M13S64322A The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE , BA0 and BA1 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A10 in the same cycle as CS , RAS , CAS , WE , BA0 and BA1 going low is written in the mode register. One clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7~A10 specify operating mode. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0 0 0 0 DLL TM CAS Latency BT Burst Length Mode Register A8 0 1 DLL Reset No Yes A7 0 1 Mode Normal Test A3 0 1 Burst Type Sequential Interleave Burst Length CAS Latency BA1 BA0 0 0 0 1 Operating Mode MRS Cycle EMRS Cycle A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserve Reserve 2 3 4 Reserve Reserve Reserve A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Latency Sequential Interleave Reserve Reserve 2 2 4 4 8 8 Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 11/49 ESMT Burst Length 2 Starting Address (A2, A1,A0) xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 Preliminary Burst Address Ordering for Burst Length Sequential Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 M13S64322A Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 4 8 DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S64322A also support the option of weak drive strength or match mode drive strength, intended for lighter load and/or point-to-point environments. Mode Register Set 0 CLK CLK *1 1 2 3 4 5 6 7 8 COMMAND Precharg e Al l Ba n k s Mod e Register Set An y Com m an d tCK t R P* 2 *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 12/49 ESMT Extended Mode Register Set (EMRS) Preliminary M13S64322A The extended mode register stores the data enabling or disabling DLL. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS , RAS , CAS , WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2~A5, A7~A10 and BA1 in the same cycle as CS , RAS , CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched impedance. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0, A1, A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0 1 RFU: Must be set “0” D.I.C RFU: Must be set “0” D.I.C DLL Extended Mode Register A6 0 0 1 1 A1 0 1 0 1 Output Driver Impedance Control Normal Weak RFU Matched Impedance 60Ω A0 0 1 DLL Enable Enable Disable BA1 0 0 BA0 0 1 Operating Mode MRS Cycle EMRS Cycle Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 13/49 ESMT Precharge Preliminary M13S64322A The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. Burst Selection for Precharge by Bank address bits A8/AP 0 0 0 0 1 BA1 0 0 1 1 X BA0 0 1 0 1 X Precharge Bank A Only Bank B Only Bank C Only Bank D Only All Banks NOP & Device Deselect The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and NOP the device should finish the current operation when this command is issued. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 14/49 ESMT Row Active Preliminary M13S64322A The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CLK). The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time(tRRD min). Bank Activation Command Cycle ( CAS Latency = 2) 0 CLK CLK 1 2 Addr ess Ban k A Ro w Ad d r . Ban k A Col. Add r . Bank B Ro w Ad d r . Ban k A Ro w . Ad d r . RAS-CAS d el ay (tRCD) RAS-RAS d el ay (tRRD) Bank B Act ivat e NOP Bank A Act ivat e Command Ban k A Activate NOP Write A wi th Au t o Precharg e ROW Cycle Time (tRC) : Don't Care Read Bank This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command. Write Bank This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 15/49 ESMT Essential Functionality for DDR SDRAM Burst Read Operation Preliminary M13S64322A Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from the bank activation. The address inputs (A0~A7) determine the starting address for the Burst, The Mode Register sets type of burst (Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM until the burst length is completed. 0 CLK CLK 1 2 3 4 5 6 7 8 CO MMAND READ A NOP NOP NOP NO P NO P NOP NOP NOP DQS CAS Latency= 2 DQ's tRPRE tRPST Dout 0 Dout 1 Dout 2 Dout 3 DQS CAS Latency= 3 DQ's Dout 0 Dout 1 Dout 2 Dout 3 DQS CAS Latency= 4 DQ's Dout 0 Dout 1 Dout 2 Dout 3 Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 16/49 ESMT Burst Write Operation Preliminary M13S64322A The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. 0 CLK CLK 1 2 3 4 5 6 7 8 COMM AND NOP W RITE NO P NOP NOP NO P NO P NOP NOP tDQSS DQ S tWPRES tW PST DQ's Din0 Din1 Din2 Din3 Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 17/49 ESMT Read Interrupted by a Read Preliminary M13S64322A A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock. 0 CLK CLK 1 2 3 4 5 6 7 8 COMMAND READ A READ B NOP NOP NOP NO P NOP NOP NOP DQS CAS Latency= 3 DQ's Dou t A 0 Dou t A 1 Dou t B 0 Dou t B 1 Dou t B 2 Dou t B 3 Read Interrupted by a Write & Burst Stop To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQ’s (Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the write operation, Burt stop command must be applied at least CAS Latency clock cycles before the Write command. 0 CLK CLK 1 2 3 4 5 6 7 8 COMMAND READ Bu r st S t op NOP NO P W RITE NO P NOP NOP NOP DQS CAS Latency= 3 DQ's Dou t 0 Dou t 1 Din 0 Din 1 Din 2 Din 3 Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 18/49 ESMT Read Interrupted by a Precharge Preliminary M13S64322A A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency. 0 CLK CLK 1tCK COMMAND READ Prech arg e 1 2 3 4 5 6 7 8 NOP NOP NO P NO P NOP NOP NOP DQS CAS Latency= 3 DQ's Dou t 0 Dou t 1 Dou t 2 Dou t 3 Dou t 4 Dou t 5 Dou t 6 Dou t 7 Int err upt ed by precharg e When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS precharge time). 2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after tRP. 3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 19/49 ESMT Write Interrupted by a Write Preliminary M13S64322A A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 0 CLK CLK 1tCK COMM AND NO P WRITE A WRITE B NO P NO P NO P NO P NOP NOP 1 2 3 4 5 6 7 8 DQ S DQ's Din A 0 Din A 1 Din B 0 Din B 1 Din B 2 Din B 3 The following functionality establishes how a Write command may interrupt a Read burst. 1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command = CAS Latency clock cycles. 2. It is illegal for a Write command to interrupt a Read with autoprecharge command. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 20/49 ESMT Write Interrupted by a Read & DM Preliminary M13S64322A A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command. 0 CLK CLK 1 2 3 4 5 6 7 8 COMMAND NOP W RITE NO P NOP NOP tWTR Read NOP NOP NOP tDQSSmax DQS CAS Latency= 3 DQ's tDQSSmin DQS tWPRES CAS Latency= 3 DQ's Din 0 Din 1 Din 2 tWPRES Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dou t 0 Dou t 1 tWTR Din 3 Din 4 Din 5 Din 6 Din 7 Dou t 0 Dou t 1 DM The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the memory. 1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay is 1 clock cycle is disallowed. 2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation. 3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the DDR SDRAM drives them during a read operation. 4. If input Write data is masked by the Read command, the DQS inputs is ignored by the DDR SDRAM. 5. It is illegal for a Read command interrupt a Write with autoprecharge command. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 21/49 ESMT Write Interrupted by a Precharge & DM Preliminary M13S64322A A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time(tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM. 0 CLK CLK 1 2 3 4 5 6 7 8 COMMAND NOP WRITE A NOP NOP NOP NOP Precharge WRITE B NOP tDQSSmax DQS tWR DQ's tDQSSmin DQS tWR DQ's Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 Dinb1 Di n a 0 D i n a 1 Di n a 2 D i n a 3Di n a 4 Di n a 5 D i n a 6 Di n a 7 Dinb0 DM Precharge timing for Write operations in DRAMs requires enough time to allow “Write recovery” which is the time required by a DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used to indicate the required of time between the last valid write operation and a Precharge command to the same bank. The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the DDR SDRAM, the data path is eventually synchronizes with the address path by switching clock domains from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain. tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge that strobes in the precharge command. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 22/49 ESMT Preliminary M13S64322A 1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write recovery is defined by tWR. 2. When a precharge command interrupts a Write burst operation, the data mask pin, DQ, is used to mask input data during the time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above. 4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst. Burst Stop The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock (CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation. 0 CLK CLK 1 2 3 4 5 6 7 8 COMMAND READ A Burst Stop NOP NOP NOP NOP NO P NOP NO P DQS CAS Latency= 2 The burst ends after a delay equal to the CAS latency. DQ's Dout 0 Dout 1 DQS CAS Latency= 3 DQ's Dout 0 Dout 1 DQS CAS Latency= 4 DQ's Dout 0 Dout 1 Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 23/49 ESMT 1. 2. 3. 4. 5. 6. Preliminary M13S64322A The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required. The BST command may only be issued on the rising edge of the input clock, CLK. BST is only a valid command during Read burst. BST during a Write burst is undefined and shall not be used. BST applies to all burst lengths. BST is an undefined command during Read with autoprecharge and shall not be used. When terminating a burst Read command, the BST command must be issued LBST ( “BST Latency”) clock cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations. 7. When the burst terminates, the DQ and DQS pins are tristated. The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s). DM masking The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe. 0 CLK CLK 1 2 3 4 5 6 7 8 CO MM AND W RITE NOP NOP NOP NOP NOP NOP NOP NOP DQS tDQSS DQ's Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 DM masked by DM = H Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 24/49 ESMT Read With Auto Precharge Preliminary M13S64322A If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time (tRP) has been satisfied CLK CLK 0 1 2 3 4 5 6 7 8 COMMAND Ban k A ACTIVE NOP Re a d A Auto Pr ec har g e NO P NO P NOP NOP NOP NOP tRAS( min. ) DQS CAS Latency= 2 DQ's Dout 0 Dout 1 D out 2 Dout 3 tRP DQS CAS Latency= 3 DQ's Bank can b e react ivated at t h e comp letion of p rech arg e Dout 0 Dout 1 Dout 2 Dout 3 DQS RAS Latency= 4 DQ's Begin Auto-Prech arg e Dout 0 Dout 1 Dout 2 Dout 3 At burst read / write with auto precharge, CAS interrupt of the same bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 25/49 ESMT Write with Auto Precharge Preliminary M13S64322A If A8 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). 0 CLK CLK 1 2 3 4 5 6 7 8 COMM AND Ban k A ACTIVE NO P W r i te A Auto Pr ec har g e NOP NO P NO P NO P NOP NOP DQ S *B an k c an be reac t ivat ed at com p let ion of t RP DQ's Dout 0 Dout 1 Dout 2 Dout 3 tWR In te rn al p re ch ar g e s tar t tRP Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of the clock (CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tRC(min). CLK CLK COMMAND PR E Au t o Ref resh CMD CKE = High tRP tRC Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 26/49 ESMT Self Refresh Preliminary M13S64322A A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSR for locking of DLL. CLK CLK COMMAND Sel f Ref resh Au t o Ref resh Rea d CKE tXSA tXSR Power down The power down mode is entered when CKE is low and exited when CKE is high. Once the power down mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit tree are gated off to reduce power consumption. All the banks should be in idle state prior to entering the precharge power down mode and CKE should be set high at least 1tCK+1tIS prior to row active remain command. During power down, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period (tREFI) of the device. CLK CLK Prec harge power down Entry Pr ec harge power down Exit Active power down Entry CO MM AN D Precharge Active Active power down Exit Rea d CKE Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 27/49 ESMT Functional Truth Table. Current CS H L L IDLE L L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L L L L L H H L L L H L H L BA, CA, A8 BA, RA BA, A8 X RAS X H H H L L L L X H H H H L L L L X H H H CAS X H H L H H L L X H H L L H H L L X H H L WE Preliminary Address X X BA BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 Command DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / READA WRITE / WRITEA Active PRE / PREA Refresh MRS NOP NOP M13S64322A Action X H L X H L H L X H L H L H L H L X H L H ILLEGAL*2 ILLEGAL*2 Bank Active, Latch RA NOP*4 AUTO-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto -precharge Begin Write, Latch CA, Determine Auto -precharge Bank Active/ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 ILLEGAL Bank Active/ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL Op-Code Mode-Add Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 28/49 ESMT Current State CS H L L L RAS X H H H CAS X H H L WE Preliminary Address X X BA BA, CA, A8 Command DESEL NOP Burst Stop READ/READA M13S64322A Action NOP (Continue Burst to end) NOP (Continue Burst to end) ILLEGAL Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA, Begin new Write, Determine Auto-Precharge*3 Bank Active/ILLEGAL*2 Terminal Burst With DM= High, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to end) NOP (Continue Burst to end) ILLEGAL READ*7 ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL Write Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL X H L H WRITE L L L L L H L L H L L L L X H H H H L L L L X H H H H L L L L L H H L L X H H L L H H L L X H H L L H H L L L H L H L X H L H L H L H L X H L H L H L H L BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add WRITE/WRITEA Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS READ with AUTO PRECHARGE L L L L L L H L L L READ L L L L L Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 29/49 ESMT Current State CS H L L PRE-CHARGIN G L L L L L H L L ROW ACTIVATING L L L L L H L L L WRITE RECOVERING L L L L L RAS X H H H L L L L X H H H L L L L X H H H H L L L L CAS X H H L H H L L X H H L H H L L X H H L L H H L L WE Preliminary Address X X BA BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add Command DESEL NOP Burst Stop READ/WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ WRITE Active PRE / PREA Refresh MRS M13S64322A Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (ROW Active after tRCD) NOP (ROW Active after tRCD) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2 ILLEGAL*2 WRITE ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL X H L X H L H L X H L X H L H L X H L H L H L H L Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 30/49 ESMT Current State CS H L L RE-FRESHING L L L L L H L L MODE REGISTER SETTING L L L L L RAS X H H H L L L L X H H H L L L L CAS X H H L H H L L X H H L H H L L WE Preliminary Address X X BA BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add X X BA BA, CA, A8 BA, RA BA, A8 X Op-Code Mode-Add Command DESEL NOP Burst Stop READ/WRITE Active PRE / PREA Refresh MRS DESEL NOP Burst Stop READ / WRITE Active PRE / PREA Refresh MRS M13S64322A Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL X H L X H L H L X H L X H L H L ABBREVIATIONS : H = High Level, L = Low level, V = Valid, X = Don’t Care BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the bank. 3. Must satisfy bus contention, bus turn around and write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL of any bank is not idle. 6. Same bank’s previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be performed. 7. Refer to “Read with Auto Precharge: for more detailed information. ILLEGAL = Device operation and / or data integrity are not guaranteed. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 31/49 ESMT Current State CKE n-1 H L L SELF-REFRESHING* 1 L L L L H POWER DOWN L L H H H ALL BANKS IDLE*2 H H H H L H ANY STATE other than listed above CKE n X H H H H H L X H L H L L L L L L L H CS X H L L L L X X X X X L H L L L L L X RAS X X H H H L X X X X X L X H H H L X X CAS X X H H L X X X X X X L X H H L X X X WE Preliminary Add X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh Exit Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Action M13S64322A X X H L X X X X X X X H X H L X X X X Exit Power Down (Idle after tPDEX) NOP (Maintain Power Down) Refer to Function True Table Enter Self-Refresh Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function True Table ABBREVIATIONS : H = High Level, L = Low level, V = Valid, X = Don’t Care Note : 1. CKE Low to High transition will re-enable CLK, CLK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from All Bank Idle state. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 32/49 ESMT tCH tCL tCK 0 CLK CLK 1 2 3 4 Preliminary M13S64322A Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3) 5 6 7 8 9 10 tHP HIGH CKE Note1 CS tIS tIH RAS CAS BA0,BA1 BAa BAb A8/ AP BAa Cb WE tDQSCK tRPRE DQS tDQSCK tRPST Hi-Z tDQSS tWPREH tDQSQ tLZ DQ Da0 Da1 Da2 tAC Da3 tHZ Hi-Z tDQSL tDQSH tWPRES tDS tDH tDS tDH Db0 Db1 Db2 tWPST Hi-Z Db3 Hi-Z tQH DM COMM AND READ WRITE Note1 tHP is lesser of tCL or tCH clock transition collectively when a bank is active. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 33/49 ESMT Multi Bank Interleaving READ (@BL=4, CL=3) Preliminary M13S64322A 0 CLK CLK 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS BA0,BA1 BAa BAb BAa BAb A8/ AP Ra Rb ADDR (A0~A7, A9~A10 ) tRRD Ra Rb Ca tRCDRD Cb WE DQS DQ Q a0 Qa1 Q a2 Q a3 Q b0 Q b1 Q b2 Q b3 DM tRCDRD COMM AN D ACTIVE ACTIVE READ READ Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 34/49 ESMT Multi Bank Interleaving WRITE (@BL=4) Preliminary M13S64322A 0 CLK CLK 1 2 3 4 5 6 7 8 9 10 HIGH CKE CS RAS CAS BA0,BA1 BAa BAb BAa BAb A8/ AP Ra Rb tRRD ADDR (A0~A7, A9~A10 ) Ra Rb Ca tRCDW R Cb WE DQS DQ Q a0 Q a1 Qa2 Q a3 Q b0 Qb 1 Q b2 Q b3 DM tRCDW R COMMAND ACTIVE ACTIVE WRITE WRITE Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 35/49 ESMT Read with Auto Precharge (@BL=8) 0 CLK CLK 1 2 3 4 Preliminary M13S64322A 5 6 7 8 9 10 CKE HIGH CS RAS CAS BA0, BA1 BAa BAa A8/ AP Ra AD D R (A0~A7, A9~A10 ) Ca Ra WE Au t o p r e ch ar g e s t a r t tRP Note1 DQS(CL=3) DQ(CL=3) Q a0 Qa1 Qa2 Qa3 Q a4 Q a5 Q a6 Q a7 DM CO MM AND READ ACTIVE Note 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 36/49 ESMT Write with Auto Precharge (@BL=4) 0 CLK CLK 1 2 3 4 Preliminary M13S64322A 5 6 7 8 9 10 CKE HIGH CS RAS CAS BA0, BA1 BAa BAa A8/ AP Ra ADDR (A0~A7, A9~A10 ) Ca Ra WE Au t o p r e ch ar g e s t a r t tWR Note1 DQ S tRP DQ Q a0 Qa1 Qa2 Qa3 DM COMMAND WRITE ACTIVE Note 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 37/49 ESMT Read Interrupted by Precharge (@BL=8) 0 CLK CLK 1 2 3 4 Preliminary M13S64322A 5 6 7 8 9 10 HIGH CKE CS RAS CAS BA0,BA1 BAa BAb A8/ AP ADDR (A0~A7, A9~A10 ) Ca WE DQS(CL=3) DQ(CL=3) Q a0 Q a1 Q a2 Q a3 Q a4 Qa5 DM COMM AND READ PRE CHARGE Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 38/49 ESMT Read Interrupted by a Read (@BL=8, CL=3) 0 CLK CLK 1 2 3 4 Preliminary M13S64322A 5 6 7 8 9 10 HIGH CKE CS RAS CAS BA0,BA1 BAa BAb A8 / AP ADDR (A0~A7, A9~A10 ) Ca Cb WE DQS DQ Q a0 Qa1 Qb0 Qb1 Q b2 Q b3 Qb4 Q b5 Q b6 Qb7 DM COMM AND READ READ Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 39/49 ESMT 0 CLK CLK 1 2 3 4 Preliminary M13S64322A Read Interrupted by a Write & Burst stop (@BL=8, CL=3) 5 6 7 8 9 10 CKE HIGH CS RAS CAS BA0,BA1 BAa BAb A8/ AP ADDR (A0~A7, A9~A10 ) Ca Cb WE DQS DQ Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 DM COMMAND READ Burst Stop WRITE Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 40/49 ESMT Write followed by Precharge (@BL=4) 0 CLK CLK 1 2 3 4 Preliminary M13S64322A 5 6 7 8 9 10 HIGH CKE CS RAS CAS BA0,BA1 BAa BAa A8/ AP ADDR (A0~A7, A9~A10 ) Ca WE tWR DQS DQ Da0 Da1 Da2 Da3 DM COMMAND WRITE PRE CHARGE Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 41/49 ESMT Write Interrupted by Precharge & DM (@BL=8) 0 CLK CLK 1 2 3 4 Preliminary M13S64322A 0 1 2 3 4 5 HIGH CKE CS RAS CAS BA0,BA1 BAa BAa BAb BAc A8 / AP ADDR (A0~A7, A9~A10 ) Ca Cb Cc WE DQS DQ Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Dc0 Dc1 Dc2 Dc 3 DM tWR CO MM AND WRITE PRE CHARGE WRITE WRITE Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 42/49 ESMT Write Interrupted by a Read (@BL=8, CL=3) 0 CLK CLK 1 2 3 4 Preliminary M13S64322A 5 6 7 8 9 10 HIGH CKE CS RAS CAS BA0,BA1 BAa BAb A8 / AP ADDR (A0~A7, A9~A10 ) Ca Cb WE DQ S DQ Da0 Da1 Da2 Da3 Da4 Da5 Q b0 Qb1 Q b2 Qb3 Qb4 Qb5 Ma s k ec d b y D M DM tWTR COMMAND WRITE READ Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 43/49 ESMT DM Function (@BL=8) only for write 0 CLK CLK 1 2 3 4 Preliminary M13S64322A 5 6 7 8 9 10 HIGH CKE CS RAS CAS BA0,BA1 BAa A8/ AP ADDR (A0~A7, A9~A10 ) Ca WE DQS(CL=3) DQ(CL=3) Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 DM CO MM AND WRITE Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 44/49 ESMT Power up & Initialization Sequence 0 CLK CLK 1 2 3 4 5 6 7 8 9 Preliminary M13S64322A 10 11 12 13 14 15 16 17 18 19 CKE Hi gh l evel i s r equ i r ed CS RAS CAS WE BA0 BA1 ,A 9, A1 0 A8 /AP A7 ADDRESS KEY A1 ~ A6 A0 High-Z DQ Minimum 200 Cycle tRP High-Z DQ S Precharge All B an k Power & Cl ock m us t be stable f or 200us EMRS DLL Enable MRS Dll Reset Precharge All Ban k tRP tRC tRC M i n i m u m o f 2 R ef r es h Cyc les ar e r equ ir e d Any Com mand 1st Auto Ref res h 2nd Auto Ref resh M ode R es i st er S et : Don't Car e Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 45/49 ESMT Mode Register Set 0 CLK CLK 1 2 3 4 5 6 7 8 Preliminary M13S64322A 9 10 11 12 13 14 15 16 17 18 19 tCK CKE CS RAS CAS WE BA0,BA1 A8/ AP AD DR ES S KE Y ADD R (A0~A7, A9~A10 ) DM tRP High-Z DQ High- Z DQS Precharge Com man d All B an k Any Command Mode R egis ter Set Command Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 46/49 ESMT PACKING 100-LEAD DIMENSIONS LQFP Preliminary M13S64322A DDR SDRAM(14x20mm) D D1 80 81 51 50 C C1 b b1 WITH PLATING BASE METAL SEC : B-B E1 E F F 100 1 e 30 31 b GAGE PLANE B B L L1 A2 A SEC : F-F SEATING PLANE A1 Symbol A A1 A2 b b1 c c1 D D1 E E1 e L L1 θ° Dimension in inch Min Norm Max 0.063 0.002 0.006 0.053 0.055 0.057 0.009 0.013 0.015 0.009 0.012 0.013 0.004 0.008 0.004 0.006 0.860 0.866 0.872 0.783 0.787 0.791 0.624 0.630 0.636 0.547 0.551 0.555 0.026BSC 0.018 0.024 0.030 0.039 REF 00 3.50 70 Dimension in mm Min Norm Max 1.60 0.05 0.15 1.35 1.40 1.45 0.22 0.32 0.38 0.22 0.30 0.33 0.09 0.20 0.09 0.16 21.85 22.00 22.15 19.90 20.00 20.10 15.85 16.00 16.15 13.90 14.00 14.10 0.65 BSC 0.45 0.60 0.75 1.00 REF 00 3.50 70 Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 47/49 ESMT PACKING 144-BALL DIMENSIONS Preliminary M13S64322A FBGA DDR DRAM (12x12mm) Symbol A A1 Φb D E D1 E1 e aaa bbb ddd eee fff MD/ME Dimension in mm Min Norm Max 1.14 1.40 0.30 0.35 0.40 0.40 0.45 0.50 11.90 12.00 12.10 11.90 12.00 12.10 8.80 8.80 0.80 0.10 0.10 0.12 0.15 0.08 12/12 Dimension in inch Min Norm Max 0.049 0.055 0.012 0.014 0.016 0.016 0.018 0.020 0.469 0.472 0.476 0.469 0.472 0.476 0.346 0.346 0.031 0.004 0.004 0.005 0.004 0.006 12/12 Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 48/49 ESMT All rights reserved. Preliminary Important Notice M13S64322A No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 49/49