M24L16161ZA

ESMT Revision History : Revision 1.0 (Jul. 4, 2007) - Original M24L16161ZA Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 1/15 ESMT PSRAM Features ‧Wide voltage range: 2.2V–3.6V • Access Time: 70 ns • Ultra-low active power— Typical active current: 3 mA @ f = 1 MHz— Typical active current: 18 mA @ f = fmax • Ultra low standby power • Automatic power-down when deselected • CMOS for optimum speed/power • Deep Sleep Mode • Offered in a Lead-Free 48-ball BGA package • Operating Temperature: –40°C to +85°C M24L16161ZA 16-Mbit (1M x 16) Pseudo Static RAM are disabled ( OE HIGH), both Byte High Enable and Byte Low Enable are disabled ( BHE , BLE HIGH), or during a write operation ( CE LOW and WE LOW). To write to the device, take Chip Enable ( CE LOW) and Write Enable ( WE ) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable ( BHE ) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables ( CE LOW) and Output Enable ( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the Truth Table for a complete description of read and write modes. To enable Deep Sleep Mode, drive ZZ LOW. See the Truth Table for a complete description of Read, Write, and Deep Sleep mode. Functional Description[1] The M24L16161ZA is a high-performance CMOS Pseudo Static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode when deselected ( OE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected ( OE HIGH), outputs Logic Block Diagram Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 2/15 ESMT Pin Configuration[2, 3] 48-ball VFBGA Top View M24L16161ZA Product Portfolio Product Power Dissipation Product Min. M24L16161ZA 2.2 VCC Range (V) Typ.[4] 3.0 Max 3.6 70 Speed(ns) Operating ICC(mA) f = 1MHz f = fmax .Typ.[4] Max. .Typ.[4] Max 3 5 18 25 Standby ISB2(µA) .Typ. [4] 55 Max 70 Low-Power Modes At power-up, all four sections of the die are activated and thePSRAM enters into its default state of full memory size andrefresh space. This device provides three different Low-Power Modes. 1.Reduced Memory Size Operation 2.Partial Array Refresh 3.Deep Sleep Mode 4.Temperature Controlled Refresh only refresh certain portions of the memory in Standby Mode, as configured by the user through the settings in the Variable Address Register. Once ZZ returns HIGH in this mode, the PSRAM goes back to operating in full address refresh. Refer to “Variable Address Space Register (VAR)” on page4 for the protocol to turn off sections of the memory in Standby mode. If the VAR register is not updated after power-up, the PSRAM will be in its default state. In the default state the whole memory array will be refreshed in Standby Mode. The 16-Mbit is divided into four 4-Mbit sections allowing certain sections to be active (i.e., refreshed). Reduced Memory Size Operation In this mode, the 16-Mb PSRAM can be operated as a 12-Mbit,8-Mbit, and 4-Mbit memory block. Refer to “Variable Address Space Register (VAR)” on page4 for the protocol to turn on/off sections of the memory. The device remains in RMS mode until changes to the Variable Address Space register are made to revert back to a complete 16-Mbit PSRAM. Deep Sleep Mode In this mode, the data integrity in the PSRAM is not guaranteed. This mode can be used to lower the power consumption of the PSRAM in an application. This mode can be enabled and disabled through VAR similar to the RMS and PAR mode. Deep Sleep Mode is activated by driving ZZ LOW. The device stays in the deep sleep mode until ZZ is driven HIGH. Partial Array Refresh The Partial Array Refresh mode allows customers to turn off sections of the memory block in Standby mode (with ZZ tied LOW) to reduce standby current. In this mode the PSRAM will Notes: 2. Ball H6 and E3 can be used to upgrade to a 32M and a 64M density respectively. 3. NC “no connect” - not connected internally to the die. 4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25°C. Tested initially and after any design changes that may affect the parameter. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 3/15 ESMT Variable Address Mode Register (VAR) Update[5, 6] M24L16161ZA Deep Sleep Mode—Entry/Exit[7] VAR Update and Deep Sleep Mode Timing[5, 6] Parameter tZZWE tCDR tR[7] tZZMIN Notes: 5. OE and the data pins are in a don’t care state while the device is in variable address mode. 6. All other timing parameters are as shown in the data sheets. 7. tR applies only in the deep sleep mode. Description ZZ LOW to Write Start Min. 0 200 8 Max. 1 Unit µs ns µs µs Chip deselect to ZZ LOW Operation Recovery Time (Deep Sleep Mode only) Deep Sleep Mode Time Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 4/15 ESMT Variable Address Space Register (VAR) M24L16161ZA Variable Address Space—Address Patterns Partial Array Refresh Mode (A3=0, A4=1) A2 A1, A0 Refresh Section Address 0 11 1/4th of the array 00000h - 3FFFFh (A19 = A18 = 0) 0 10 1/2th of the array 00000h - 7FFFFh (A19 = 0) th 00000h - BFFFFh (A19:A18 not equal to 11) 0 01 3/4 of the array 1 1 1 11 10 01 th 1/4 of the array th 1/2 of the array th 3/4 of the array Size 256K x 16 512K x 16 768K x 16 256K x 16 512K x 16 786K x 16 Density 4M 8M 12M 4M 8M 12M C0000h - FFFFFh (A19 = A18 = 1) 80000h - FFFFFh (A19 = 1) 40000h - FFFFFh (A19:A18 not equal to 00) Reduced Memory Size Mode (A3=1, A4=1) 0 0 0 0 1 1 1 1 11 10 01 00 11 10 01 00 th 1/4 of the array th 1/2 of the array th 3/4 of the array 00000h - 3FFFFh (A19 = A18= 0) 00000h - 7FFFFh (A19 = 0) 00000h - BFFFFh (A19:A18 not equal to 1 1) 00000h - FFFFFh (Default) C0000h - FFFFFh (A19 = A18 = 1) 80000h - FFFFFh (A19 = 1) 40000h - FFFFFh (A19:A18 not equal to 00) 00000h - FFFFFh (Default) 256K x 16 512K x 16 768K x 16 1M x 16 256K x 16 512K x 16 768K x 16 1M x 16 4M 8M 12M 16M 4M 8M 12M 16M Full array th 1/4 of the array th 1/2 of the array th 3/4 of the array Full array Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 5/15 ESMT Power-up Characteristics The initialization sequence is shown in the figure below. Chip Select ( CE ) should be HIGH for at least 200 µs after VCC has reached a stable value. No access must be attempted during this period of 200 µs. ZZ is high (H) for the duration of power-up. M24L16161ZA Parameter TPU Description Chip Enable Low After Stable VCC Min. 200 Max. Unit µs Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 6/15 ESMT Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied.............................................–55°C to +125°C Supply Voltage to Ground Potential..............................–0.3V to VCCMAX + 0.3V DC Voltage Applied to Outputs in High Z State[8, 9, 10]......................–0.3V to VCCMAX + 0.3V DC Input Voltage[8, 9, 10]..................–0.3V to VCCMAX + 0.3V Output Current into Outputs (LOW).............................20 mA M24L16161ZA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015)Latch-Up Current....................................................> 200 mA Operating Range Range Industrial Ambient Temperature (TA) −40°C to +85°C VCC 2.2V to 3.6V DC Electrical Characteristics (Over the Operating Range) [8, 9, 10] Parameter VCC VOH VOL VIH VIL IIX IOZ ICC Description Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current —CMOS Inputs Automatic CE Power-Down Current —CMOS Inputs Deep Sleep Current Test Conditions Min. 2.2 IOH = −0.1 mA VCC = 2.2V to 3.6V IOL = 0.1 mA, VCC = 2.2V to 3.6V VCC = 2.2V to 3.6V VCC = 2.2V to 3.6V GND ≤ VIN < VCC GND ≤ VOUT ≤ VCC f = fMAX = 1/tRC f = 1 MHz ISB1 CE > VCC − 0.2V, VIN > VCC − 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 ( OE , WE , BHE and BLE ), VCC=3.60V, ZZ ≥ VCC – 0.2V CE > VCC−0.2V, VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC = VCCMAX, ZZ ≥ VCC – 0.2V -70 Typ.[4] 3.0 Max. 3.6 Unit V V 0.2 V V V µA µA mA VCC-0.2 0.8* VCC -0.3 -1 -1 VCC= VCCmax IOUT = 0mA CMOS levels 18 3 55 VCC+0.3V 0.2* VCC +1 +1 25 5 70 µA ISB2 55 70 µA IZZ VCC = VCCMAX, ZZ < 0.2V, CE = HIGH or BHE and BLE = HIGH 10 µA Capacitance[11] Parameter CIN Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. 8 Unit pF Notes: 8. VIL(MIN) = –0.5V for pulse durations less than 20 ns. 9.VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns. 10.Overshoot and undershoot specifications are characterized and are not 100% tested. 11.Tested initially and after any design or process changes that may affect these parameters.. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 7/15 ESMT Thermal Resistance[11] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA/JESD51. M24L16161ZA VFBGA 56 11 Unit °C/W °C/W Parameters R1 R2 RTH VTH 3.0V VCC 26000 26000 13000 1.50 Unit Ω Ω Ω V Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 8/15 ESMT Switching Characteristics Over the Operating Range [12, 13, 14, 15, 18] Parameter Read Cycle tRC[17] tCD tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE Write Cycle[15] tWC tSCE tAW tCD tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Description Read Cycle Time Chip Deselect Time CE , BLE / BHE High Pulse Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[13, 14, 16] OE HIGH to High Z[13, 14, 16] CE LOW to Low Z[13, 14, 16] CE HIGH to High Z[13, 14, 16] BLE / BHE LOW to Data Valid BLE / BHE LOW to Low Z[13, 14, 16] BLE / BHE HIGH to High Z[13, 14, 16] M24L16161ZA -70 Min. 70 15 70 5 70 35 5 25 10 25 70 5 25 70 60 60 15 0 0 50 60 25 0 25 10 40000 Max. 40000 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write Cycle Time CE LOW to Write End Address Set-Up to Write End Chip Deselect Time CE , BLE / BHE High Pulse Time Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE / BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High-Z[13, 14, 16] WE HIGH to Low-Z[13, 14, 16] Notes: 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC/2, input pulse levels of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 13. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V). 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 15. The internal Write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 16. High-Z and Low-Z parameters are characterized and are not 100% tested. 17. If invalid address signals shorter than min. tRC are continuously repeated for 40 µs, the device needs a normal read timing (tRC) or needs to enter standby state at least once in every 40 µs.18.In order to achieve 70-ns performance, the read access must be CE controlled. That is, the addresses must be stable prior to CE going active. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 9/15 ESMT Switching Waveforms Read Cycle 1 (Address Transition Controlled)[20, 21] M24L16161ZA Read Cycle 2 ( OE Controlled) [19, 21] Notes: 19. Whenever CE , BHE / BLE are taken inactive, they must remain inactive for a minimum of 15 ns. 20. Device is continuously selected. OE , CE = VIL. 21. WE is HIGH for Read Cycle. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 10/15 ESMT Switching Waveforms (continued) M24L16161ZA Notes: 22.Data I/O is high-Impedance if OE > VIH. 23.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 11/15 ESMT Switching Waveforms (continued) Write Cycle 2 ( CE Controlled) [15, 16, 19, 22, 23] M24L16161ZA Write Cycle 3 ( WE Controlled, OE LOW)[19, 23] Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 12/15 ESMT Switching Waveforms (continued) Write Cycle 4 ( BHE / BLE Controlled, OE LOW)[15, 19, 22, 23] M24L16161ZA Truth Table[24, 25] ZZ H H H CE H X L L L L L L L L L L L H WE X X X OE X X X L L L H H H X X X X X BHE X H H BLE X H H Inputs/Outputs High Z High Z High Z Data Out (I/O0–I/O15) Data Out (I/O0–I/O7); (I/O8–I/O15) in High Z Data Out (I/O8–I/O15); (I/O0–I/O7) in High Z High Z High Z High Z Data In (I/O0–I/O15) Data In (I/O0–I/O7); (I/O8–I/O15) in High Z Data Out (I/O8–I/O15); (I/O0–I/O7) in High Z Data In (A0–A4) High Z Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write (Upper Byte and Lower Byte) Write (Lower Byte Only) Write (Upper Byte Only) Write (Variable Address Mode Register) Deep Power-down/PAR Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Deep Sleep (IZZ)/Standb H H H H H H H L L L L H H H H H H L L L L X L H L L H L L H L L X L L H L L H L L H L X Notes: 24.H = Logic HIGH, L = Logic LOW, X = Don’t Care. 25.During ZZ = L and CE = H, Mode depends on how the VAR is set up either in PAR or Deep Sleep Modes. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 13/15 ESMT Ordering Information Speed (ns) 70 Ordering Code M24L16161ZA -70BIG M24L16161ZA Package Type 48-ball Very Fine Pitch BGA (6 x 8 x 1 mm) (Pb-Free) Operating Range Industrial Package Diagrams Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 14/15 ESMT Important Notice All rights reserved. M24L16161ZA No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 15/15