M24L416256DA-55BEG

ESMT PSRAM Features • Advanced low-power architecture •High speed: 55 ns, 60 ns and 70 ns •Wide voltage range: 2.7V to 3.6V •Typical active current: 1 mA @ f = 1 MHz •Low standby power •Automatic power-down when deselected M24L416256DA 4-Mbit (256K x 16) Pseudo Static RAM reducing power consumption dramatically when deselected ( CE1 HIGH, CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected ( CE1 HIGH, CE2 LOW, OE is HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). Reading from the device is accomplished by asserting the Chip Enables ( CE1 LOW and CE2 HIGH) and Output Enable( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins A0 through A17 will appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table for a complete description of read and write modes. Functional Description The M24L416256DA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 1/15 ESMT Pin Configuration[3, 4, 5] M24L416256DA 44-pin TSOPII Top View A4 A3 A2 A1 A0 CE1 I/O0 I/O1 I/O2 I/O3 V CC V SS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BL E I/O 1 5 I/O 1 4 I/O 1 3 I/O 1 2 V SS V CC I/ O1 1 I/ O1 0 I/ O9 I/ O8 CE2 A8 A9 A1 0 A11 A1 7 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 2/15 ESMT Product Portfolio VCC Range(V) Speed (ns) Max. 55 M24L416256DA 2.7 3.0 3.6 60 70 1 5 Operating, ICC (mA) f = 1 MHz Typ.[2] Max. M24L416256DA Power Dissipation Product Min. Standby, ISB2 (µA) Typ.[2] Max. f = fMAX Typ.[2] 14 8 Max. 22 15 Typ. 17 40 Notes: 2.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25°C. 3.Ball H1, G2, H6 are the address expansion pins for the 8-Mb, 16-Mb, and 32-Mb densities, respectively. 4.NC “no connect”—not connected internally to the die. 5.DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper application. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 3/15 ESMT Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied ..............................................–55°C to +125°C Supply Voltage to Ground Potential ................−0.4V to 4.6V DC Voltage Applied to Outputs in High-Z State[6, 7, 8] .......................................−0.4V to 3.7V DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V Output Current into Outputs (LOW) ............................20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) M24L416256DA Latch-up Current ....................................................> 200 mA Operating Range Range Extended Industrial Ambient Temperature (TA) −25°C to +85°C −40°C to +85°C VCC 2.7V to 3.6V 2.7V to 3.6V DC Electrical Characteristics (Over the Operating Range) Parameter VCC VOH VOL VIH VIL IIX IOZ Description Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Test Conditions Min. 2.7 VCC – 0.4 0.4 0.8 * VCC F=0 GND ≤ VIN ≤ Vcc GND ≤ VOUT ≤ Vcc, Output Disabled f = fMAX = 1/tRC f = 1 MHz Automatic CE1 Power-down Current —CMOS Inputs Automatic CE1 Power-down Current —CMOS Inputs VCC = 3.6V, IOUT = 0 mA, CMOS level -0.4 -1 -1 14 for –55 14 for –60 08 for –70 1 for all speeds VCC + 0.4 0.62 +1 +1 22 for –55 22 for –60 15 for –70 5 for all speeds -55, 60, 70 Typ.[2] 3.0 Max. 3.6 Unit V V V V V µA µA IOH = −0.1 mA IOL = 0.1 mA ICC mA ISB1 CE1 ≥ VCC − 0.2V, CE2 ≤ 0.2V, VIN ≥ VCC − 0.2V, VIN ≤ 0.2V, f = fMAX(Address and Data Only),f = 0 ( OE , WE , BHE and BLE ) 150 250 µA ISB2 CE1 ≥ VCC − 0.2V, CE2 ≤ 0.2V, VIN ≥ VCC − 0.2V or VIN ≤ 0.2V, f = 0, VCC = 3.6V 17 40 µA Capacitance[9] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. 8 8 Unit pF pF Thermal Resistance[9] Parameter Description θJA θJC Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. VFBGA 55 17 Unit °C/W °C/W Notes: 6.VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 7.VIL(MIN) = –0.5V for pulse durations less than 20 ns. 8.Overshoot and undershoot specifications are characterized and are not 100% tested. 9.Tested initially and after design or process changes that may affect these parameters. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 4/15 ESMT AC Test Loads and Waveforms M24L416256DA Parameters R1 R2 RTH VTH 3.0V VCC 22000 22000 11000 1.50 Unit Ω Ω Ω V Switching Characteristics (Over the Operating Range)[10] Prameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[11, 12] OE HIGH to High Z[11, 12] CE1 LOW and CE2 HIGH to Low Z[11, 12] CE1 HIGH and CE2 LOW to High Z[11, 12] BLE / BHE LOW to Data Valid BLE / BHE LOW to Low Z[11, 12] –55 Min. 55[14] 55 5 55 25 5 25 5 25 55 5 10 0 55 45 45 0 0 60 45 45 0 0 5 5 5 8 Max. Min. 60 –60 Max. Min. 70 60 10 60 25 5 25 5 25 60 5 10 5 70 60 55 0 0 –70 Max. Unit ns ns ns ns ns ns ns ns 70 70 35 25 25 70 25 10 ns ns ns ns ns ns ns ns ns ns BLE / BHE HIGH to High-Z[11, 12] [14] tSK Address Skew Write Cycle[13] tWC Write Cycle Time tSCE CE1 LOW and CE2 HIGH to Write End tAW tHA tSA Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start Notes: 10. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance. 11. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. High-Z and Low-Z parameters are characterized and are not 100% tested. 13. The internal write time of the memory is defined by the overlap of WE , CE1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 5/15 ESMT Switching Characteristics (Over the Operating Range)[10] (continued) Prameter tPWE tBW tSD tHD tHZWE tLZWE Description WE Pulse Width BLE / BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High Z[11, 12] WE HIGH to Low Z[11, 12] M24L416256DA –55 Min. 40 50 25 0 25 5 5 Max. Min. 40 50 25 0 25 5 –60 Max. Min. 45 55 25 0 25 –70 Max. Unit ns ns ns ns ns ns Switching Waveforms Read Cycle 1 (Address Transition Controlled)[14, 15, 16] Read Cycle 2 ( OE Controlled)[14, 16] Notes: 15.Device is continuously selected. OE , CE = VIL. 16. WE is HIGH for Read Cycle. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 6/15 ESMT Switching Waveforms (continued) Write Cycle No. 1( WE Controlled)[12, 13, 17, 18, 19] M24L416256DA Notes: 17.Data I/O is high impedance if OE > VIH. 18.If Chip Enable goes INACTIVE simultaneously with WE =HIGH, the output remains in a high-impedance state. 19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 7/15 ESMT Switching Waveforms (continued) Write Cycle 2 ( CE1 or CE2 Controlled)[12, 13, 17, 18, 19] M24L416256DA Write Cycle 3 ( WE Controlled, OE LOW)[18, 19] Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 8/15 ESMT Switching Waveforms (continued) Write Cycle No. 4 ( BHE / BLE Controlled, OE LOW)[18, 19] M24L416256DA Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 9/15 ESMT Avoid Timing M24L416256DA ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15μs shown as in Avoidable timing 1 or toggle CE1 to high (≧tRC) one time at least shown as in Avoidable Timing 2. Abnormal Timing ≧15μs CE1 WE ＜ tRC Address Avoidable Timing 1 ≧15μs CE1 WE ≧ tRC Address Avoidable Timing 2 ≧15μs CE1 ≧ tRC WE ＜ tRC Address Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 10/15 ESMT Truth Table[20] CE1 H X X L M24L416256DA OE X X X L L L H H H X X X BHE X X H L BLE X X H L CE2 X L X H H H H H H H H H WE X X X H Inputs/Outputs High Z High Z High Z Data Out (I/O0–I/O15) Data Out (I/O0–I/O7); I/O8–I/O15 in High Z Data Out (I/O8–I/O15); I/O0–I/O7 in High Z High Z High Z High Z Data In (I/O0–I/O15) Data In (I/O0–I/O7); I/O8–I/O15 in High Z Data In (I/O8–I/O15); I/O0–I/O7 in High Z Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Read (Upper Byte and Lower Byte) Read (Upper Byte only) Read (Lower Byte only) Output Disabled Output Disabled Output Disabled Write (Upper Byte and Lower Byte) Write (Lower Byte Only) Write (Upper Byte Only) Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) L L L L L L L L H H H H H L L L H L L H L L H L L H L L H L L H Note: 20.H = Logic HIGH, L = Logic LOW, X = Don’t Care. Ordering Information Speed (ns) 55 60 70 55 60 70 55 60 70 55 60 70 Ordering Code M24L416256DA-55BEG M24L416256DA-60BEG M24L416256DA-70BEG M24L416256DA-55TEG M24L416256DA-60TEG M24L416256DA-70TEG M24L416256DA-55BIG M24L416256DA-60BIG M24L416256DA-70BIG M24L416256DA-55TIG M24L416256DA-60TIG M24L416256DA-70TIG Package Type 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 44-pin TSOPII (Pb-Free) 44-pin TSOPII (Pb-Free) 44-pin TSOPII (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 44-pin TSOPII (Pb-Free) 44-pin TSOPII (Pb-Free) 44-pin TSOPII (Pb-Free) Operating Range Extended Extended Extended Extended Extended Extended Industrial Industrial Industrial Industrial Industrial Industrial Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 11/15 ESMT Package Diagram 48-ball VFBGA (6 x 8 x 1 mm) M24L416256DA Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 12/15 ESMT 44-LEAD TSOP(II) PSRAM(400mil) M24L416256DA Symbol Dimension in mm Min A A1 A2 B B1 C C1 D ZD E E1 L L1 e 11.56 10.03 0.40 0.05 0.95 0.30 0.30 0.12 0.10 18.28 1.00 0.35 Norm Max 1.20 0.15 1.05 0.45 0.40 0.21 0.16 18.54 11.96 10.29 0.69 Dimension in inch Min 0.002 0.037 0.012 0.012 0.005 0.004 0.720 0.455 0.395 0.016 0.039 0.014 Norm Max 0.047 0.006 0.042 0.018 0.016 0.008 0.006 0.730 0.471 0.4 0.027 18.41 0.805 REF 11.76 10.16 0.59 0.80 REF 0.80 BSC 0.725 0.0317 REF 0.463 0.400 0.023 0.031 REF 0.0315 BSC θ 0° 8° 0° 8° Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 13/15 ESMT Revision History Revision 1.0 1.1 1.2 1.3 1.4 1.5 Date 2007.07.04 2007.11.20 2007.11.22 2008.02.27 2008.03.24 2008.07.04 Original Description M24L416256DA Modify the descriptive error for standby mode, tHZWE and tLZWE description Modify tHZBE and tLZBE descriptive and restore tHZWE and tLZWE description 1.Add 44-pin TSOPII package 2. Add Avoid timing Add I-grade for TSOPII package 1. Move Revision History to the last 2. Modify voltage range 2.7V~3.3V to 2.7V~3.6V 3. Add Industrial grade for BGA package Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 14/15 ESMT Important Notice All rights reserved. M24L416256DA No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.5 15/15