M24L416256SA-70TEG

ESMT PSRAM Features • Wide voltage range: 2.7V–3.6V • Access time: 55 ns, 60 ns and 70 ns • Ultra-low active power — Typical active current: 1 mA @ f = 1 MHz — Typical active current: 8 mA @ f = fmax (70-ns speed) • Ultra low standby power • Automatic power-down when deselected • CMOS for optimum speed/power M24L416256SA 4-Mbit (256K x 16) Pseudo Static RAM The input/output pins (I/O0through I/O15) are placed in a high-impedance state when : deselected ( CE HIGH), outputs are disabled ( OE HIGH), both Byte High Enable and Byte Low Enable are disabled ( BHE , BLE HIGH), or during a write operation ( CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable( CE LOW) and Write Enable ( WE ) input LOW. If Byte Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins(A0 through A17). If Byte High Enable ( BHE ) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable ( CE LOW) and Output Enable ( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable( BHE ) is LOW, then data from memory will appear on I/O8 toI/O15. Refer to the truth table for a complete description of read and write modes. Functional Description The M24L416256SA is a high-performance CMOS Pseudo static RAM organized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode when deselected ( CE HIGH or both BHE and BLE are HIGH). Logic Block Diagram Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 1/14 ESMT Pin Configuration[2, 3, 4] M24L416256SA 44-pin TSOPII Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 V CC V SS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BL E I/O 1 5 I/O 1 4 I/O 1 3 I/O 1 2 V SS V CC I/ O1 1 I/ O1 0 I/ O9 I/ O8 NC A8 A9 A1 0 A11 A1 7 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 2/14 ESMT Product Portfolio VCC Range(V) Speed (ns) Max. 55 M24L416256SA 2.7 3.0 3.6 60 70 1 5 Operating, ICC (mA) f = 1 MHz Typ.[5] Max. M24L416256SA Power Dissipation Product Min. Standby, ISB2 (µA) Typ.[5] Max. f = fmax Typ.[5] 14 8 Max. 22 15 Typ.[5] 17 40 Notes: 2. Ball H1, G2 and ball H6 for the VFBGA package can be used to upgrade to an 8-Mbit, 16-Mbit and 32-Mbit density, respectively. 3. NC “no connect” – not connected internally to the die. 4. DNU (Do Not Use) pins have to be left floating or tied to Vss to ensure proper application. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 3/14 ESMT Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied ..............................................–55°C to +125°C Supply Voltage to Ground Potential ................−0.4V to 4.6V DC Voltage Applied to Outputs in High-Z State[6, 7, 8] .......................................−0.4V to 3.7V DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V Output Current into Outputs (LOW) ............................20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) M24L416256SA Latch-up Current ....................................................> 200 mA Operating Range Range Extended Industrial Ambient Temperature (TA) −25°C to +85°C −40°C to +85°C VCC 2.7V to 3.6V 2.7V to 3.6V DC Electrical Characteristics (Over the Operating Range) Parameter VCC VOH VOL VIH VIL IIX IOZ Description Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Test Conditions Min. 2.7 VCC – 0.4 0.4 0.8 * VCC -0.4 GND ≤ VIN ≤ Vcc GND ≤ VOUT ≤ Vcc, Output Disabled f = fMAX = 1/tRC f = 1 MHz Automatic CE Power-down Current —CMOS Inputs Automatic CE Power-down Current —CMOS Inputs VCC = VCCmax, IOUT = 0 mA, CMOS level -1 -1 14 for –55 14 for –60 8 for –70 1 for all speeds VCC + 0.4 0.6 +1 +1 22 for –55 22 for –60 15 for –70 5 for all speeds -55, 60, 70 Typ.[5] 3.0 Max. 3.6 Unit V V V V V µA µA IOH = −0.1 mA IOL = 0.1 mA VCC = 2.7V VCC = 2.7V ICC mA ISB1 CE ≥ VCC − 0.2V, VIN ≥ VCC − 0.2V, VIN ≤ 0.2V, f = fMAX(Address and Data Only),f = 0 ( OE , WE , BHE and BLE ), VCC = 3.6V CE ≥ VCC − 0.2V, VIN ≥ VCC − 0.2V or VIN ≤ 0.2V, f = 0, VCC = 3.6V 150 250 µA ISB2 17 40 µA Thermal Resistance[9] Parameter θJA θJC Description Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. VFBGA 55 17 Unit °C/W °C/W Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Capacitance[9] Parameter Description Test Conditions Max. CIN Input Capacitance TA = 25°C, f = 1 MHz 8 VCC = VCC(typ) COUT Output Capacitance 8 Notes: 6.VIL(MIN) = –0.5V for pulse durations less than 20 ns. 7.VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns. 8.Overshoot and undershoot specifications are characterized and are not 100% tested. 9.Tested initially and after any design or process changes that may affect these parameters. Unit pF pF Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 4/14 ESMT AC Test Loads and Waveforms M24L416256SA Parameters R1 R2 RTH VTH 3.0V VCC 22000 22000 11000 1.50 Unit Ω Ω Ω V Switching Characteristics (Over the Operating Range)[10] Prameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[11, 13] OE HIGH to High Z[11, 13] CE LOW to Low Z[11, 13] CE HIGH to High Z[11, 13] BLE / BHE LOW to Data Valid 5 10 0 55 45 45 0 0 40 60 45 45 0 0 40 2 25 55 5 10 5 70 60 55 0 0 45 5 25 2 25 60 5 25 10 –55 Min. 55 55 5 55 25 5 25 5 25 70 8 60 25 5 25 Max. Min. 60 60 10 70 35 –60 Max. Min. 70 70 –70 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns BLE / BHE LOW to Low Z[11, 13] tHZBE BLE / BHE HIGH to High-Z[11, 13] [14] tSK Address Skew Write Cycle[12] tWC Write Cycle Time tSCE CE LOW to Write End tAW Address Set-up to Write End tHA Address Hold from Write End tSA Address Set-up to Write Start tPWE WE Pulse Width Notes: 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0V to V CC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal Write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 13. High-Z and Low-Z parameters are characterized and are not 100% tested. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 5/14 ESMT Switching Characteristics (Over the Operating Range)[10] (continued) Prameter tBW tSD tHD tHZWE tLZWE Description BLE / BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High Z[11, 13] WE HIGH to Low Z[11, 13] M24L416256SA –55 Min. 50 25 0 25 5 5 Max. Min. 50 25 0 25 5 –60 Max. Min. 55 25 0 25 –70 Max. Unit ns ns ns ns ns Switching Waveforms Read Cycle 1 (Address Transition Controlled)[14, 15, 16] Read Cycle 2 ( OE Controlled)[14, 16] Notes: 15.Device is continuously selected. OE , CE = VIL. 16. WE is HIGH for Read Cycle. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 6/14 ESMT Switching Waveforms (continued) Write Cycle 1 ( WE Controlled)[12, 13, 17, 18, 19] M24L416256SA Write Cycle 2 ( CE Controlled)[12, 13, 17, 18, 19] Notes: 17.Data I/O is high-impedance if OE ≥ VIH. 18.If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state. 19.During this period in the DATA I/O waveform, the I/Os could be in the output state and input signals should not be applied. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 7/14 ESMT Switching Waveforms (continued) Write Cycle 3 ( WE Controlled, OE LOW)[18, 19] M24L416256SA Write Cycle 4 ( BHE / BLE Controlled, OE LOW)[18, 19] Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 8/14 ESMT Avoid Timing M24L416256SA ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15μs shown as in Avoidable timing 1 or toggle CE to high (≧tRC) one time at least shown as in Avoidable Timing 2. Abnormal Timing ≧ 15μ s CE WE ＜ tRC Address Avoidable Timing 1 ≧ 15μ s CE WE ≧ tRC Address Avoidable Timing 2 ≧ 15μ s CE ≧ tRC WE ＜ tRC Address Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 9/14 ESMT Truth Table[20] CE1 H X L WE X X H M24L416256SA BHE X H L BLE X H L OE X X L L L H H H X X X Inputs/Outputs High Z High Z Data Out (I/O0–I/O15) Data Out (I/O0–I/O7); High Z I/O8–I/O15 High Z I/O0–I/O7 ; Data Out (I/O8–I/O15) High Z High Z High Z Data In (I/O0–I/O15) Data In (I/O0–I/O7); High Z I/O8–I/O15 High Z I/O0–I/O7; Data In (I/O8–I/O15) Mode Deselect/Power-down Deselect/Power-down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) L L L L L L L L H H H H H L L L H L L H L L H L L H H L L L L H Ordering Information Speed (ns) 55 60 70 55 60 70 55 60 70 55 60 70 Ordering Code M24L416256SA-55BEG M24L416256SA-60BEG M24L416256SA-70BEG M24L416256SA-55TEG M24L416256SA-60TEG M24L416256SA-70TEG M24L416256SA-55BIG M24L416256SA-60BIG M24L416256SA-70BIG M24L416256SA-55TIG M24L416256SA-60TIG M24L416256SA-70TIG Package Type 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 44-pin TSOPII (Pb-Free) 44-pin TSOPII (Pb-Free) 44-pin TSOPII (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 44-pin TSOPII (Pb-Free) 44-pin TSOPII (Pb-Free) 44-pin TSOPII (Pb-Free) Operating Range Extended Extended Extended Extended Extended Extended Industrial Industrial Industrial Industrial Industrial Industrial Note : 20. H = Logic HIGH, L = Logic LOW, X = Don’t Care. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 10/14 ESMT Package Diagram 48-ball VFBGA (6 x 8 x 1 mm) M24L416256SA Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 11/14 ESMT 44-LEAD TSOP(II) PSRAM(400mil) M24L416256SA Symbol Dimension in mm Min A A1 A2 B B1 C C1 D ZD E E1 L L1 e 11.56 10.03 0.40 0.05 0.95 0.30 0.30 0.12 0.10 18.28 18.41 0.805 REF 11.96 10.29 0.69 11.76 10.16 0.59 0.80 REF 0.80 BSC 1.00 0.35 Norm Max 1.20 0.15 1.05 0.45 0.40 0.21 0.16 18.54 Dimension in inch Min 0.002 0.037 0.012 0.012 0.005 0.004 0.720 0.455 0.395 0.016 0.725 0.0317 REF 0.463 0.400 0.023 0.031 REF 0.0315 BSC 0.471 0.4 0.027 0.039 0.014 Norm Max 0.047 0.006 0.042 0.018 0.016 0.008 0.006 0.730 θ 0° 8° 0° 8° Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 12/14 ESMT Revision History Revision 1.0 1.1 1.2 1.3 1.4 Date 2007.07.04 2007.09.10 2008.02.27 2008.03.24 2008.07.04 Original Modify Vcc (max) =3.3V to 3.6V 1. Add 44-pin TSOPII package 2. Add Avoid timing Add I-grade for TSOPII package 1. Move Revision History to the last 2. Add Industrial grade for BGA package Description M24L416256SA Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 13/14 ESMT Important Notice All rights reserved. M24L416256SA No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 14/14