M24L816512SA

ESMT PSRAM Features ‧Advanced low-power architecture • High speed: 55 ns, 70 ns • Wide voltage range: 2.7V to 3.6V • Typical active current: 2 mA @ f = 1 MHz • Typical active current: 11 mA @ f = fMAX • Low standby power • Automatic power-down when deselected M24L816512SA 8-Mbit (512K x 16) Pseudo Static RAM Byte Low Enable are disabled ( BHE , BLE HIGH), or during a write operation ( CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable( CE LOW) and Write Enable ( WE ) input LOW. If Byte Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins(A0 through A18). If Byte High Enable ( BHE ) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable ( CE LOW) and Output Enable ( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable( BHE ) is LOW, then data from memory will appear on I/O8 toI/O15. Refer to the truth table for a complete description of read and write modes. Functional Description The M24L816512SA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 512K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode when deselected ( CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0through I/O15) are placed in a high-impedance state when : deselected ( CE HIGH), outputs are disabled ( OE HIGH), both Byte High Enable and Logic Block Diagram Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 1/14 ESMT Pin Configuration[2, 3, 4] 48-ball VFBGA Top View M24L816512SA 44-Pin TSOPII(Note*) Top View (Default) A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 V CC V SS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BL E I/O 1 5 I/O 1 4 I/O 1 3 I/O 1 2 V SS V CC I/ O1 1 I/ O1 0 I/ O9 I/ O8 A1 8 A8 A9 A1 0 A11 A1 7 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC V SS I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (TypeA) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O 15 I/O 14 I/O 13 I/O 12 V SS V CC I/O 11 I/O 10 I/O 9 I/O 8 A8 A9 A1 0 A11 A1 2 A1 3 Note* : The default pin arrangement of TSOPII package of the device is as ”Default” figure. User also can control pin 18~28 to turn into pin arrangement of “Type A” with software. (The difference in pin arrangement between ”Default” and “Type A” is pin 18~28) Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 2/14 ESMT Product Portfolio Product M24L816512SA Power Dissipation Product Min. M24L816512SA 2.7 VCC Range (V) Speed(ns) Max. 3.6 55 70 Operating ICC(mA) f = 1MHz Typ.[5] 2 Max. 5 f = fMAX Typ.[5] 11 Max. 22 17 Standby, ISB2(µA) Typ. [5] 55 100 110(for Vcc > 3.3V) Max. Typ. 3.0 Notes: 2.DNU pins are to be left floating or tied to VSS. 3.Ball G2, H6 are the address expansion pins for the 16-Mbit and 32-Mbit densities respectively. 4.NC “no connect”—not connected internally to the die. 5.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25°C. Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 3/14 ESMT Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied ..............................................–55°C to +125°C Supply Voltage to Ground Potential ................−0.4V to 4.6V DC Voltage Applied to Outputs in High-Z State[6, 7, 8] .......................................−0.4V to 3.7V DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V Output Current into Outputs (LOW) ............................20 mA M24L816512SA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current ....................................................> 200 mA Operating Range Range Extended Industrial Ambient Temperature (TA) −25°C to +85°C −40°C to +85°C VCC 2.7V to 3.6V 2.7V to 3.6V DC Electrical Characteristics (Over the Operating Range) [5, 6, 7, 8] -55 Parameter VCC VOH VOL VIH VIL IIX IOZ ICC Description Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current —CMOS Inputs Automatic CE Power-Down Current —CMOS Inputs Test Conditions Min. IOH = −0.1 mA IOL = 0.1 mA 0.8* VCC -0.4 -1 -1 11 2 2.7 VCC0.4 Typ .[5] 3.0 Max. 3.6 Min. 2.7 VCC0.4 0.8* VCC -0.4 -1 -1 11 2 -70 Typ. [5] 3.0 Unit Max. 3.6 V V 0.4 VCC+0 .4V 0.4 +1 +1 17 5 mA V V V µA µA 0.4 VCC+ 0.4V 0.4 +1 +1 22 5 f=0 GND ≤ VIN < VCC GND ≤ VOUT ≤ VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 3.6V IOUT = 0mA CMOS level ISB1 CE ≥ VCC − 0.2V, VIN ≥ VCC − 0.2V, VIN ≤ 0.2V, f = fMAX (Address and Data Only), f = 0 BLE ) ( OE , WE , BHE and 100 400 100 400 µA ISB2 CE ≥ VCC−0.2V, VIN ≥ VCC − 0.2V or VIN ≤ 0.2V, f=0 VCC = 3.3V VCC = 3.6V 55 100 110 55 100 110 µA Capacitance[9] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. 8 8 Unit pF pF Thermal Resistance[9] Parameter ΘJA ΘJC Description Thermal Resistance(Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/ JESD51. BGA 55 17 Unit °C/W °C/W Notes: 6.VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 7.VIL(MIN) = –0.5V for pulse durations less than 20 ns. 8.Overshoot and undershoot specifications are characterized and are not 100% tested. 9.Tested initially and after design or process changes that may affect these parameters. Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 4/14 ESMT AC Test Loads and Waveforms M24L816512SA Parameters R1 R2 RTH VTH 3.0V VCC 22000 22000 11000 1.50 Unit Ω Ω Ω V Switching Characteristics Over the Operating Range[10, 11, 12, 13, 14] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE tSK[14] Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to LOW Z[11, 12] OE HIGH to High Z[11, 12] CE LOW to Low Z[11, 12] CE HIGH to High Z[11, 12] BLE / BHE LOW to Data Valid BLE / BHE LOW to Low Z[11, 12] BLE / BHE HIGH to High Z[11, 12] Address Skew -55 Min. 55[14] 55 5 55 25 5 25 5 25 55 5 10 0 5 5 5 5 Max. Min. 70 -70 Max. Unit ns ns ns ns ns ns 70 70 35 25 ns ns 25 70 ns ns ns 25 10 ns ns Notes: 10. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V CC(typ)/2, input pulse levels of 0V to V CC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance 11. tHZOE, tHZCE, tHZBE, and tHZWEtransitions are measured when the outputs enter a high-impedance state. 12. High-Z and Low-Z parameters are characterized and are not 100% tested. 13. The internal write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 5/14 ESMT Parameter Write Cycle[13] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Description Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE / BHE LOW to Write End M24L816512SA Switching Characteristics (Over the Operating Range) (continued)[10, 11, 12, 13, 14] -55 Min. 55 45 45 0 0 40 50 42 0 25 5 5 Max. Min. 70 55 55 0 0 55 55 42 0 25 -70 Max. Unit ns ns ns ns ns ns ns ns ns ns ns Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[11, 12] WE HIGH to Low-Z[11, 12] Switching Waveforms Read Cycle 1 (Address Transition Controlled)[14, 15, 16] Read Cycle 2 ( OE Controlled)[14, 15] Notes: 15. WE is HIGH for Read Cycle. 16. Device is continuously selected. OE , CE = VIL Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 6/14 ESMT Switching Waveforms (continued) Write Cycle 1 ( WE Controlled) [12, 13, 17, 18, 19] M24L816512SA Write Cycle 2 ( CE Controlled) [12, 13, 17, 18, 19] Notes: 17.Data I/O is high impedance if OE ≥ VIH. 18.If Chip Enable goes INACTIVE simultaneously with WE = HIGH, the output remains in a high-impedance state. 19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 7/14 ESMT Switching Waveforms (continued) Write Cycle 3 ( WE Controlled, OE LOW)[18, 19] M24L816512SA Write Cycle 4 ( BHE / BLE Controlled, OE LOW)[18, 19] Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 8/14 ESMT Avoid Timing M24L816512SA ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15μs shown as in Avoidable timing 1 or toggle CE to high (≧tRC) one time at least shown as in Avoidable Timing 2. Abnormal Timing ≧ 15μ s CE WE ＜ tRC Address Avoidable Timing 1 ≧ 15μ s CE WE ≧ tRC Address Avoidable Timing 2 ≧ 15μ s CE ≧ tRC WE ＜ tRC Address Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 9/14 ESMT Truth Table[20] CE H X L L L L L L L L L WE X X M24L816512SA OE X X L L L H H H X X X BHE X H BLE X H Inputs/Outputs High Z High Z Data Out (I/O0–I/O15) Data Out (I/O0–I/O7); (I/O8–I/O15) in High Z Data Out (I/O8–I/O15); (I/O0–I/O7) in High Z High Z High Z High Z Data In (I/O0–I/O15) Data In (I/O0–I/O7); (I/O8–I/O15) in High Z Data Out (I/O8–I/O15); (I/O0–I/O7) in High Z Mode Deselect/Power-Down Deselect/Power-Down Read (Upper Byte and Lower Byte) Read (Lower Byte only) Read (Upper Byte only) Output Disabled Output Disabled Output Disabled Write (Upper Byte and Lower Byte) Write (Lower Byte Only) Write (Upper Byte Only) Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) H H H H H H L L L L H L L H L L H L L L H L L H L L H Ordering Information Speed (ns) 55 70 55 70 55 70 55 70 Ordering Code M24L816512SA-55BEG M24L816512SA -70BEG M24L816512SA-55TEG M24L816512SA-70TEG M24L816512SA-55BIG M24L816512SA-70BIG M24L816512SA-55TIG M24L816512SA-70TIG Package Type 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free) 44-pin TSOPII (Pb-Free) 44-pin TSOPII (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free) 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free) 44-pin TSOPII (Pb-Free) 44-pin TSOPII (Pb-Free) Operating Range Extended Extended Extended Extended Industrial Industrial Industrial Industrial Note: 20.H = Logic HIGH, L = Logic LOW, X = Don’t Care. Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 10/14 ESMT Package Diagrams 48-Ball (6 mm x 8mm x 1.2 mm) FBGA M24L816512SA Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 11/14 ESMT 44-LEAD TSOP(II) PSRAM(400mil) M24L816512SA Symbol Min A A1 A2 B B1 C C1 D ZD E E1 L L1 e 0.05 0.95 0.30 0.30 0.12 0.10 Dimension in mm Norm Max 1.20 0.15 1.00 1.05 0.45 0.35 0.40 0.21 0.16 18.41 0.805 11.56 10.03 0.40 REF 11.96 10.29 0.69 18.54 Dimension in inch Min Norm Max 0.047 0.002 0.037 0.012 0.012 0.005 0.004 0.720 0.725 0.0317 REF 0.455 0.395 0.016 0.463 0.400 0.023 0.031 REF 0.471 0.4 0.027 0.014 0.039 0.006 0.042 0.018 0.016 0.008 0.006 0.730 18.28 11.76 10.16 0.59 0.80 REF 0.80 BSC 0.0315 BSC θ 0° 8° 0° 8° Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 12/14 ESMT Revision History Revision 1.0 1.1 1.2 1.3 1.4 1.5 Date 2008.02.27 2008.03.24 2008.06.23 2008.07.04 2009.02.20 2009.06.22 Description M24L816512SA Original Add I-grade for TSOPII package 1. Move Revision History to the last 2. Modify voltage range from 2.7V~3.3V to 2.7V~3.6V Add Industrial grade for BGA package 1.Correct Logic Block Diagram 2.Correct the ball name of H1 in BGA configuration Correct the ball name of D3 in BGA configuration Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 13/14 ESMT Important Notice All rights reserved. M24L816512SA No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009 Revision : 1.5 14/14