ES6218SAF

ESS Technology, Inc. DESCRIPTION ES6218A Vibratto-S Automotive DVD Processor Product Brief FEATURES • Single-chip DVD processor. • Integrated NTSC/PAL encoder with pixel-adaptive de-interlacer and three 10-bit 54 MHz video DACs. The ES6218A VibrattoS DVD processor is a super highperformance single-chip MPEG video decoding solution that is ideal for automotive DVD applications. The chip integrates CPRM and S/PDIF input and output support. The ES6218A performs audio/video stream data processing, TV encoding, Macrovision copy protection, DVD system navigation, system control, and housekeeping functions. The Vibratto-S DVD processor is built on the ESS proprietar y dual CPU Programmable Multimedia Processor (PMP) core consisting of 32-bit RISC and 64-bit DSP processors and offers the best DVD feature set. The processing units enable simultaneous parallel execution of system commands and data processing to perform specialized encoding and decoding tasks. The RISC processor performs bit stream parsing, control audio data output, transfer video and audio data to the vector engine and service system control and housekeeping functions. The vector engine performs audio and video micro-code processing required by A/V standards, such as Dolby  D igital, DTS  s urround, MPEG and JPEG imaging. These processing tasks include video motion compensation and estimation, loop filtering, Discrete Cosine Transforms (DCT), inverse DCT, quantization, and inverse quantization. The Vibratto-S DVD processor supports both parallel and serial DVD loader interfaces, industry standard I2S audio data input and output, EPROM and DRAM access, and audio/video data buffering. It also supports both letterbox and pan-and-scan displays, sub-picture overlay, and OnScreen Display (OSD). The Vibratto-S DVD solution also offers support for Karaoke CD+G, HDCD, CD-DA, DVD-Audio, MP3, and WMA. The ES6218A DVD processor is available in a 208-pin Low-profile Quad Flat Pack (LQFP) package with leadfree leads. The silicon is qualified for an extended temperature range of –40 to 85 ° C for automotive applications. • DVD-Video, DVD-VR, VCD 1.1 and 2.0. • Media playback with CD-ROM, CD-R/RW, DVD-R/RW, DVD+R/RW, and DVD-RAM. • Full DVD-Audio support including MLP and Linear PCM decoding, CPPM and watermark detection. • Up to 7.1 channel audio outputs. • • • • Interface for IDE devices, A/V DVD loaders and flash. Interface for CF, MS, MMC, SD, and SM memory cards. Direct interface of 8-/16-bit DRAM up to 128-Mb capacity. Direct interface for up to 4 banks of 8-/16-bit EPROM or Flash EPROM for up to 4-MB for each bank. • Macrovision 7.1 for NTSC/PAL interlaced video. • Composite, S-video and RGB or YUV outputs. • CCIR 656/601 YUV 4:2:2 input and output. • On-Screen Display controller supports 256 colors in 8 degrees of transparency. • Subpicture Unit (SPU) decoder supports karaoke lyric, subtitles, and EIA-608 compliant Line 21 Captioning. • JPEG digital photo CD support (Kodak Picture CD and Fujifilm FujiColor CD). • ESS Music Slideshow™. • • • • • • • Dolby Digital (AC-3), Dolby Pro Logic™, and Pro Logic II. DTS surround. S/PDIF digital audio input and output. MPEG AAC and Multichannel. SRS TruSurround and TruSurround XT. Windows™ Media Audio (WMA). Extended temperature range –40 to 85 °C ambient for automotive applications. • Slave mode for control by host processor. • Lead-free leads using 98%-Sn/2%-Cu or 98%-Sn/2%-Bi. ESS Technology, Inc. SAM0575-021805 1 2 VEE HA2/AUX4[4] VEE I2CDATA/AUX0 I2C_CLK/AUX1 AUX2/IOW# VSS VEE AUX3/IOR# AUX4 AUX5 AUX6 AUX7 LOE# VSS VCC PIXOUT_CLK/LCS0# LCS1# LCS2# LCS3# VSS LD0 LD1 LD2 LD3 LD4 VEE VSS LD5 LD6 LD7 LD8 LD9 LD10 LD11 VSS VEE LD12 LD13 LD14 LD15 LWRLL# LWRHL# VSS VEE PIXIN0/CAMIN0 PIXIN1/CAMIN1 LA0 LA1 LA2 LA3 VSS 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 ES6218A PINOUT DIAGRAM The device pinout for the ES6218A is shown in Figure 1. SAM0575-021805 ES6218A Figure 1 ES6218A Device Pinout 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 VEE VSS DSCK DQM DCS0# VEE VSS DCS1# DB15 DB14 DB13 DB12 VEE VSS DB11 DB10 DB9 DB8 DB7 DB6 VSS VCC DB5 DB4 DB3 DB2 DB1 DB0 VSS VEE DMBS1 DMBS0 DRAS# DWE# DOE#/DSCK_EN DCAS# VEE VSS DMA11 DMA10 DMA9 DMA8 DMA7 DMA6 VSS VEE DMA5 DMA4 DMA3 DMA2 DMA1 DMA0 VEE LA4 LA5 LA6 LA7 LA8 LA9 VSS VCC LA10 LA11 LA12 LA13 LA14 LA15 LA16 VSS VEE LA17 LA18 LA19 LA20 LA21 RESET# TDMDX/RSEL VSS VEE TDMDR TDMCLK TDMFS TDMTSC# TWS/SEL_PLL2 TSD0/SEL_PLL0 VSS VCC TSD1/SEL_PLL1 TSD2 TSD3 MCLK TBCK SEL_PLL3/SPDIF_OUT SPDIF_IN VSS VCC RSD RWS RBCK PIXIN3/CAMIN3 XIN XOUT AVEE AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VSS HA1/AUX4[3] HA0/AUX4[2] HCS3FX#/AUX3[6] HCS1FX#/AUX3[7] HIOCS16#/CAMCLK/AUX3[4]/PIXIN_CLK HRD#/DCI_ACK#/AUX4[6] HWR#/DCI_CLK/AUX4[5] VEE VSS HIORDY/AUX3[3] HRST#/AUX3[5] HIRQ/DCI_ERR#/AUX4[7] HRRQ#/AUX4[0]/CAMIN2/PIXIN2 HWRQ#/DCI_REQ#/AUX4[1] HD15/AUX2[7]/IR HD14/AUX2[6] VCC VSS HD13/AUX2[5]/SP HD12/AUX2[4]/C2PO HD11/AUX2[3]//IRQ HD10/AUX2[2] HD9/AUX2[1] HD8/DCI_FDS#/AUX2[0]/VFD_CLK HD7/DCI7/AUX1[7]/VFD_DIN VEE VSS HD6/DCI6/AUX1[6]/VFD_DOUT HD5/DCI5/AUX1[5] HD4/DCI4/AUX1[4] HD3/DCI3/AUX1[3] HD2/DCI2/AUX1[2] HD1/DCI1/AUX1[1] HD0/DCI0/AUX1[0] VCC VSS HSYNC#/CAMIN7/AUX3[0]/PIXIN7 VSYNC#/CAMIN6/AUX3[1]/PIXIN6 PCLKQSCN/CAMIN5/AUX3[2]/PIXIN5 PCLK2XSCN/CAMIN4/PIXIN4 YUV7/PIXOUT7 YUV6/PIXOUT6 YUV5/YDAC/PIXOUT5 ADVSS ADVEE YUV4/RSET/PIXOUT4 YUV3/COMP/PIXOUT3 YUV2/CDAC/PIXOUT2 YUV1/VREF/PIXOUT1 YUV0/UDAC/PIXOUT0 DCLK ES6218A PRODUCT BRIEF ES6218A PINOUT DIAGRAM ESS Technology, Inc. ES6218A PRODUCT BRIEF ES6218A PIN DESCRIPTION ES6218A PIN DESCRIPTION Table 1 lists the pin descriptions for the ES6218A. Table 1 ES6218A Pin Description Name Pin Numbers 1,18, 27, 59, 68, 75, 92, 99, 104, 130, 148, 157, 159, 164, 183, 193, 201 2-7, 10-16, 19-23, 204-207 8, 17, 26, 34, 43, 60, 67, 76, 84, 91, 98, 103, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 9, 35, 44, 83, 121, 139, 172 24 I/O Definition VEE P I/O power supply. LA[21:0] O RISC port address bus. VSS G Ground. VCC RESET# TDMDX P I O I Core power supply. Reset input. TDM transmit data output. LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ resistor; read only during reset. RSEL 0 1 Selection 16-bit ROM 8-bit ROM RSEL 25 TDMDR TDMCLK TDMFS TDMTSC# TWS 28 29 30 31 I I I O O I TDM receive data input. TDM clock input. TDM frame sync input. TDM output enable. Audio transmit frame sync output. System and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Strapped to VCC or ground via 4.7-kΩ resistor; read only during reset. SEL_PLL2 0 SEL_PLL1 0 0 1 1 0 0 1 1 SEL_PLL0 0 1 0 1 0 1 0 1 PLL Settings DCLK × 4.5 DCLK × 5.0 Bypass DCLK × 4.0 DCLK × 4.25 DCLK × 4.75 DCLK × 5.5 DCLK × 6.0 SEL_PLL2 32 0 0 0 1 1 1 1 ESS Technology, Inc. SAM0575-021805 3 ES6218A PRODUCT BRIEF ES6218A PIN DESCRIPTION Table 1 ES6218A Pin Description (Continued) Name TSD0 33 SEL_PLL0 TSD1 36 SEL_PLL1 TSD2 TSD3 MCLK TBCK SPDIF_OUT 37 38 39 40 I O O I/O I/O O I 41 SEL_PLL3 Refer to the description and matrix for SEL_PLL2 pin 32. Audio transmit serial data output 2. This pin must be pulled down to VSS via a 4.7-kΩ resistor for proper operation. Audio transmit serial data output 3. Audio master clock for audio DAC. Audio transmit bit clock. TBCK is an input during reset and subsequently is programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4). S/PDIF output. Clock source select. Strapped to VCC or ground via 4.7-kΩ resistor; read only during reset. SEL_PLL3 0 1 SPDIF_IN RSD RWS RBCK CAMIN3 48 PIXIN3 XIN XOUT AVEE AVSS DMA[11:0] DCAS# DOE# 70 DSCK_EN DWE# DRAS# DMBS0 DMBS1 DB[15:0] DCS[1:0]# DQM DSCK 71 72 73 74 77-82, 85-90, 93-96 97,100 101 102 O O O O O I/O O O O DRAM clock enable. DRAM write enable. DRAM row address strobe. DRAM bank select 0. DRAM bank select 1. DRAM data bus. DRAM chip select. Data input/output mask. Output clock to DRAM. 49 50 51 52 53-58, 61-66 69 I I O P G O O O CCIR656 input pixel 3. 27-MHz crystal input. 27-MHz crystal output. Analog power for PLL. Analog ground for PLL. DRAM address bus. DRAM column address strobe. DRAM output enable. 42 45 46 47 I I I I I S/PDIF input. Audio receive serial data. Audio receive frame sync. Audio receive bit clock. Camera YUV 3. Clock Source Crystal oscillator DCLK input I O Refer to the description and matrix for SEL_PLL2 pin 32. Audio transmit serial data output 1. Pin Numbers I/O O Definition Audio transmit serial data output 0. 4 SAM0575-021805 ESS Technology, Inc. ES6218A PRODUCT BRIEF ES6218A PIN DESCRIPTION Table 1 ES6218A Pin Description (Continued) Name DCLK UDAC Pin Numbers 105 I/O I O Definition Clock input to PLL. Video DAC output. Value 0 1 2 3 4 5 6 7 106 8 9 10 11 12 13 14 Y DAC C DAC U DAC (pin 113) (pin 108) (pin 106) Y Y Y N/A N/A Y Y G Y G G G Y Y G C C C N/A N/A Pb Pb B Pb B R R Pr Pr R N/A CVBS2 N/A CVBS2 N/A Pr Pr R Pr R B B Pb Pb B Y: Luma component for YUV and Y/C processing. C: Chrominance signal for Y/C processing. U: Chrominance component signal for YUV mode. YUV0 PIXOUT0 YUV1 VREF PIXOUT1 YUV2 CDAC PIXOUT2 YUV3 COMP PIXOUT3 YUV4 RSET PIXOUT4 110 109 108 107 O O O I O O O O O I O O I O YUV pixel 0 output data. CCIR656 output pixel 0. YUV pixel 1 output data. Internal voltage reference to video DAC. Bypass to ground with 0.1-µF capacitor. CCIR656 output pixel 1. YUV pixel 2 output data. Video DAC output. Refer to description and matrix for UDAC pin 106. CCIR656 output pixel 2. YUV pixel 3 output data. Compensation input. Bypass to ADVEE with 0.1-µF capacitor. CCIR656 output pixel 3. YUV pixel 4 output data. DAC current adjustment resistor input. CCIR656 output pixel 4. ESS Technology, Inc. SAM0575-021805 5 ES6218A PRODUCT BRIEF ES6218A PIN DESCRIPTION Table 1 ES6218A Pin Description (Continued) Name ADVEE ADVSS YUV5 YDAC PIXOUT5 YUV6 114 PIXOUT6 YUV7 115 PIXOUT7 PCLK2XSCN CAMIN4 PIXIN4 PCLKQSCN CAMIN5 117 PIXIN5 AUX3[2] VSYNC# CAMIN6 118 PIXIN6 AUX3[1] HSYNC# CAMIN7 119 PIXIN7 AUX3[0] HD[5:0] DCI[5:0] AUX1[5:0] HD6 DCI6 128 AUX1[6] VFD_DOUT HD7 DCI7 131 AUX1[7] VFD_DIN I/O I Aux1 data I/O. VFD data input. I/O I I/O I/O Aux1 data I/O. VFD data output. Host data bus line 7. DVD channel data I/O. 122-127 I I/O I/O I/O I/O I/O I/O CCIR656 input pixel 7. Aux3 data I/O. Host data bus lines 5:0. DVD channel data I/O. Aux1 data I/O. Host data bus line 6. DVD channel data I/O. I I/O I/O I CCIR656 input pixel 6. Aux3 data I/O. Horizontal sync. Camera YUV 7. I I/O I/O I CCIR656 input pixel 5. Aux3 data I/O. Vertical sync. Camera YUV 6. 116 O I/O I I O I CCIR656 output pixel 7. 27-MHz video output pixel clock. Camera YUV 4. CCIR656 input pixel 4. 13.5-MHz video output pixel clock. Camera YUV 5. O O CCIR656 output pixel 6. YUV pixel 7 output data. 113 Pin Numbers 111 112 I/O P G O O O O Definition Analog power for video DAC. Analog ground for video DAC. YUV pixel 5 output data. Video DAC output. Refer to description and matrix for UDAC, pin 106. CCIR656 output pixel 5. YUV pixel 6 output data. 6 SAM0575-021805 ESS Technology, Inc. ES6218A PRODUCT BRIEF ES6218A PIN DESCRIPTION Table 1 ES6218A Pin Description (Continued) Name HD8 DCI_FDS# 132 AUX2[0] VFD_CLK HD9 133 AUX2[1] HD10 134 AUX2[2] HD11 AUX2[3] IRQ HD12 AUX2[4] C2PO HD13 AUX2[5] SP HD14 140 AUX2[6] HD15 AUX2[7] IR HWRQ# DCI_REQ# AUX4[1] HRRQ# AUX4[0] 143 CAMIN2 PIXIN2 HIRQ DCI_ERR# AUX4[7] HRST# 145 AUX3[5] HIORDY 146 AUX3[3] I/O Aux3 data I/O. I/O I Aux3 data I/O. Host I/O ready. 144 I I I/O I/O I/O O Camera YUV 2. CCIR656 input pixel 2. Host interrupt request. DVD channel data error. Aux4 data I/O. Host reset. 142 141 I/O I/O I/O I O O I/O O I/O Aux2 data I/O. Host data bus line 15. Aux2 data I/O. IR remote control input. Host write request. DVD control interface request. Aux4 data I/O. Host read request. Aux4 data I/O. 137 136 135 I/O I/O I/O O I/O I/O I I/O I/O I I/O Aux2 data I/O. Host data bus line 11. Aux2 data I/O. IRQ. Host data bus line 12. Aux2 data I/O. C2PO error correction flag from CD-ROM. Host data bus line 13. Aux2 data I/O. 16550 UART serial port input. Host data bus line 14. I/O I/O Aux2 data I/O. Host data bus line 10. I/O I I/O Aux2 data I/O. VFD clock input. Host data bus line 9. Pin Numbers I/O I/O I/O Definition Host data bus line 8. DVD input sector start. ESS Technology, Inc. SAM0575-021805 7 ES6218A PRODUCT BRIEF ES6218A PIN DESCRIPTION Table 1 ES6218A Pin Description (Continued) Name HWR# DCI_CLK AUX4[5] HRD# DCI_ACK# AUX4[6] HIOCS16# CAMCLK 151 PIXIN_CLK AUX3[4] HCS1FX# 152 AUX3[7] HCS3FX# 153 AUX3[6] HA[2:0] 154, 155, 158 AUX4[4:2] AUX0 160 I2CDATA AUX1 161 I2C_CLK AUX2 162 IOW# AUX3 165 IOR# AUX4-7 LOE# LCS0# 173 PIXOUT_CLK LCS[3:1]# LD[15:0] LWRLL# LWRHL# CAMIN0 202 PIXIN0 CAMIN1 203 PIXIN1 I CCIR656 input pixel 1. I I CCIR656 input pixel 0. Camera YUV 1. 174-176 178-182, 185-191, 194-197 198 199 O O I/O O O I CCIR656 output pixel clock. RISC port chip select [3:1]. RISC port data bus. RISC port low-byte write enable. RISC port high-byte write enable. Camera YUV 0. 166-169 170 O I/O O O I/O Read strobe (LCS1). Auxiliary ports 4-7. RISC port output enable. RISC port chip select 0. O I/O I/O Write strobe (LCS1). Auxiliary port 3. I/O I/O I2C clock I/O. Auxiliary port 2. I/O I/O I2C data I/O. Auxiliary port 1 (open collector). I/O I/O Aux4 data I/Os. Auxiliary port 0 (open collector). I/O I/O Aux3 data I/O. Host address bus. I/O O Aux3 data I/O. Host select 3. I I/O O CCIR656 input pixel clock. Aux3 data I/O. Host select 1. 150 149 Pin Numbers I/O I/O I/O I/O O O I/O I I Definition Host write. DVD channel data clock. Aux4 data I/O. Host read. DVD channel data valid. Aux4 data I/O. Device 16-bit data transfer. Camera port pixel clock input. 8 SAM0575-021805 ESS Technology, Inc. ES6218A PRODUCT BRIEF SYSTEM BLOCK DIAGRAM SYSTEM BLOCK DIAGRAM A sample system block diagram for the ES6218A Vibratto-S DVD player board design is shown in Figure 2. Analog Video ROM/Flash Digital Video (CCIR656/601) TV Display Digital Devices Speakers A/V Receiver Microphone In VFD Panel IR Remote SDRAM (4/16 MB) EEPROM Audio DAC ES6218A Vibratto-S S/PDIF Audio ADC DVD Drive VFD Driver Figure 2 ES6218A Vibratto-S System Block Diagram FUNCTIONAL DESCRIPTION Figure 3 shows the internal block diagram for the ES6218A Vibratto-S DVD processor. GPIO SRAM/ROM Interface 32-Bit RISC Processor 16 K Cache OSD Display Subpicture Controller TV-Encoder TDM Interface CCIR656/601 Output Interface Gateway + DCI Interface DVD Descrambler + Transport DMA Controller Huffman Decoder Host Interface DRAM Interface CCIR656/601 Input Interface Serial Audio Interface Video Processor ROM RAM Figure 3 ES6218A Vibratto-S Block Diagram ESS Technology, Inc. SAM0575-021805 9 ES6218A PRODUCT BRIEF ORDERING INFORMATION ORDERING INFORMATION Part Number ES6218SAF Description Vibratto-S DVD, Progressive Scan, DVD-Audio, and TV encoder, with lead-free leads Package 208-pin LQFP The letters S and F at the end of the part number identify the package type LQFP and lead-free leads. No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. MPEG is the Moving Picture Experts Group of the ISO/IEC. References to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee draft ISO 11172 dated January 9, 1992. Vibratto, SmartBright, SmartLogo, SmartColor, and Music Slideshow are trademarks of ESS Technology, Inc. Dolby is a trademark of Dolby Laboratories, Inc. Trusurround, Trusurround XT, SRS, and (o) symbol are trademarks of SRS Labs., Inc. All other trademarks are trademarks of their respective companies and are used for identification purposes only. ESS Technology, Inc. 48401 Fremont Blvd. Fremont, CA 94538 Tel: (510) 492-1088 Fax: (510) 492-1898 10 http://www.esstech.com ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. U.S. patents pending. © 2005 ESS Technology, Inc. SAM0575-021805