ES6425FDF

ESS Technology, Inc. DESCRIPTION The ES6425 Digital Media Processor 2 (DMP2) is a high performance single-chip audio/video decoder for a wide series of applications such as networked or nonnetworked/flash memory media players. This second generation of Digital Media Processor has an enhanced performance engine to decode MPEG-4 video at D1 resolution with state-of-the-art progressive scan NTSC/PAL video encoder for brilliant and sharp, flickerfree output to the video display. At the heart of the ES6425 is the ESS proprietary Programmable Multimedia Processor core consisting of 32-bit RISC and 64-bit DSP processors that enable simultaneous parallel execution of system commands and specialized multimedia decoding tasks. The ES6425 includes a memory controller which interfaces to 8-bit or 16-bit DRAM with up to 128-Mb capacity. The ES6425 performs video processing to provide highresolution display of MPEG-1, MPEG-2, and MPEG-4 videos and JPEG photos. The integrated NTSC/PAL TVencoder provides composite, S-video, and YUV outputs. The ES6425 includes an On-Screen-Display (OSD) controller to provide a user friendly setup menu to enable or modify the various audio decoding and video display features. A CCIR656/601 digital video output port is also present. The ES6425 also performs audio processing for Wave, MP3, AAC, Dolby Digital, and WMA playback along with a 7-band graphic equalizer. The ES6425 has a multichannel audio serial port compliant to I 2 S format for interfacing to an external audio DAC and ADC. An S/PDIF output port is also integrated for transmitting digital audio streams. A 16-bit host interface present in the ES6425 connects to many different storage solutions including Compact Flash, Smart Media, xD-Picture Card, and IDE hard drives. Similarly, a serial interface is built-in to interface to SD  , xD  , MultiMediaCard  , and Memory Stick  devices. The ES6425 is available in an industry-standard 208-pin Plastic Quad Flat Pack (PQFP) device package. ES6425 Digital Media Processor 2 Product Brief FEATURES • Single-chip digital audio and video decoder and processor. • MPEG-4 Advanced Simple Profile* at full screen D1 video playback (playability is dependent on memory card bandwidth). • MPEG-2 video playback (playability is dependent on memory card bandwidth). • • • • • • • • • • • MPEG-1 video playback. Motion JPEG playback. JPEG photo playback. Progressive JPEG photo playback. MP3 music playback. WMA music playback (Microsoft license required). Dolby Digital decode (ES6425FDF only) AAC audio decode and playback. ESS Music Slideshow. S/PDIF digital audio output. Integrated NTSC/PAL encoder with pixel adaptive deinterlacer and five 10-bit 54 MHz video DACs. • High-quality progressive scan video output for flicker-free video display. • Simultaneous Composite, S-Video, and YUV outputs. • CCIR656/601 YUV 4:2:2 output. • On-Screen-Display controller with 3-bit blending to provide 256 colors display. • Integrated I2S serial port for up to 5.1 channel audio output and stereo input. • Direct interface for IDE devices and flash memory cards including CF, MS, MS Pro, SD, xD, MMC, and SM. • DRAM memory controller with interface to 8-bit or 16-bit SDRAM for up to 16 MB of memory. • 16-bit SRAM interface for connecting to boot EPROM or flash memory. • Lead-free leads using 98%-Sn/2%-Cu or 98%-Sn/2%-Bi. ESS Technology, Inc. SAM0529-091305 1 Note: (*) MPEG-4 Advanced Simple Profile without hardware Q-PEL and Global Motion Compensation (GMC). 2 VEE HA2/AUX4[4] VEE I2CDATA/AUX0 I2C_CLK/AUX1 IOW#/AUX2 VSS VEE IORD#/AUX3 AUX4 AUX5 AUX6 AUX7 LOE# VSS VCC LCS0#/PIXOUT_CLK LCS1# LCS2# LCS3# VSS LD0 LD1 LD2 LD3 LD4 VEE VSS LD5 LD6 LD7 LD8 LD9 LD10 LD11 VSS VEE LD12 LD13 LD14 LD15 LWRLL# LWRHL# VSS VEE CAMIN0 CAMIN1 LA0 LA1 LA2 LA3 VSS 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 ES6425 PINOUT DIAGRAM The device pinout for the ES6425 is shown in Figure 1. The pound symbol (#) denotes an active-low signal. SAM0529-091305 ES6425 Figure 1 ES6425 Device Pinout 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 VEE VSS DSCK DQM DCS0# VEE VSS DCS1# DB15 DB14 DB13 DB12 VEE VSS DB11 DB10 DB9 DB8 DB7 DB6 VSS VCC DB5 DB4 DB3 DB2 DB1 DB0 VSS VEE DMBS1 DMBS0 DRAS# DWE# DOE#/DSCK_EN DCAS# VEE VSS DMA11 DMA10 DMA9 DMA8 DMA7 DMA6 VSS VEE DMA5 DMA4 DMA3 DMA2 DMA1 DMA0 VEE LA4 LA5 LA6 LA7 LA8 LA9 VSS VCC LA10 LA11 LA12 LA13 LA14 LA15 LA16 VSS VEE LA17 LA18 LA19 LA20 LA21 RESET# TDMDX/RSEL VSS VEE TDMDR TDMCLK TDMFS TDMTSC# TWS/SEL_PLL2 TSD0/SEL_PLL0 VSS VCC TSD1/SEL_PLL1 TSD2 NC MCLK TBCK SPDIF/SEL_PLL3 NC VSS VCC RSD RWS RBCK CAMIN3 XIN XOUT AVEE AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VSS HA1/AUX4[3] HA0/AUX4[2] HCS3FX3#/AUX3[6] HCS1FX#/AUX3[7] HIOCS16#/AUX3[4] HRD#/AUX4[6] HWR#/AUX4[5] VEE VSS HIORDY/AUX3[3] HRST#/AUX3[5] HIRQ/AUX4[7] HRRQ#/AUX4[0]/CAMIN2 HWRQ#/AUX4[1] HD15/AUX2[7]/IR HD14/AUX2[6] VCC VSS HD13/AUX2[5] HD12/AUX2[4] HD11/AUX2[3] HD10/AUX2[2] HD9/AUX2[1] HD8/AUX2[0]/VFD_CLK HD7/AUX1[7]/VFD_DIN VEE VSS HD6/AUX1[6]/VFD_DOUT HD5/AUX1[5] HD4/AUX1[4] HD3/AUX1[3] HD2/AUX1[2] HD1/AUX1[1] HD0/AUX1[0] VCC VSS HSYNC#/AUX3[0]/CAMIN7 VSYNC#/AUX3[1]/CAMIN6 PCLKQSCN/AUX3[2]/CAMIN5 PCLK2XSCN/CAMIN4 YUV7/PIXOUT7 YUV6/VDAC/PIXOUT6 YUV5/YDAC/PIXOUT5 ADVSS ADVEE YUV4/RSET/PIXOUT4 YUV3/COMP/PIXOUT3 YUV2/CDAC/PIXOUT2 YUV1/VREF/PIXOUT1 YUV0/UDAC/PIXOUT0 DCLK ES6425 PRODUCT BRIEF ES6425 PINOUT DIAGRAM ESS Technology, Inc. ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION ES6425 PIN DESCRIPTION Table 1 lists the pin descriptions for the ES6425. The pound symbol (#) denotes an active-low signal. Table 1 Name ES6425 Pin Description Pin Numbers 1,18, 27, 59, 68, 75, 92, 99, 104, 130, 148, 157, 159, 164, 183, 193, 201 2-7, 10-16, 19-23, 204-207 8, 17, 26, 34, 43, 60, 67, 76, 84, 91, 98, 103, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 9, 35, 44, 83, 121, 139, 172 24 I/O Definition VEE P I/O power supply. LA[21:0] O RISC port address bus. VSS G Ground. VCC RESET# TDMDX I I O I Core power supply. Reset input (active-low); (5V tolerant input). TDM transmit data. LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ resistor; read during reset. RSEL 0 1 Selection 16-bit ROM 8-bit ROM RSEL 25 TDMDR TDMCLK TDMFS TDMTSC# TWS 28 29 30 31 I I I O O TDM receive data; (5V tolerant input). TDM clock; (5V tolerant input). TDM frame sync; (5V tolerant input). TDM output enable (active-low). Audio transmit frame sync. System and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset. SEL_PLL2 0 SEL_PLL1 0 0 1 1 0 0 1 1 SEL_PLL0 0 1 0 1 0 1 0 1 Clock Type DCLK x 4.5 DCLK x 5.0 Bypass mode DCLK x 4.0 DCLK x 4.25 DCLK x 4.75 DCLK x 5.5 DCLK x 6.0 SEL_PLL2 32 I 0 0 0 1 1 1 1 TSD0 SEL_PLL0 33 O I Audio transmit serial data output 0. Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset. ESS Technology, Inc. SAM0529-091305 3 ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION Table 1 Name TSD1 SEL_PLL1 TSD2 MCLK TBCK SPDIF SEL_PLL3 NC RSD RWS RBCK CAMIN3 XIN XOUT AVEE AVSS DMA[11:0] DCAS# DOE# DSCK_EN DWE# DRAS# DMBS0 DMBS1 DB[15:0] DCS[1:0]# DQM DSCK DCLK ES6425 Pin Description (Continued) Pin Numbers 36 37 39 40 I/O O I O I/O I/O O I — I I I I I O P G O O O O O O O O I/O O O O I Definition Audio transmit serial data output 1. Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset. Audio transmit serial data output 2. This pin must be pulled down to VSS via a 4.7-kΩ resistor for proper operation. Audio master clock for audio DAC. Audio transmit bit clock. TBCK is an input during reset and subsequently is programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4). S/PDIF output. Pull down to ground via 4.7-kΩ resistor for proper operation; read during reset. No connect. Audio receive serial data; (5V tolerant input). Audio receive frame sync; (5V tolerant input). Audio receive bit clock; (5V tolerant input). Camera and YUV input 3. 27-MHz crystal input. 27-MHz crystal output. Analog power for PLL. Analog ground for PLL. DRAM address bus. DRAM column address strobe (active-low). DRAM output enable (active-low). DRAM clock enable. DRAM write enable (active-low). DRAM row address strobe (active-low). SDRAM bank select 0. SDRAM bank select 1. DRAM data bus. SDRAM chip select (active-low). Data input/output mask. Output clock to SDRAM. Clock input to PLL; (5V tolerant input). 41 38, 42 45 46 47 48 49 50 51 52 53-58, 61-66 69 70 71 72 73 74 77-82, 85-90, 93-96 97,100 101 102 105 4 SAM0529-091305 ESS Technology, Inc. ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION Table 1 Name ES6425 Pin Description (Continued) Pin Numbers I/O O Definition Video DAC output: Value 0 1 2 3 4 5 6 7 UDAC 106 8 9 10 11 12 13 DAC V (pin 114) CVBS1 CVBS1 N/A CVBS1 CVBS1 CVBS1 N/A SYNC CHROMA CVBS1 CVBS1 SYNC N/A CVBS1 DAC Y (pin 113) Y Y Y N/A N/A Y Y G Y G G G Y Y DAC C (pin 108) N/A CVBS2 N/A CVBS2 N/A Pr Pr R Pr R B B Pb Pb DAC U (pin 106) C C C N/A N/A Pb Pb B Pb B R R Pr Pr Y: Luma component for YUV and Y/C processing. C: Chrominance signal for Y/C processing. U: Chrominance component signal for YUV mode. V: Chrominance component signal for YUV mode. YUV0 PIXOUT0 VREF YUV1 PIXOUT1 CDAC YUV2 PIXOUT2 COMP YUV3 PIXOUT3 RSET YUV4 PIXOUT4 ADVEE ADVSS YDAC YUV5 PIXOUT5 VDAC YUV6 PIXOUT6 ESS Technology, Inc. 114 113 111 112 110 109 108 107 O O I O O O O O I O O I O O P G O O O O O O YUV pixel 0 output data. CCIR656 output pixel 0. Internal voltage reference to DAC. Bypass to ground with 0.1-µF capacitor. YUV pixel 1 output data. CCIR656 output pixel 1. Chrominance signal for Y/C processing display. YUV pixel 2 output data. CCIR656 output pixel 2. Compensation input. Bypass to ADVEE with 0.1-µF capacitor. YUV pixel 3 output data. CCIR656 output pixel 3. DAC current adjustment resistor input. YUV pixel 4 output data. CCIR656 output pixel 4. Analog power. Analog ground for video DAC. Luma component for Y/C processing display. YUV pixel 5 output data. CCIR656 output pixel 5. Video DAC output. Refer to description and matrix for UDAC pin 106. YUV pixel 6 output data. CCIR656 output pixel 6. SAM0529-091305 5 ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION Table 1 Name YUV7 PIXOUT7 PCLK2XSCN CAMIN4 PCLKQSCN AUX3[2] CAMIN5 VSYNC# AUX3[1] CAMIN6 HSYNC# AUX3[0] CAMIN7 HD[5:0] AUX1[5:0] HD6 AUX1[6] VFD_DOUT HD7 AUX1[7] VFD_DIN HD8 AUX2[0] VFD_CLK HD9 AUX2[1] HD10 AUX2[2] HD11 AUX2[3] HD12 AUX2[4] HD13 AUX2[5] HD14 AUX2[6] HD15 AUX2[7] IR HWRQ# AUX4[1] 142 141 133 134 135 136 137 140 132 131 128 122-127 119 118 117 ES6425 Pin Description (Continued) Pin Numbers 115 116 I/O O O I/O I O I/O I I/O I/O I I/O I/O I I/O I/O I/O I/O O I/O I/O I I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I/O Definition YUV pixel 7 output data. CCIR656 output pixel 7. 27-MHz video pixel clock. Camera and YUV input 4. 13.5-MHz video output pixel clock. Aux3 data I/O; (5V tolerant input). Camera and YUV input 5 Vertical sync (active-low); (5V tolerant input). Aux3 data I/O; (5V tolerant input). Camera and YUV input 6. Horizontal sync (active-low); (5V tolerant input). Aux3 data I/O; (5V tolerant input). Camera and YUV input 7. Host data bus; (5V tolerant input). Aux1 data I/O; (5V tolerant input). Host data bus; (5V tolerant input). Aux1 data I/O; (5V tolerant input). VFD data output. Host data bus; (5V tolerant input). Aux1 data I/O; (5V tolerant input). VFD data input. Host data bus; (5V tolerant input). Aux2 data I/O; (5V tolerant input). VFD clock. Host data bus; (5V tolerant input). Aux2 data I/O; (5V tolerant input). Host data bus; (5V tolerant input). Aux2 data I/O; (5V tolerant input). Host data bus; (5V tolerant input). Aux2 data I/O; (5V tolerant input). Host data bus; (5V tolerant input). Aux2 data I/O; (5V tolerant input). Host data bus; (5V tolerant input). Aux2 data I/O; (5V tolerant input). Host data bus; (5V tolerant input). Aux2 data I/O; (5V tolerant input). Host data bus; (5V tolerant input). Aux2 data I/O 7; (5V tolerant input). IR remote control; (5V tolerant input). Host write request (active-low). Aux4 data I/O 1; (5V tolerant input). 6 SAM0529-091305 ESS Technology, Inc. ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION Table 1 Name HRRQ# AUX4[0] CAMIN2 HIRQ AUX4[7] HRST# AUX3[5] HIORDY AUX3[3] HWR# AUX4[5] HRD# AUX4[6] HIOCS16# AUX3[4] CAMCLK HCS1FX# AUX3[7] HCS3FX# AUX3[6] HA[2:0] AUX4[4:2] AUX0 I2CDATA AUX1 I2C_CLK IOW# AUX2 IOR# AUX3 AUX4-7 LOE# LCS0# PIXOUT_CLK LCS[3:1]# LD[15:0] LWRLL# LWRHL# CAMIN0 CAMIN1 152 153 154, 155, 158 160 161 162 165 166-169 170 173 174-176 178-182, 185-191, 194-197 198 199 202 203 151 144 145 146 149 150 143 ES6425 Pin Description (Continued) Pin Numbers I/O O I/O I O I/O O I/O I I/O O I/O O I/O I I/O I O I/O O I/O I/O I/O I/O I/O I/O I/O O I/O O I/O I/O O O O O I/O O O I I Definition Host read request (active-low). Aux4 data I/O 0; (5V tolerant input). Camera and YUV input 2. Host interrupt. Aux4 data I/O 7; (5V tolerant input). Host reset (active-low). Aux3 data I/O 5; (5V tolerant input). Host I/O ready. Aux3 data I/O 3; (5V tolerant input). Host write (active-low). Aux4 data I/O 5; (5V tolerant input). Host read (active-low). Aux4 data I/O 6; (5V tolerant input). Device 16 bit data transfer (active-low). Aux3 data I/O 4; (5V tolerant input). Camera and YUV port pixel clock. Host select 1 (active-low). Aux3 data I/O 7; (5V tolerant input). Host select 3 (active-low). Aux3 data I/O 6; (5V tolerant input). Host address bus. Aux4 data I/Os 2, 3, and 4; (5V tolerant input). Auxiliary port 0 (open collector); (5V tolerant input). I2C data I/O; (5V tolerant input). Auxiliary port 1 (open collector); (5V tolerant input). I2C clock I/O; (5V tolerant input). I/O write strobe (LCS1) (active-low). Auxiliary port 2; (5V tolerant input). I/O read strobe (LCS1) (active-low). Auxiliary port 3; (5V tolerant input). Auxiliary ports 4-7; (5V tolerant input). RISC port output enable (active-low). RISC port chip select 0 (active-low). CCIR656 output pixel clock. RISC port chip select [3:1] (active-low). RISC port data bus; (5V tolerant input). RISC port low-byte write enable (active-low). RISC port high-byte write enable (active-low). Camera and YUV input 0. Camera and YUV input 1. ESS Technology, Inc. SAM0529-091305 7 ES6425 PRODUCT BRIEF SYSTEM BLOCK DIAGRAM SYSTEM BLOCK DIAGRAM A sample system block diagram for the ES6425 board design is shown in Figure 2. Video ROM/Flash (1 MB) SDRAM (4/16 MB) ADC Audio DAC S/PDIF EEPROM Audio ES6425 DMP2 Speakers A/V Receiver IR Remote IDE HDD Memory Cards Figure 2 ES645 System Block Diagram ORDERING INFORMATION Part Number ES6425FF ES6425FDF Description Digital Media Processor 2 with lead-free leads. Digital Media Processor 2 with Dolby Digital support and lead-free leads. Package 208-pin PQFP 208-pin PQFP The letter F at the end of the part number identifies the package type PQFP. The second letter F at the end of the part number indicates lead-free leads with the device. No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. MPEG is the Moving Picture Experts Group of the ISO/IEC. References to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee draft ISO 11172 dated January 9, 1992. Vibratto, SmartBright, SmartLogo, SmartColor, and Music Slideshow are trademarks of ESS Technology, Inc. Dolby is a trademark of Dolby Laboratories, Inc. Trusurround, Trusurround XT, SRS, and (o) symbol are trademarks of SRS Labs., Inc. All other trademarks are trademarks of their respective companies and are used for identification purposes only. ESS Technology, Inc. 48401 Fremont Blvd. Fremont, CA 94538 Tel: (510) 492-1088 Fax: (510) 492-1898 8 http://www.esstech.com ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. U.S. patents pending. © 2005 ESS Technology, Inc. SAM0529-091305