ES9018K2M
32-bit Stereo Low Power Audio DAC
Datasheet
Analog Reinvented
The ES9018K2M SABRE32 Reference DAC is a high-performance 32-bit, 2-channel audio D/A converter
targeted for audiophile-grade portable power sensitive applications such as digital music players, consumer
applications such as Blu-ray players, audio pre-amplifiers and A/V receivers, as well as professional applications
such as recording systems, mixer consoles and digital audio workstations.
Using the critically acclaimed ESS patented 32-bit HyperStream™ DAC architecture, SABRE SOUND®
technology, and Time Domain Jitter Eliminator, the ES9018K2M SABRE32 Reference DAC delivers a DNR of
up to 127dB and THD+N of –120dB, a performance level that will satisfy the most demanding audio enthusiasts.
The ES9018K2M SABRE32 Reference DAC’s 32-bit HyperStream™ architecture can handle up to 32-bit,
384kHz PCM data via I2S, DSD-11.2MHz data as well as mono mode for highest performance applications.
Both synchronous and ASRC (asynchronous sample rate conversion) modes are supported.
The ES9018K2M SABRE32 Reference DAC comes in 28-QFN package and typically consumes 52mW in
normal operating mode (< 1mW in standby mode).
The ES9018K2M SABRE32 Reference DAC sets the standard for HD audio performance, in an easy-to-use
form factor for today’s most demanding digital-audio applications.
FEATURE
DESCRIPTION
Patented 32-bit HyperStream™ DAC
o +127dB DNR
o –120dB THD+N
o
Patented Time Domain Jitter Eliminator
SABRE SOUND® technology
64-bit accumulator and 32-bit processing
Integrated DSP Functions
o
o
o
o
o
o
o
Customizable output configuration
I2C control
28-QFN (5mm x 5mm) package
52mW typical operating power
< 1mW standby power
Versatile digital input
Customizable filter characteristics
o
o
o
Industry’s highest performance 32-bit mobile audio DAC with
unprecedented dynamic range and ultra-low distortion
Supports both synchronous and ASRC (asynchronous
sample rate converter) modes
Unmatched audio clarity free from input clock jitter
HD Audio Performance
Distortion free signal processing
Click-free soft mute and volume control
Programmable Zero detect
De-emphasis for 32kHz, 44.1kHz, and 48kHz sampling
Mono or stereo output in current or voltage mode based on
performance criterion
Allows software control of DAC features
Minimizes PCB footprint
Maximizes battery life
o
o
o
Supports SPDIF, PCM (I2S, LJ 16-32-bit) or DSD input
User-programmable filter allowing custom roll-off response
By-passable oversampling filter
o
APPLICATIONS
• Mobile phones / Tablets / Digital music players / Portable multimedia players
• Blu-ray / SACD / DVD-Audio player
• Audio preamplifier and A/V receiver
• Professional audio recording systems / Mixing consoles / Digital audio workstation
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
3.7
April 22, 2021
ES9018K2M Datasheet
GPIO2
GPIO1
SCL
SDA
RESETB
FUNCTIONAL BLOCK DIAGRAM
CONTROL INTERFACE
OVERSAMPLING FILTER
DATA[2:1]
DATA_CLK
XI / MCLK
XO
PCM /
DSD /
SPDIF
Interface
OSC
Fast/Slow roll-off (PCM)
50/60/70kHz (DSD)
De-emphasis (PCM)
Volume Control
Soft Mute
Zero Detect
ES9018K2M
ASRC
&
Jitter
Reduction
Dynamic
Matching
(2x)
DACL, DACR
DACLB, DACRB
DPLL
Core & IO
Power Supply
Core
Voltage
VCCA
(3.3V)
32-bit
HyperstreamTM
DAC (2x)
DVDD
DVCC
(1.8/3.3V)
GND
DAC
Power Supply
AVCC_L, AVCC_R
(3.3V)
TYPICAL APPLICATION DIAGRAM
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
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April 22, 2021
3.7
ES9018K2M Datasheet
28
27
26
25
24
23
22
RESETB
DATA_CLK
DATA1
DATA2
GPIO1
GPIO2
N.C.
PIN LAYOUT
1
2
3
4
5
6
7
ES9018K2M
28-QFN
21
20
19
18
17
16
15
DVDD
DGND
N.C.
DVCC
VCCA
AVCC_R
AVCC_L
AGND
DACR
DACRB
AGND_R
AGND_L
DACL
DACLB
8
9
10
11
12
13
14
DGND
N.C.
SCL
SDA
ADDR
XO
XI (MCLK)
3
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
3.7
April 22, 2021
ES9018K2M Datasheet
PIN DESCRIPTIONS
Reset
State
Ground
Tri-stated
Tri-stated
Tri-stated
Floating
Floating
Ground
Driven to
ground
Driven to
ground
Ground
Ground
Driven to
ground
Driven to
ground
Power
Power
Power
Power
Ground
Pin
Name
Pin Type
1
2
3
4
5
6
7
8
DGND
N.C.
SCL
SDA
ADDR
XO
XI (MCLK)
AGND
Ground
I
I/O
I
AO
AI
Ground
9
DACR
AO
10
DACRB
AO
11
12
AGND_R
AGND_L
Ground
Ground
13
DACL
AO
14
DACLB
AO
15
16
17
18
19
20
AVCC_L
AVCC_R
VCCA
DVCC
N.C.
DGND
Power
Power
Power
Power
Ground
21
DVDD
Power
(Internal /
External)
Power
22
23
24
25
N.C.
GPIO2
GPIO1
DATA2
I/O
I/O
I
Tri-stated
Tri-stated
Tri-stated
26
DATA1
I/O
Tri-stated
27
DATA_CLK
I/O
Tri-stated
28
Exposed
Pad
RESETB
I
Tri-stated
DGND
Ground
Ground
Pin Description
Digital Ground
No internal connection. Pin may be grounded if desired.
I2C Serial Clock Input
I2C Serial Data Input / Output
I2C Address Select
XTAL Output
XTAL / MCLK Input
Analog Ground
Differential Positive Analog Output Right
Differential Negative Analog Output Right
Analog Ground
Analog Ground
Differential Positive Analog Output Left
Differential Negative Analog Output Left
Analog AVCC for Left Channel
Analog AVCC for Right Channel
Analog +3.3V for OSC
Digital +1.8V to +3.3V
No internal connection. Pin may be grounded if desired.
Digital Ground. Internally connected to the Exposed Pad.
Digital Core Voltage, nominally +1.2V, is supplied by a regulator
from DVCC. DVDD must be decoupled with a minimum 2.2F
capacitor to DGND. DVDD needs to be externally supplied for
high XI / MCLK frequency. Please refer to the section about the
DVDD supply on page 7 for additional information.
No internal connection. Pin may be grounded if desired.
GPIO 2
GPIO 1
DSD Data2 I or PCM Data CH1/CH2 or SPDIF Input 2
Master mode off: Input for DSD Data1 (L) or PCM Frame Clock
or SPDIF Input 3
Master mode on: Output for PCM Frame Clock
Master mode off: Input for PCM Bit Clock OR DSD Bit Clock OR
SPDIF Input 1
Master mode on: Output for PCM Bit Clock
Master Reset / Power Down (active low)
The exposed pad must be connected to Digital Ground
Notes:
There are 3 N.C. (No Connect) pins. If desired, these pins can be connected to ground on the PCB to strengthen the
otherwise isolated pin pads. Alternatively the N.C. pins can be used to route signals to simplify PCB layout.
The exposed pad must be connected to digital ground.
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
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April 22, 2021
3.7
ES9018K2M Datasheet
FUNCTIONAL DESCRIPTION
NOTATATIONS for Sampling Rates
Mode
DSD
Serial (PCM) Normal Mode
Serial (PCM) OSF Bypass Mode
SPDIF
fs (target sample rate)
DATA_CLK / 64
Frame Clock Rate
Frame Clock Rate / 8
SPDIF Sampling Rate
FSR (raw sample rate)
DSD data rate
Frame Clock Rate
Frame Clock Rate
SPDIF Sampling Rate
PCM, SPDIF and DSD Pin Connections
PCM Audio Format
Notes:
XI clock (MCLK) must be > 192 x FSR when using PCM input (normal mode), or 128 x FSR (synchronous MCLK).
XI clock (MCLK) must be > 24 x FSR when using PCM input (OSF bypass mode).
Pin Name
DATA1
DATA2
DATA_CLK
Description
Frame clock
2-channel PCM serial data
Bit clock for PCM audio format
Master Mode (32-bit data only)
When Register #1 ‘input_select’ is set to 2’d0 (I2S) and ‘i2s_length’ is set to 2’d2 (32-bit), the DAC can become a
master for Bit Clock and Frame Clock by setting Register #9 ‘master clock enable’ to 1’b1. The Bit Clock frequency
can be configured to MCLK / 4, MCLK / 8 or MCLK / 16 by setting Register #9 ‘clock divider select’ to 2’b00, 2’b01 or
2’b10. GPIO 1 (or 2) can be configured to output MCLK by setting Register #8 gpio1_cfg (or gpio2_cfg) to 4’d3.
SLAVE PCM MODE
MASTER PCM MODE
ES901xK2M
BCLK (Bit Clock)
ES901xK2M
BCLK (Bit Clock)
LRCLK (Frame Clock)
DATA_CLK
DATA1
LRCLK (Frame Clock)
DATA_CLK
DATA1
SIN (Serial PCM Data)
DATA2
SIN (Serial PCM Data)
DATA2
MCLK (Master Clock)
GPIO1
SPDIF Audio Formant
Note: XI clock (MCLK) must be > 386 x FSR when using SPDIF input.
Up to 5 SPDIF inputs can be connected to the 5-to-1 mux, selectable via register “spdif_sel”.
Pin Name
GPIO2
GPIO1
DATA1
DATA2
DATA_CLK
Description
SPDIF input 5
SPDIF input 4
SPDIF input 3
SPDIF input 2
SPDIF input 1
DSD Audio Format
Note: XI clock (MCLK) must be > 3 x FSR when using DSD input.
Pin Name
DATA[1:2]
DATA_CLK
5
Description
2-channel DSD data input
Bit clock for DSD data input
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
3.7
April 22, 2021
ES9018K2M Datasheet
FEATURE DESCRIPTIONS
Soft Mute
When Mute is asserted the output signal will ramp to the - level. When Mute is reset the attenuation level will ramp back up
to the previous level set by the volume control register. Asserting Mute will not change the value of the volume control
register. The ramp rate is 0.0078125 x fs / 2(vol_rate-5) dB/s.
Automute
During an automute condition the ramping of the volume of each DAC to - can now be programmatically enabled or
disabled.
o In PCM serial mode, “AUTOMUTE” will become active once the audio data is continuously below the threshold set by
, for a length of time defined by 2096896 / ( x 64 x fs) Seconds.
o In SPDIF mode, “AUTOMUTE” will become active once the audio data is continuously below the threshold set by
, for a length of time defined by 2096896 / ( x 64 x fs Seconds.
o In the DSD Mode, “AUTOMUTE” will become active when any 8 consecutive values in the DSD stream have as many 1’s
and 0’s for a length of time defined by 2096896 / ( x DATA_CLK) seconds. The following
table summarizes the conditions.
Mode
PCM
SPDIF
DSD
Detection Condition
Data is continuously lower than
Data is continuously lower than
Equal number of 1s and 0s in
every 8 bits of data
Time
2096896 / ( x 64 x fs)
2096896 / ( x (64 x fs))
2096896 / ( x DATA_CLK)
Volume Control
Each output channel has its own attenuation circuit. The attenuation for each channel is controlled independently. Each
channel can be attenuated from 0dB to –127dB in 0.5dB steps.
Each 0.5dB step transition takes up to 64 intermediate levels, depending on the vol_rate register setting. The result being
that the level changes are done using small enough steps so that no switching noise occurs during the transition of the
volume control. When a new volume level is set, the attenuation circuit will ramp softly to the new level.
Master Trim
The master trim sets the 0dB reference level for the volume control of each DAC. The master trim is programmable via
registers 17-20 and is a 32bit signed number. Therefore it should never exceed’32'h7FFFFFFF (as this is full-scale signed).
All Mono Mode
An all mono mode is supported where all DACs are driven from the same source. This can be useful for high-end audio
applications. The source data for all DACs can be programmatically configured to be either CH1 or CH2.
De-emphasis
The de-emphasis feature is included for audio data that has utilized the 50/15s pre-emphasis for noise reduction. There are
three de-emphasis filters, one for 32kHz, one for 44.1kHz, and one for 48kHz.
SPDIF Data Select
An SPDIF source multiplexer allows for up to five SPDIF sources to be connected to the data pins. An internal
programmable register (spdif_sel) is used to select the appropriate data pin to decode.
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
6
April 22, 2021
3.7
ES9018K2M Datasheet
System Clock (XI / MCLK)
A system clock is required for proper operation of the digital filters and modulation circuitry. See p.30, Note 2 for the
maximum MCLK frequencies supported. The minimum system clock frequency must also satisfy:
Data Type
DSD Data
Serial OSF Bypass Mode
Minimum MCLK Frequency
MCLK > 3 x FSR , FSR = 2.8224MHz (x 1, 2 or 4)
MCLK > 192 x FSR, FSR 384kHz
or
MCLK = 128 x FSR (synchronous MCLK) with FSR 384kHz
MCLK > 24 x FSR, FSR 1.536MHz
SPDIF Data
MCLK > 386 x FSR, FSR 200kHz
Serial Normal Mode
Note
The maximum FSR
frequency is further
limited by the maximum
MCLK frequencies
supported as shown p.30,
Note 2.
Data Clock
DATA_CLOCK must be (2 x i2s_length) x FSR for SERIAL, and FSR for DSD modes. For SPDIF mode, this pin is used for
SPDIF input. This pin should be pulled low if not used.
Built-in Digital Filters
Three digital filters (fast roll-off, slow roll-off filters and minimum phase filter) are included for PCM data. See 'PCM Filter
Characteristics' for more information.
Standby Mode
For lowest power consumption the followings should be performed to enter stand-by mode:
• Set the soft_start bit in register 14 to 1'b0 to ramp the DAC outputs (DACL, DACLB, DACR, DACRB) to ground.
• RESETB pin should be brought to low digital level to:
o Shut off the DACs, Oscillator and internal regulator.
o Force digital I/O pins (DATA_CLK, DATA1, GPIO1, GPIO2, SDA ) into tri-state mode
o Reset all registers to default states
• If XI/MCLK is supplied externally, it should be stopped at logic low level
• If DVDD is supplied by an external regulator, it should be shut down during standby.
To resume from standby mode, bring RESETB to high digital level and reinitialize all registers.
DVDD Supply
The ES9018K2M is equipped with a regulated DVDD supply powered from DVCC. The internal DVDD regulator must be
decoupled to DGND with a capacitor that maintains a minimum value of 1F at 1.2V over the target operating temperature
range. The recommended capacitor for decoupling DVDD is a 2.2F ±20%, X5R 6.3V 0402, e.g. TDK part number
C1005X5R0J225M050BC or similar.
• The internal DVDD should be used except under the following conditions:
PCM (SPDIF, I2S with OSF Bypass off or on): MCLK > 50MHz or FSR > 192kHz
DSD: MCLK > 50MHz or FSR > 11.2MHz
• Internal DVDD may be used up to the maximum supported MCLK frequencies specified on p.29, Note 2. An External
DVDD (+1.3V) supply must be used above those frequencies. The external supply voltage must be greater than the
internal supply of +1.2V so the internal supply is disabled.
7
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
3.7
April 22, 2021
ES9018K2M Datasheet
Programmable FIR filter
A two stage interpolating FIR design is used. The interpolating FIR filter is generated using MATLAB, and can then be
downloaded using a custom C code.
Example Source Code for Loading a Filter
// only accept 128 or 16 coefficients
// Note: The coefficients must be quantized to 24 bits for this method!
// Note: Stage 1 consists of 128 values (0-127 being the coefficients)
// Note: Stage 2 consists of 16 values (0-13 being the coefficients, 14-15 are zeros)
// Note: Stage 2 is symmetric about coefficient 13. See the example filters for more information.
byte reg26 = (byte)(coeffs.Count == 128 ? 0 : 128);
for (int i = 0; i < coeffs.Count; i++)
{
// stage 1 contains 128 coefficients, while stage 2 contains 16 coefficients
registers.WriteRegister(26, (byte)(reg26 + i));
// write the coefficient data
registers.WriteRegister(27, (byte)(coeffs[i] & 0xff));
registers.WriteRegister(28, (byte)((coeffs[i] >> 8) & 0xff));
registers.WriteRegister(29, (byte)((coeffs[i] >> 16) & 0xff));
registers.WriteRegister(30, 0x02);
// set the write enable bit
}
// disable the write enable bit when’we're done
registers.WriteRegister(30, (byte)(setEvenBit ? 0x04 : 0x00));
OSF Bypass
The oversampling FIR filter can be bypassed, sourcing data directly into the IIR filter. ESS recommends using 8 x FSR as
the input. For example, an external signal at 44.1kHz can be oversampled externally to 8 x 44.1kHz = 352.8kHz and then
applied to the serial decoder in either I2S or LJ format. The maximum sample rate that can be applied is 1.536MHz (8 x
192kHz).
THD Compensation
THD Compensation removes the non-linearity of the DAC resistors and to a lesser degree the non-linearity of passive
components in the output stage. Taking the I-V characteristic curve of a real resistor you will notice that it as a slight
downward curvature. As more current flows, more power dissipates the resistor heats and the resistance rises.
Non-linearity of the DAC output resistors can lead to output distortion in two ways:
•
Amplitude modulation of the output current from the DAC
•
Gain modulation of the output stage as the output impedance of the DAC swings with the audio signal
The ES9018K2M includes models for its output resistors and can compensate for their characteristic curve by finely adjusting
the DAC codes for large and small signal amplitudes.
THD Compensation is effective if the base THD+N measurement with no compensation is less than approximately 70dBr. If
your system performs worse than this, check for other errors with the circuit before applying the THD Compensation.
Registers #13, and #22 to #25 are used for THD Compensation.
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
8
April 22, 2021
3.7
ES9018K2M Datasheet
Audio Interface Formats
LRCLK
RIGHT
LEFT
Several interface formats are provided so that direct connection to common audio processors is possible. The available
formats are shown in the following diagrams.
The audio interface format can be set by programming the registers.
BCLK
SIN
32-bit
LRCLK
SIN
24-bit
31
30
2
29
MSB
23
22
2
21
1
MSB
BCLK
SIN
32-bit
31
30
SIN
20bit
29
23
SIN
16bit
22
18
17
MSB
MSB
SIN
24-bit
19
15
2
1
0
2
13
2
1
0
MSB
SIN
16-bit
15
31
30
29
2
1
0
23
22
LSB
14
LRCLK
13
2
1
0
15
31
0
23
LSB
MSB
0
19
MSB
15
30
29
22
21
18
17
2
1
2
13
2
1
13
31
30
2
1
2
LEFT
1
0
2
1
14
1
0
LSB
0
LSB
23
22
LSB MSB
LEFT JUSTIFIED FORMAT
14
0
LSB MSB
14
MSB
21
LSB MSB
MSB
0
LSB MSB
LSB
1
LSB MSB
14
MSB
21
1
RIGHT
LEFT
1
LSB MSB
0
15
14
RIGHT
LSB MSB
BCLK
SIN
32-bit
31
30 29 JUSTIFIED FORMAT
LEFT
22
23
21
RIGHT
MSB
LEFT
SIN
20bit
BCLK
1
19
18
2
2
17
1
1
MSB
SIN
32-bit
31
30
29
MSB
SIN
24-bit
23
22
SIN
16-bit
15
MSB
SIN
16bit
2
1
2
1
13
31
30
29
31
30
29
15
0
23
14
2
13
1
23
MSB
22
21
0
19
LSB
MSB
2
0
1
RIGHT JUSTIFIED FORMAT
21
0
31
2
1
0
23
LSB MSB
LEFT
2
BCLK
1
0
15
14
13
2
1
LSB MSB
SIN
32-bit
31
30
18
30
2
29
1
0
15
22
RIGHT
14
0
31
30
29
22
21
LSB MSB
I2S FORMAT
23
22
2
21
0
23
LSB
MSB
1
MSB
Notes: for Left-Justified and I2S formats,
SIN the following number of BCLKs is present per (left plus right) frame:
19 18 17
0
1
2
19 18 17
• 16-bit mode: 32 BCLKs
20bit
MSB
LSB
MSB
• 24-bit mode: 48 BCLKs
SIN
15 14 13
0
1
2
15 14 13
• 32-bit mode: 64 BCLKs
16bit
MSB
LSB
MSB
2
2
2
1
0
LSB
DCLK
DCLK
D..
D0
D1
D2
D3
D4
FIGURE 4A
DSD NORMAL MODE
DCLK
DCLK
D1DSD2
DSD1,
D2
D.. D.. D0 D0 D1 D1 D2 D2 D3 D3 D4 D4
FIGURE 4B
DSD PHASE MODE
9
1
0
LSB
I2S FORMAT
D1
15
MSB
LSB MSB
MSB
SIN
24-bit
DSD1,
D2DSD2
17
LSB MSB
LSB
MSB
22
0
LSB
LSB MSB
LRCLK
14
0
LSB MSB
21
MSB
0
LSB MSB
SIN
24-bit
LRCLK
2
MSB
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
3.7
April 22, 2021
ES9018K2M Datasheet
SERIAL CONTROL INTERFACE
The registers inside the chip are programmed via an I 2C interface. The diagram below shows the timing for this interface.
The chip address can be set to 2 different settings via the “ADDR” pin. The table below summarizes this.
ADDR
0
1
CHIP ADDRESS
0x90
0x92
Notes:
1. The “ADDR” pin is used to create the CHIP ADDRESS. (0x90, 0x92)
2. The first byte after the chip address is the “ADDRESS” this is the register address.
3. The second byte after the CHIP ADDRESS is the “DATA” this is the data to be programmed into the register at the
previous “ADDRESS”.
Start
Start
Parameter
Symbol
Standard-Mode
Stop
Start
Fast-Mode
Unit
MIN
MAX
MIN
MAX
fSCL
0
100
0
400
kHz
tHD,STA
4.0
-
0.6
-
s
LOW period of SCL
tLOW
4.7
-
1.3
-
s
HIGH period of SCL
tHIGH
4.0
-
0.6
-
s
START condition setup time (repeat)
tSU,STA
4.7
-
0.6
-
s
SDA hold time from SCL falling
tHD,DAT
0.3
-
0.3
-
s
SDA setup time from SCL rising
tSU,DAT
250
-
100
-
ns
Rise time of SDA and SCL
tr
-
1000
300
ns
Fall time of SDA and SCL
tf
-
300
300
ns
STOP condition setup time
tSU,STO
4
-
0.6
-
s
Bus free time between transmissions
tBUF
4.7
-
1.3
-
s
Capacitive load for each bus line
Cb
-
400
-
400
pF
SCL Clock Frequency
START condition hold time
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
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April 22, 2021
3.7
ES9018K2M Datasheet
REGISTER MAP
Address
(Dec/Hex)
Read/Write
0 / 0x00
1 / 0x01
2 / 0x02
3 / 0x03
4 / 0x04
5 / 0x05
6 / 0x06
7 / 0x07
8 / 0x08
9 / 0x09
10 / 0x0A
11 / 0x0B
12 / 0x0C
13 / 0x0D
14 / 0x0E
15 / 0x0F
16 / 0x10
17 / 0x11
18 / 0x12
19 / 0x13
20 / 0x14
21 / 0x15
22 / 0x16
23 / 0x17
24 / 0x18
25 / 0x19
26 / 0x1A
27 / 0x1B
28 / 0x1C
29 / 0x1D
30 / 0x1E
Register
SYSTEM SETTINGS
INPUT
CONFIGURATION
RESERVED
RESERVED
AUTOMUTE _TIME
AUTOMUTE
_LEVEL
SOFT VOLUME
CONTROL 3 &
DE-EMPHASIS
GENERAL
SETTINGS
GPIO
CONFIGURATION
RESERVED
MASTER MODE
CONTROL
CHANNEL
MAPPING
DPLL/ASRC
SETTINGS
THD
COMPENSATION
SOFT START
SETTINGS
VOLUME 1
VOLUME 2
D7 (MSB)
D6
D5
D4
D2
OSC_DRV
D1
D0 (LSB)
RESERVED
I2S_LENGTH
I2S_MODE
SOFT_RESET
AUTO_INPUT_SELECT
INPUT_SELECT
RESERVED
RESERVED
AUTOMUTE_TIME
AUTOMUTE_
LOOPBACK
SPDIF_AUTO
_DEEMPH
AUTOMUTE_LEVEL
DEEMPH
_BYPASS
RESERVED
DEEMPH_SEL
FILTER_SHAPE
RESERVED
RESERVED
VOL_RATE
IIR_WR
GPIO2_CFG
MASTER_CLK
_ENABLE
CLOCK_DIVIDER_SELECT
RESERVED
SPDIF_SEL
RESERVED FOR REVISION V
SYNC_
MODE
CH2_ANALOG
_SWAP
STOP_DIV
CH1_ANALOG
_SWAP
DPLL_BW_I2S
RESERVED
BYPASS_THD
SOFT_START
SOFT_START
_ON_LOCK
MUTE
GPIO1_CFG
CH2_SEL
CH1_SEL
DPLL_BW_DSD
RESERVED
MUTE_ON
_LOCK
SOFT_START_TIME
VOLUME 1
VOLUME 2
MASTER TRIM
GPIO INPUT
SELECTION & OSF
BYPASS
2ND HARMONIC
COMPENSATION
COEFFICIENTS
3RD HARMONIC
COMPENSATION
COEFFICIENTS
PROGRAMMABLE
FILTER ADDRESS
PROGRAMMABLE
FILTER
COEFFICIENT
PROGRAMMABLE
FILTER CONTROL
D3
MASTER_TRIM
GPIO_INPUT_SEL2
GPIO_INPUT_SEL1
RESERVED
BYPASS_IIR
RESERVED
BYPASS_OSF
PROG_
COEFF_WE
PROG_
COEFF_EN
THD_COMP_C2
THD_COMP_C3
PROG_COEFF
_STAGE
PROG_COEFF_ADDR
PROG_COEFF
EVEN_STAGE2
_COEFF
RESERVED
Read Only
64 / 0x40
CHIP STATUS
65 / 0x41
66 / 0x42
67 / 0x43
68 / 0x44
69 / 0x45
70-93 /
0x46-0x5D
GPIO STATUS
11
RESERVED
REVISION
CHIP_ID
RESERVED
DPLL RATIO
DPLL_NUM
CHANNEL STATUS
SPDIF CHANNEL STATUS
AUTOMUTE
LOCK_STATUS
_STATUS
GPIO_I[1:0]
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
3.7
April 22, 2021
ES9018K2M Datasheet
REGISTER SETTINGS
Register #0: System Settings
8 bit, Read-Write Register, Default = 0x00
Bits
[7] [6] [5] [4] [3] [2] [1]
Mnemonic
osc_drv
reserved *
Default
0
Bit
Mnemonic
[7:4]
osc_drv
[3:1]
reserved *
[0]
soft_reset
0
0
0
0
0
[0]
soft_reset
0
0
Description
Oscillator drive specifies the bias current to the oscillator pad.
• 4'b0000: full bias (default)
• 4'b1000: 3/4 bias
• 4'b1100: 1/2 bias
• 4'b1110: 1/4 bias
• 4'b1111: shut down the oscillator
• Other settings: reserved
It is recommended to use the default setting.
1'b1 resets chip
1'b0 is normal operation (default)
* All Reserved Bits in Register #0 must be set to the indicated logic level to ensure correct device operation.
Register #1: Input Configuration
8 bit, Read-Write Register, Default = 0x8C
Bits
[7]
[6]
[5]
[4]
[3]
[2]
Mnemonic
i2s_length i2s_mode auto_input_select
Default
1
0
Bit
Mnemonic
[7:6]
i2s_length
[5:4]
i2s_mode
[3:2]
auto_input_select
[1:0]
input_select
0
0
1
1
[1]
[0]
input_select
0
0
Description
2'd0 = 16bit
2'd1 = 24bit
2'd2 or 2'd3 = 32bit (default)
2’d0 = I2S (default)
2’d1 = LJ mode
2’d2 = I2S
2’d3 = LJ mode
2'd0 = input select
2'd1 = I2S or DSD
2'd2 = I2S or SPDIF
2'd3 = I2S, SPDIF or DSD (default)
2'd0 = I2S (default)
2'd1 = SPDIF
2'd2 = reserved
2'd3 = DSD
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12
April 22, 2021
3.7
ES9018K2M Datasheet
Register #2: Reserved
8 bit, Read-Write Register, Default = 0x18
Bits
[7] [6] [5] [4] [3] [2]
Reserved
Mnemonic
Default
0
0
0
1
1
0
[1]
[0]
0
0
[1]
[0]
0
0
Register #3: Reserved
8 bit, Read-Write Register, Default = 0x10
Bits
[7] [6] [5] [4] [3] [2]
Reserved
Mnemonic
Default
0
0
0
1
0
0
Register #4: Soft Volume Control 1 (Automute Time)
8 bit, Read-Write Register, Default = 0x00
Bits
[7] [6] [5] [4] [3] [2]
automute_time
Mnemonic
Default
0
0
0
0
0
0
Bit
Mnemonic
[7:0]
automute_time
[1]
[0]
0
0
Description
Default o’ 8'd0 (Automute Disabled)
Time in Seconds = 2096896 / (automute_time x DATA_CLK) with DATA_CLK in Hz
Register #5: Soft Volume Control 2 (Automute Level)
8 bit, Read-Write Register, Default = 0x68
Bits
[7]
[6] [5]
Mnemonic
Default
automute_loopback
0
Bit
Mnemonic
[7]
automute_loopback
[6:0]
automute_level
13
[4]
[3]
[2]
[1]
[0]
0
0
automute_level
1
1
0
1
0
Description
1'b0 disables automute_loopback (default)
1'b1 ramps to -infinity on automute
The level (in 1dB increments) of the automute, default of 7'd104
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
3.7
April 22, 2021
ES9018K2M Datasheet
Register #6: Soft Volume Control 3 and De-emphasis
8 bit, Read-Write Register, Default = 0x4A
Bits
[7]
[6]
Mnemonic
spdif_auto_deemph
deemph_bypass
Default
0
1
Bit
Mnemonic
[7]
spdif_auto_deemph
[6]
deemph_bypass
[5:4]
deemph_sel
[3]
reserved
[2:0]
vol_rate
[5]
[4]
deemph_sel
0
0
[3]
reserved *
1
[2] [1] [0]
vol_rate
0
1
0
Description
1'b0 disables automatic de-emphasis select in SPDIF mode (default)
1'b1 enables automatic de-emphasis select in SPDIF mode
1'b0 enables de-emphasis filters
1'b1 disabled de-emphasis filters (default)
2’b00 = 32kHz (default)
2’b01 = 44.1kHz
2’b10 = 48kHz
2’b11 = RESERVED
Must be left as 1'b1 for normal operation
3'd2 by default
Sets the volume ramp rate to 0.0078125 x fs / 2(vol_rate-5) dB/s
* All Reserved Bits in Register #6 must be set to the indicated logic level to ensure correct device operation.
Register #7: General Settings
8 bit, Read-Write Register, Default = 0x80
Bits
[7]
[6]
[5]
Mnemonic
Default
Bit
[7]
reserved *
1
Mnemonic
reserved *
[6:5]
filter_shape
[4]
reserved *
[3:2]
iir_bw
[1:0]
mute
filter_shape
0
0
[4]
reserved *
0
[3]
[2]
iir_bw
0
0
[1]
[0]
mute
0
0
Description
2’d0 = fast rolloff (default)
2’d1 = slow rolloff
2’d2 = minimum phase
2'd3 = reserved
2’d0 = 1.0757 x fs or 47.44kHz (fs = 44.1kHz) – Normal mode (default)
2’d1 = 1.1338 x fs or 50kHz (fs = 44.1kHz)
2’d2 = 1.3605 x fs or 60kHz (fs = 44.1kHz)
2’d3 = 1.5873 x fs or 70kHz (fs = 44.1kHz)
This is a soft mute, which uses the ramping volume control.
mute[0]
• 1’b0: Channel 1 (default of left channel) unmuted (default)
• 1’b1: Channel 1 (default of left channel) muted
mute[1]
• 1’b0: Channel 2 (default of right channel) unmuted (default)
• 1’b1: Channel 2 (default of right channel) muted
* All Reserved Bits in Register #7 must be set to the indicated logic level to ensure correct device operation.
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14
April 22, 2021
3.7
ES9018K2M Datasheet
Register #8: GPIO Configuration
8 bit, Read-Write Register, Default = 0x10
Bits
[7] [6] [5] [4] [3] [2] [1] [0]
Mnemonic
gpio2_cfg
gpio1_cfg
Default
0
0
0
1
0
0
0
0
Bit
Mnemonic
[7:4]
gpio2_cfg
[3:0]
gpio1_cfg
Description
Set GPIO 2 configuration.
Default to 4’d1 (DPLL Lock Status).
See GPIO Configuration Table below for meaning of all settings.
Set GPIO 1 configuration
Default to 4’d0 (Automute Status).
See GPIO Configuration Table below for meaning of all settings.
GPIO Configuration Table
Setting
Direction
4’d0
Output
4’d1
Output
4’d2
Output
4’d3
Output
4’d4
Output
4’d5
Output
4’d6
Output
4’d7
4’d8
4’d9
4’d15
Output
Input
Input
Output
GPIO Function
Automute status (active high)
– asserted when Automute condition is met
DPLL Lock status (active high)
– asserted when DPLL is in lock
Minimum Volume (active high)
- asserted when volume of both the left & right channels has ramped to its minimum
value (–127.5dB)
MCLK
DPLL Lock interrupt (active high)
- asserted when DPLL Lock status changes state
- reading register 64 clears the interrupt
Automute Interrupt (active high)
- asserted when Automute status changes state
- reading register 64 clears the interrupt
DPLL Lock or Automute interrupt (active high)
- asserted when DPLL Lock or Automute status changes state
- reading register 64 clears the interrupt
Output low
Used as input pin – pin status can be read from register 65.
Input Selection – uses the GPIO as an input select based on register 21
Output high
Register #9: Reserved
8 bit, Read-Write Register, Default = 0x22
Bits
[7] [6] [5] [4] [3] [2] [1]
Mnemonic
Reserved for Revision V
Default
0
0
0
0
0
0
0
15
[0]
0
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
3.7
April 22, 2021
ES9018K2M Datasheet
Register #10: Master Mode Control
8 bit, Read-Write Register, Default = 0x5
Bits
[7]
[6]
[5]
Mnemonic
master_clock_enable clock_divider_select
Default
0
0
0
Bit
Mnemonic
[7]
master_clock_enable
[6:5]
clock_divider_select
[4]
sync_mode
[3:0]
stop_div
[4]
sync_mode
0
[3]
0
[2] [1] [0]
stop_div
1
0
1
Description
1’b0 disables master mode (default)
1’b1 enables master mode (driving Bit clock and Frame Clock)
2’b00: Bit Clock frequency = MCLK / 4 (default)
2’b01: Bit Clock frequency = MCLK / 8
2b10: Bit Clock frequency = MCLK / 16
2’b11: Bit Clock frequency = MCLK / 16
Frame Clock frequency = Bit Clock frequency / 64
1’b0 for normal operation of the DPLL and ASRC.
1’b1 to enable quick lock if the fs and MCLK are synchronous and MCLK is 128 x FSR
Note: quick lock can only be used in PCM normal mode.
Sets the number of FSR edges that must occur before the DPLL and
ASRC can lock on to the incoming signal.
4’d0 = 16384 FSR edges
4’d1 = 8192 FSR edges
4’d2 = 5461 FSR edges
4’d3 = 4096 FSR edges
4’d4 = 3276 FSR edges
4’d5 = 2730 FSR edges (default)
4’d6 = 2340 FSR edges
4’d7 = 2048 FSR edges
4’d8 = 1820 FSR edges
4’d9 = 1638 FSR edges
4’d10 = 1489 FSR edges
4’d11 = 1365 FSR edges
4’d12 = 1260 FSR edges
4’d13 = 1170 FSR edges
4’d14 = 1092 FSR edges
4’d15 = 1024 FSR edges
For correct operation, master mode should only be enabled when the DAC’s input mode is set to I 2S, and when i2s_length is
set to 32-bit and i2s_mode is set to I2S in register 1.
When master mode is enabled, the DATA_CLK pin will output Bit Clock and the DATA1 pin will output Frame Clock at
frequencies specified by clock divider select.
For compatibility with Rev. W, or when PCM data with FSR > 96kHz is used, stop_div should be set to 4’d0 (16384 FSR
edges).
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
16
April 22, 2021
3.7
ES9018K2M Datasheet
Register #11: Channel Mapping
8 bit, Read-Write Register, Default = 0x02
Bits
[7]
[6] [5] [4]
Mnemonic
reserved *
spdif_sel
Default
0
0
0
0
Bit
Mnemonic
[7]
reserved *
[6:4]
spdif_sel
[3]
ch2_analog_swap
[2]
ch1_analog_swap
[1]
ch2_sel
[0]
ch1_sel
[3]
ch2_analog_swap
0
[2]
ch1_analog_swap
0
[1]
ch2_sel
1
[0]
ch1_sel
0
Description
select the spdif data source
3’d0 = DATA_CLK (default)
3’d1 = DATA2
3’d2 = DATA1
3’d3 = GPIO1
3’d4 = GPIO2
3’d5-7: reserved
1’b0 = normal operation (default)
1’b1 = swap dac and dacb
1’b0 = normal operation (default)
1’b1 = swap dac and dacb
1’b0 = left
1’b1 = right (default)
1’b0 = left (default)
1’b1 = right
* All Reserved Bits in Register #11 must be set to the indicated logic level to ensure correct device operation.
Left and Right channels can be reversed using Register #11.
17
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
3.7
April 22, 2021
ES9018K2M Datasheet
Register #12: DPLL/ASRC Settings
8 bit, Read-Write Register, Default = 0x5A
Bits
[7] [6] [5] [4] [3] [2] [1] [0]
Mnemonic
dpll_bw_i2s
dpll_bw_dsd
Default
0
1
0
1
1
0
1
0
Bit
Mnemonic
[7:4]
dpll_bw_i2s
Description
DPLL bandwidth setting for I2S and SPDIF modes (16 settings)
4’b0000 : OFF
4’b0001 : Lowest Bandwidth
4’b0101 : (default)
4’b1010 :
4’b1111 : Highest Bandwidth
DPLL bandwidth setting for DSD mode (16 settings)
4’b0000 : OFF
4’b0001 : Lowest Bandwidth
[3:0]
dpll_bw_dsd
4’b0101 :
4’b1010 : (default)
4’b1111 : Highest Bandwidth
Register #13: THD Compensation
8 bit, Read-Write Register, Default = 0x40
Bits
[7]
[6]
Mnemonic
reserved *
bypass_thd
Default
0
1
Bit
Mnemonic
[7]
reserved *
[6]
bypass_thd
[5:0]
reserved *
[5]
0
[4]
[3] [2] [1]
reserved *
0
0
0
0
[0]
0
Description
1’b0: enable THD compensation
• output = input + (input2) x thd_comp_c2 + (input3) x thd_comp_c3
• thd_comp_c2 is stored in registers 23-22 (16 bits signed) (register 23 stores MSBs)
thd_comp_c3 is stored in registers 25-24 (16 bits signed) (register 25 stores MSBs)
1’b1: disable THD compensation (default)
• PCM mode: output = input; DSD mode: output = input / 2
* All Reserved Bits in Register #13 must be set to the indicated logic level to ensure correct device operation.
THD compensation can be used to reduce the 2nd and 3rd harmonic distortion introduced by external output drivers.
A system level tuning is required to arrive at the optimum coefficients for thd_comp_c2 and thd_comp_c3.
Notes:
• To get the same gain (output = input) for PCM and DSD modes without THD compensation, bypass_thd should be set to
1’b0 with thd_comp_c2 and thd_comp_c3 set to 16’d0 (default)
• Erroneous compensation can lead to higher distortion than the one without compensation. If accurate tuning cannot be
performed, thd_comp_c2 and thd_comp_c3 should be set to 16’d0 (default) if bypass_thd is set to 1’b0.
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
18
April 22, 2021
3.7
ES9018K2M Datasheet
Register #14: Soft Start Settings
8 bit, Read-Write Register, Default = 0x8A
Bits
[7]
[6]
Mnemonic
soft_start
soft_start_on_lock
Default
1
0
Bit
Mnemonic
[7]
soft_start
[6]
soft_start_on_lock
[5]
mute_on_lock
[4:0]
soft_start_time
[5]
mute_on_lock
0
[4]
[3] [2] [1] [0]
soft_start_time
0
1
0
1
0
Description
1’b0: Ramp the output stream to ground
1’b1: Normal operation (default) – ramp the output stream to ½ x AVCC_L/R
1’b0: Do not force output low when lock is lost (default)
1’b1: Force output low when lock is lost
1’b0: Do not force a mute when lock is lost (default)
1’b1: Force a mute when lock is lost
Time for soft start ramp
= 4096 x 2(soft_start_time+1) / MCLK seconds (where MCLK is measured in Hz).
The valid range of soft-start_time is from 0 to 20.
Register #15: Volume 1 (usually selected for the Left Channel, but can be reversed using Register #11)
8 bit, Read-Write Register, Default = 0x00
Bits
[7] [6] [5] [4] [3] [2]
Mnemonic
volume1
Default
0
0
0
0
0
0
Bit
Mnemonic
[7:0]
volume1
[1]
[0]
0
0
Description
Default to 8’d0
0dB to –127.5dB in 0.5dB steps
Register #16: Volume 2 (usually selected for the Right Channel, but can be reversed using Register #11)
8 bit, Read-Write Register, Default = 0x00
Bits
[7] [6] [5] [4] [3] [2] [1]
Mnemonic
volume2
Default
0
0
0
0
0
0
0
Bit
Mnemonic
[7:0]
volume2
[0]
0
Description
Default to 8’d0
0dB to –127.5dB in 0.5dB steps
Register #20-17: Master Trim
32 bit, Read-Write Register, Default = 32’h7ffffff. Reg 20 are the MSB’s, Reg 17 are the LSBs.
Bits
[31:0]
Mnemonic
master_trim
Default
32’h7fffffff
This is a 32 bit value that sets the 0dB level for all volume controls. This is a signed number, so it should never exceed
32’h7fffffff (which is 231 – 1).
19
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3.7
April 22, 2021
ES9018K2M Datasheet
Register #21: GPIO Input Selection and OSF Bypass
8 bit, Read-Write Register, Default = 0x00
Bits
[7:6]
[5:4]
Mnemonic
gpio_input_sel2
gpio_input_sel1
Default
0
0
0
0
Bit
Mnemonic
[7:6]
gpio_input_sel2
[5:4]
gpio_input_sel1
[3]
reserved *
[2]
bypass_iir
[1]
reserved *
[3]
reserved *
0
[2]
bypass_iir
0
[1]
reserved *
0
[0]
bypass_osf
0
Description
Selects which input will be selected when GPIOX = 1’b1
2’d0 = I2S data (default)
2’d1 = SPDIF data
2’d2 = reserved
2’d3 = DSD data
Selects which input will be selected when GPIOX = 1’b0
2’d0 = I2S data (default)
2’d1 = SPDIF data
2’d2 = reserved
2’d3 = DSD data
1’b0 = Use the IIR filter (default)
1’b1 = Bypass the IIR filter.
1’b0 = Use the interpolating 8x FIR filter (default)
1’b1 = Bypass the interpolating 8x FIR filter.
[0]
bypass_osf
Note: Bypassing the interpolating filter requires that the input data be
oversampled at 8x fs by an external oversampling filter.
* All Reserved Bits in Register #21 must be set to the indicated logic level to ensure correct device operation.
Notes: Any of the GPIO can be configured to be used as an input select. This allows an external MCU or controller to set
the input type by setting the GPIO to either logic high (1’b1) or logic low (1’b0). To set this feature, the first step is to enable
one of the GPIO as an input select by setting gpio_cfg to 4’d9. Once a GPIO is configured as an input select it has the ability
to select between two different inputs. The first input (logic low) is set via register 21[5:4]. The second input (logic high) is
set via register 21[7:6]. Only one GPIO should be configured as an input select, and the ES9018K2M will only use the first
GPIO if multiple GPIOs are configured as an input selection.
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
20
April 22, 2021
3.7
ES9018K2M Datasheet
Register #23-22: 2nd Harmonic Compensation Coefficients
16 bit, Read-Write Register, Default = 0x0000 (no compensation). Register #23 is MSB. See Register #13 for more details.
Bits
[15:0]
Mnemonic
Thd_comp_c2
Default
16’d0
Register #25-24: 3rd Harmonic Compensation Coefficients
16 bit, Read-Write Register, Default = 0x0000 (no compensation). Register #25 is MSB. See Register #13 for more details.
Bits
[15:0]
Mnemonic
Thd_comp_c3
Default
16’d0
The THD Compensation registers are signed integer values split into two memory locations each.
THD Compensation Coefficient
MSB
LSB
x^3 (third harmonic)
Register 25
Register 24
x^2 (second harmonic)
Register 23
Register 22
Table 1: THD Compensation Registers
1. Configure the output stage gain for the maximum desired output level. If any component values are later changed on
the output audio signal path you will need to re-tune the THD Compensation to achieve peak performance.
2. Set the input level, ES9018K2M Volume and Master Trim for the maximum desired output level.
If the output level is later increased beyond this level you will need to re-tune the THD Compensation to achieve
peak performance.
3. Adjust registers 0x23 and 0x25 to achieve peak THD performance. Use the I2C interface or the ES9018K2M GUI to make
the adjustments while watching the THD+N measurement.
In the GUI, adjust the THD Compensation sliders as shown in figure 1. The sliders are linked to the MSB of the THD
Compensation registers so they are somewhat coarse.
Both channels are tuned simultaneously; keep an eye on both measurements.
Typical register values are very close to zero.
4. For finer adjustments use registers 0x22 and 0x24. Use the I2C interface or the ES9018K2M GUI to make large changes
of 50 or so while watching the THD+N measurement. Switch to smaller increments when you're close to peak
performance.
In the GUI, open the register listing (see figure 2) and click Update Registers to make sure the most up-to-date values are
displayed. There are no sliders for the fine-adjust registers (see figure 3).
The ES9018K2M GUI is available for download from the ESS website at:
64-Bit: http://www.esstech.com/software/Sabre2M_signed_x64.zip
32-Bit: http://www.esstech.com/software/Sabre2M_signed_x86.zip
21
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ES9018K2M Datasheet
Figure 1. THD Compensation
Figure 2. Opening the register listing
Figure 3. THD Compensation Registers in
the register listing
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April 22, 2021
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ES9018K2M Datasheet
Register #26: Programmable Filter Address
8 bit, Read-Write Register, Default = 0x00
Bits
[7]
[6:0]
Mnemonic
prog_coeff_stage
prog_coeff_addr
Default
0
0 0 0 0 0 0
Bit
Mnemonic
[7]
prog_coeff_stage
[6:0]
prog_coeff_addr
0
Description
Selects which stage of the filter to write.
1’b0 = Stage 1 of the oversampling filter (128 coefficients).
1’b1 = Stage 2 of the oversampling filter (16 coefficients)
Selects the coefficient address when writing custom coefficients
for the oversampling filter.
Register #29-27: Programmable Filter Coefficient
8 bit, Read-Write Register, Default = 0x000000
Bits
[23:0]
Mnemonic
Default
Bit
[23:0]
prog_coeff
24’d0
Mnemonic
prog_coeff
Description
A 24-bit filter coefficient that will be written to address ‘prog_coeff_addr’.
Register #30: Programmable Filter Control
8 bit, Read-Write Register, Default = 0x00
Bits
[7:3]
[2]
Mnemonic
reserved *
even_stage2_coeff
Default
0 0 0 0 0
0
Bit
[7:3]
Mnemonic
reserved *
[2]
even_stage2_coeff
[1]
prog_coeff_we
[0]
prog_coeff_en
[1]
prog_coeff_we
0
[0]
prog_coeff_en
0
Description
Sets the type of symmetry of the stage 2 programmable filter.
1’b0 = Uses a sine symmetric filter (27 coefficients).
1’b1 = Uses a cosine symmetric filter (28 coefficients).
1’b0 = Disable writing to the custom filter coefficients.
1’b1 = Enable writing to the custom filter coefficients.
Note: When set to 1’b1 the custom filter will be bypassed
regardless of the state of register 21[0].
1’b0 = Use one of the built-in oversampling filters.
1’b1 = Use the custom oversampling filter.
Note: The custom filter is not programmed to anything on reset,
valid coefficients must be written to the filter before enabling.
* All Reserved Bits in Register #30 must be set to the indicated logic level to ensure correct device operation.
Notes: even_stage2_coeff sets the type of symmetry used by the second stage filter. The actual RAM is 16 coefficients, but
only the first 14 coefficients are used when applying the oversampling filter. The first 14 coefficients are mirrored using either
sine or cosine symmetry, resulting in a filter length of either 27 or 28 taps. This means that the second stage RAM should
only contain half of the impulse response of the second stage filter, and the impulse peak value will be contained in the 14 th
coefficient. Also note that, due to the symmetry of the filter, only linear phase filters may be used in the second stage.
23
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ES9018K2M Datasheet
Register #64: Chip Status
8 bit, Read-Only Register
Bits
[7] [6]
[5]
Mnemonic
reserved revision
Bit
[7:6]
Mnemonic
reserved
[5]
revision
[4:2]
chip_id
[1]
automute_status
[0]
lock_status
[4]
[3] [2]
chip_id
[1]
automute_status
[0]
lock_status
Description
1’b0 => revision W.
1’b1 => revision V.
3’d4 => ES9018K2M
1’b0 => Automute condition is inactive.
1’b1 => Automute condition is active.
1’b0 => The Jitter Eliminator is not locked to an incoming signal.
1’b1 => The Jitter Eliminator is locked to an incoming signal.
Register #65: GPIO Status
8 bit, Read-Only Register
Bits
Mnemonic
Bit
[7:2]
[1]
[0]
[7]
[6]
Mnemonic
reserved
gpio_I[1]
gpio_I[0]
[5] [4] [3]
reserved
[2]
[1]
[0]
gpio_I[1:0]
Description
Status of pin GPIO2
Status of pin GPIO1
Register #69-66: DPLL Ratio
32 bit, Read-Only Register. Register 69 contains the MSBs, Register 66 contains the LSBs.
Bits
[31:0]
Mnemonic
dpll_num
This is a read-only 32-bit value that can be used to calculate the sample rate. The raw sample rate (FSR) can be calculated
using: FSR = (DPLL_NUM x FMCLK) / 232.
Note that the DPLL number (register 66-69) should be read from LSB to MSB as it is latched on the LSBs (register 66).
Register #93-70: Channel Status
Register 93 contains the MSBs, Register 70 contains the LSBs. Format is [191:0]
These registers allow read back of the SPDIF channel status. The status definition is different for the consumer configuration
and professional configuration. Please refer to the following two tables for details.
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April 22, 2021
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ES9018K2M Datasheet
SPDIF CHANNEL STATUS – Consumer configuration
Address
Offset
0
1
[6]
Reserved
Reserved
[5]
0: 2-Channel
1: 4-Channel
[4]
Reserved
Category Code
0x00: General
0x01: Laser-Optical
0x02: D/D Converter
0x03: Magnetic
0x04: Digital Broadcast
0x05: Musical Instrument
0x06: Present A/D Converter
0x08: Solid State Memory
0x16: Future A/D Converter
0x19: DVD
0x40: Experimental
Channel Number
0x0: Don’t Care
0x1: A (Left)
0x2: B (Right)
0x3: C
0x4: D
0x5: E
0x6: F
0x7: G
0x8: H
0x9: I
0xA: J
0xB: K
0xC: L
0xD: M
0xE: N
0xF: O
Reserved Reserved Clock Accuracy
0x0:Level 2 1000ppm
0x1:Level 1 50ppm
0x2:Level 3 variable pitch shifted
2
3
25
[7]
4
Reserved
5-23
Reserved
Reserved
Reserved
Reserved
[3]
[2]
[1]
[0]
0: No-Preemph
1: Pre-emphasis
0: Copyright
1: Non-Copyright
0: Audio
1: Data
0: Consumer
1: Professional
Source Number
0x0:Don’t Care
0x1: 1
0x2: 2
0x3: 3
0x4: 4
0x5: 5
0x6: 6
0x7: G
0x8: 8
0x9: 9
0xA: 10
0xB: 11
0xC: 12
0xD: 13
0xE: 14
0xF: 15
Sample Frequency
0x0: 44.1k
0x2: 48k
0x3: 32k
0x4: 22.05k
0x6: 24k
0x8: 88.2k
0xA: 96k
0xC: 176.4k
0xE: 192k
Word Length:
If Word Field Size=0 |If Word Field Size = 1
000=Not indicated |000=Not indicated
100 = 23bits
|100 = 19bits
010 = 22bits
|010 = 18bits
110 = 21bits
|110 = 17bits
001 = 20bits
|001 = 16bits
101 = 24bits
|101 = 20bits
Word Field Size
0:Max 20bits
1:Max 24bits
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
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ES9018K2M Datasheet
SPDIF CHANNEL STATUS – Professional configuration
Address
Offset
0
[7]
[6]
sampling frequency:
00: not indicated (or see byte 4)
10: 48 kHz
01: 44.1 kHz
11: 32 kHz
[5]
lock:
0: locked
1: unlocked
[4]
[3]
[2]
emphasis:
000: Emphasis not indicated
001: No emphasis
011: CD-type emphasis
111: J-17 emphasis
[1]
0: Audio
1: Non-audio
[0]
0: Consumer
1: Professional
1
User bit management:
0000: no indication
1000: 192-bit block as channel status
0100: As defined in AES18
1100: user-defined
0010: As in IEC60958-3 (consumer)
2
alignment level:
00: not indicated
10: –20dB FS
01: –18.06dB FS
3
Channel identification:
if bit 7 = 0 then channel number is 1 plus the numeric value of bits 0-6 (bit reversed).
if bit 7 = 1 then bits 4–6 define a multichannel mode and bits 0–3 (bit reversed) give the channel number within that mode.
fs scaling:
Sample frequency (fs):
Reserved
DARS (Digital audio reference signal):
0: no scaling
0000: not indicated
00: not a DARS
1: apply factor of
0001: 24kHz
01: DARS grade 2 (10ppm)
1 / 1.001 to value
0010: 96kHz
10: DARS grade 1 (1ppm)
1001: 22.05kHz
11: Reserved
1010: 88.2kHz
1011: 176.4kHz
0011: 192kHz
1111: User defined
Reserved
4
5
6-9
Channel mode:
0000: not indicated (default to 2 channel)
1000: 2 channel
0100: 1 channel (monophonic)
1100: primary / secondary
0010: stereo
1010: reserved for user applications
0110: reserved for user applications
1110: SCDSR (see byte 3 for ID)
0001: SCDSR (stereo left)
1001: SCDSR (stereo right)
1111: Multichannel (see byte 3 for ID)
Source Word Length:
Use of aux sample word:
If max = 20bits
|If max = 24bits
000: not defined, audio max 20 bits
000=Not indicated |000=Not indicated 100: used for main audio, max 24 bits
100 = 23bits
|100 = 19bits
010: used for coord, audio max 20 bits
010 = 22bits
|010 = 18bits
110: reserved
110 = 21bits
|110 = 17bits
001 = 20bits
|001 = 16bits
101 = 24bits
|101 = 20bits
alphanumerical channel origin: four-character label using 7-bit ASCII with no parity. Bits 55, 63, 71, 79 = 0.
10-13
alphanumerical channel destination: four-character label using 7-bit ASCII with no parity. Bits 87, 95, 103, 111 = 0.
14-17
local sample address code: 32-bit binary number representing the sample count of the first sample of the channel status block.
18-21
time of day code: 32-bit binary number representing time of source encoding in samples since midnight
22
23
reliability flags
0: data in byte range is reliable
1: data in byte range is unreliable
CRCC
00000000: not implemented
X: error check code for bits 0–183
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April 22, 2021
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ES9018K2M Datasheet
APPLICATION DIAGRAM
RECOMMENDED POWER-UP SEQUENCE
~
~
VCCA
External DVDD (if required)
Same time as DVCC or later
RESETB
27
~
~
XI / MCLK (if externally supplied)
~
~
Same time as VCCA or later
~
~
AVCC_L, AVCC_R
DVCC
At power up, assert RESETB until at least
1ms after all external power supplies (and
XI/MCLK if supplied externally) are stabilized
Subsequent reset
should be asserted
for 10ns or longer
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
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ES9018K2M Datasheet
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Positive Supply Voltage (DVCC, VCCA, AVCC_L, AVCC_R)
Positive Supply Voltage (DVDD)
DAC Output voltage Range (DACL, DACR, DACLB, DACRB)
Storage temperature Range
RATING
+4.7V with respect to GND
+1.8V with respect to GND
GND < Vout < AVCC
Operating Junction Temperature
Voltage Range for Digital Input pins
ESD Protection
Human Body Model (HBM)
Machine Model (MM)
+125C
–0.3V to DVCC+ 0.3V
–65C to +150C
2000V
200V
WARNING: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure
to absolute–maximum–rated conditions for extended periods may affect device reliability.
WARNING: Electrostatic Discharge (ESD) can damage this device. Proper procedures must be followed to avoid ESD when handling this device.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Operating temperature
SYMBOL
TA
Power Supply
DVCC
Internal Digital Core supply
External Digital Core Supply
Analog Core Supply Voltage
DVDD
DVDD
VCCA
AVCC_L
AVCC_R
Total Power
–20C to +70C
Current nominal
(Note 1)
13.0mA
14.2mA
Current standby
(Notes 1, 2)
0mA
0mA
+1.3V 5% (Note 4)
+3.3V 5%
50mA
0.8mA
0mA
+3.3V 5%
8.0mA
0mA
DVCC = +1.8V
DVCC = +3.3V
52mW
76mW
< 1mW
< 1mW
Voltage
Digital Power Supply Voltage
Analog Power Supply Voltage
CONDITIONS
+1.8V 5%
+3.3V 5%
+1.2V (typical) (Note 3)
Notes:
(1) fs = 44.1kHz, external MCLK = 22MHz, I2S input, DAC output connected to current-to-voltage converter, internal DVDD, all external
supply voltages at nominal center values
(2) With RESETB held low after setting the soft_start bit in register 14 to 1’b0 to fully ramp the DAC outputs to ground
(3) Internal DVDD should be used except under the conditions described on page 7.
(4) External DVDD current measured at 192kHz sample rate and MCLK = 80MHz.
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April 22, 2021
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ES9018K2M Datasheet
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
VOL
Low-level output voltage
Minimum
Maximum
DVCC/2 + 0.4
0.4
DVCC – 0.2
0.2
Input capacitance
5
CO
Input/output capacitance
5
29
CLK capacitance
Comments
V
CIN
CCLK
Unit
10
V
V
IOH = 100A
V
IOL = 100A
pF
fc = 1MHz
pF
fc = 1MHz
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
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ES9018K2M Datasheet
XI / MCLK Timing
tMCH
MCLK
tMCL
tMCY
Parameter
MCLK pulse width high
MCLK pulse width low
MCLK cycle time
Symbol
TMCH
TMCL
TMCY
MCLK duty cycle
Min
4.5
4.5
10
Max
45:55
55:45
Unit
ns
ns
ns
Audio Interface Timing
tDCY
DATA_CLK
DATA_CLK
tDCH
tDH
DATA[8:1]
DATA[2:1]
Valid
tDCL
tDS
Invalid
Valid
L
Parameter
DATA_CLK pulse width high
DATA_CLK pulse width low
DATA_CLK cycle time
DATA_CLK duty cycle
DATA set-up time to DATA_CLK rising edge
DATA hold time to DATA_CLK rising edge
Symbol
Min
tDCH
tDCL
tDCY
4.5
4.5
10
45:55
4.1
2
tDS
tDH
Max
Unit
ns
ns
ns
55:45
ns
ns
Notes:
• Audio data on DATA[2:1] are sampled at the rising edges of DATA_CLK and must satisfy the setup and hold time
requirements relative to the rising edge of DATA_CLK
• For DSD Phase mode, the normal data (D0, D1, D2... on p.10) must satisfy the setup and hold time requirements relative
to the rising edge of DATA_CLK. The complimentary data (D0, D1, etc.) will be ignored.
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April 22, 2021
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ES9018K2M Datasheet
ANALOG PERFORMANCE
Test Conditions (unless otherwise stated)
1.
2.
TA = 25oC, AVCC = VCCA = DVCC = 3.3V, internal DVDD with 2.2F ±20% decoupling, fs = 44.1kHz, MCLK = 27MHz & 32-bit data
SNR / DNR: A-weighted over 20Hz-20kHz in averaging mode
THD+N: un-weighted over 20Hz-20kHz bandwidth
PARAMETER
Resolution
MCLK (PCM normal mode)
MCLK (PCM OSF bypass mode)
MCLK (DSD mode)
MCLK (SPDIF mode)
DYNAMIC PERFORMANCE
DNR (differential current mode)
THD+N (differential current mode)
ANALOG OUTPUT
CONDITIONS
Note *3
MIN
192FSR
24FSR
3FSR
386FSR
–60dBFS
0dBFS
Differential (+ or –) voltage output range
Full-scale out
Differential (+ or –) voltage output offset
Bipolar zero out
Differential (+ or –) current output range
(Note *1)
Full-scale out
Differential (+ or –) current output offset
(Note *1)
Bipolar zero out
to virtual ground
at voltage Vg (V)
Stop band
Group Delay
PCM Filter Characteristics (Slow Roll Off)
Pass band
Stop band
Group Delay
PCM Filter Characteristics (Minimum Phase)
Pass band
Stop band
MAX
Note *2
127
–120
V
3.783
mAp-p
2.112 – (1000 x
Vg) / 806
mA
0.2
dB
dB
0.454fs
0.49fs
Hz
Hz
Hz
s
0.308fs
0.454fs
Hz
Hz
Hz
s
0.454fs
0.49fs
Hz
Hz
Hz
0.546fs
35 / fs
0.05dB
–3dB
< –100dB
0.814fs
6.25 / fs
0.003dB
–3dB
< –115dB
0.546fs
Hz
Vp-p
127
0.003dB
–3dB
< –115dB
UNIT
Bits
dB-A
dB
3.05
(0.924 x AVCC)
1.65
(AVCC / 2)
Digital Filter Performance
De-emphasis error
Mute Attenuation
PCM Filter Characteristics (Sharp Roll Off)
Pass band
TYP
32
Notes
*1. Differential (+ or –) current output is equivalent to a differential (+ or –) voltage source in series with an 806 11%
resistor. The differential (+ or –) voltage source has a peak-to-peak output range of 0.924 x AVCC = 3.05V and an
output offset of AVCC / 2 = 1.65V.
*2. With internal DVDD, maximum MCLK frequency is 50MHz (DVCC = +1.8V), or up to 100MHz (DVCC = +3.3V) using
an external +1.3V DVDD supply.
*3. Synchronous MCLK at 128 x FSR is also supported.
31
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ES9018K2M Datasheet
PCM DE-EMPHASIS FILTER RESPONSE (32kHz)
PCM DE-EMPHASIS FILTER RESPONSE (44.1kHz)
PCM DE-EMPHASIS FILTER RESPONSE (48kHz)
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April 22, 2021
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ES9018K2M Datasheet
PCM FILTER FREQUENCY RESPONSE
dB
dB
dB
Unit: fs
33
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ES9018K2M Datasheet
PCM FILTER IMPULSE RESPONSE
Unit: 1/fs (s)
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April 22, 2021
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ES9018K2M Datasheet
DSD FILTER RESPONSE
dB
Unit: DATA_CLK (Hz) / 2822400
35
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ES9018K2M Datasheet
28-Pin QFN Mechanical Dimensions
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April 22, 2021
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ES9018K2M Datasheet
Example 28-Pin QFN Land Pattern
Notes:
1.
2.
3.
4.
5.
6.
37
All dimensions are in millimeters.
Thermal vias should be 0.3mm to 0.33mm in diameter, with the barrel plated to 1oz copper.
For maximum solder mask in the corners, round the inner corners of each row.
Exposed pad should be solder mask defined.
Pad width can be reduced to 0.25mm if additional pad to pad clearance is required.
For applications where solder loss through vias is a concern, plugging or tenting of the vias should be used. The
solder mask diameter for each via should be 0.1mm larger than the via diameter.
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
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ES9018K2M Datasheet
Reflow Process Considerations
For lead-free soldering, the characterization and optimization of the reflow process is the most important factor you need to
consider.
The lead-free alloy solder has a melting point of 217°C. This alloy requires a minimum reflow temperature of 235°C to
ensure good wetting. The maximum reflow temperature is in the 245°C to 260°C range, depending on the package size
(Table RPC-2). This narrows the process window for lead-free soldering to 10°C to 20°C.
The increase in peak reflow temperature in combination with the narrow process window makes the development of an
optimal reflow profile a critical factor for ensuring a successful lead-free assembly process. The major factors contributing to
the development of an optimal thermal profile are the size and weight of the assembly, the density of the components, the
mix of large and small components, and the paste chemistry being used.
Reflow profiling needs to be performed by attaching calibrated thermocouples well adhered to the device as well as other
critical locations on the board to ensure that all components are heated to temperatures above the minimum reflow
temperatures and that smaller components do not exceed the maximum temperature limits (Table RPC-2).
To ensure that all packages can be successfully and reliably assembled, the reflow profiles studied and recommended by
ESS are based on the JEDEC/IPC standard J-STD-020 revision D.1.
Figure RPC-1. IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1)
Note: Reflow is allowed 3 times. Caution must be taken to ensure time between re-flow runs does not exceed the allowed time by the
moisture sensitivity label. If the time elapsed between the re-flows exceeds the moisture sensitivity time bake the board according to the
moisture sensitivity label instructions.
Manual Soldering:
Allowed up to 2 times with maximum temperature of 350 degrees no longer than 3 seconds.
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ES9018K2M Datasheet
Table RPC-1 Classification reflow profile
Profile Feature
Preheat/Soak
Temperature Min (Tsmin)
Temperature Max (Tsmax)
Time (ts) from (Tsmin to Tsmax)
Ramp-up rate (TL to Tp)
Liquidous temperature (TL)
Time (tL) maintained above TL
Pb-Free Assembly
Peak package body temperature (Tp)
Time (tp)* within 5°C of the specified
classification temperature (Tc),
see Figure RPC-1
Ramp-down rate (Tp to TL)
150°C
200°C
60-120 seconds
3°C / second max.
217°C
60-150 seconds
For users Tp must not exceed the classification temp in
Table RPC-2.
For suppliers Tp must equal or exceed the Classification
temp in Table RPC-2.
30* seconds
6°C / second max.
Time 25°C to peak temperature
8 minutes max.
* Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.
Note 1: All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow (e.g., live-bug).
If parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e., dead-bug), Tp shall be within ± 2°C of the live-bug Tp and still
meet the Tc requirements, otherwise, the profile shall be adjusted to achieve the latter. To accurately measure actual peak package body
temperatures refer to JEP140 for recommended thermocouple use.
Note 2: Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board assembly
profiles should be developed based on specific process needs and board designs and should not exceed the parameters in Table RPC-1.
For example, if Tc is 260°C and time tp is 30 seconds, this means the following for the supplier and the user.
For a supplier: The peak temperature must be at least 260°C. The time above 255°C must be at least 30 seconds.
For a user: The peak temperature must not exceed 260°C. The time above 255°C must not exceed 30 seconds.
Note 3: All components in the test load shall meet the classification profile requirements.
Table RPC-2 Pb-Free Process – Classification Temperatures (Tc)
Package Thickness
2.5 mm
Volume mm3, 2000
260°C
260°C
250°C
260°C
250°C
245°C
260°C
245°C
245°C
Note 1: At the discretion of the device manufacturer, but not the board assembler/user, the maximum peak package body temperature (Tp) can exceed the
values specified in Table RPC-2. The use of a higher Tp does not change the classification temperature (Tc).
Note 2: Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or non-integral heat sinks.
Note 3: The maximum component temperature reached during reflow depends on package thickness and volume. The use of convection reflow processes
reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD packages may still exist.
39
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
3.7
April 22, 2021
ES9018K2M Datasheet
ORDERING INFORMATION
Part Number
Description
Package
ES9018K2M
Sabre32 Reference 32-bit Low Power Stereo Audio DAC
28-pin QFN
The letter K identifies the package type QFN.
Revision History
Rev.
Date
Notes
1.4
June 6, 2014
1.5
July 22, 2014
1.6
August 26, 2014
1.7
September 8, 2014
1.8
September 24, 2014
Added SABRE SOUNDTM trademark
Updated ESS Technology FAX number. Added medical use disclaimer.
Emphasized that Pin 20 and the Exposed Pad must be connected to Digital
Ground
Added conditions when an external DVDD regulator is required
Corrected typo on Register#7 Bit [6:5], 3’dX changed to 2’dX.
Identified Left and Right channels for Registers #15 and #16 respectively.
Updated DAC output impedance from 781.25 to 806
Removed reference to Right Justified data format that is not supported
1.9
October 1, 2014
2.0
October 6, 2014
2.1
2.2
October 16, 2014
December 1, 2014
2.3
January 8, 2015
2.4
March 16, 2015
2.5
2.6
April 30, 2015
June 10, 2015
2.7
July 26, 2015
2.8
2.9
3.0
April 12, 2016
January 24, 2017
January 31, 2017
3.1
February 14, 2017
3.2
3.3
3.4
3.5
November 28, 2017
November 15, 2018
April 25, 2019
January 7, 2021
Added details on the use of an external +1.3V DVDD supply
Updated Revision Identification from Chip Marking diagram.
Added specification to the Absolute Maximum Ratings table
Added table to Register #65 description
Corrected value of differential current output range on page 29
Added details on decoupling required for the DVDD core supply.
Deleted old revision history from 0.1 to 0.91.
Added notes on the connection of reserved Bits in the device control registers.
Updated ESS contact information.
Added information on THD compensation and how to use Registers #22 to #25
Increased typical value of AVCC_L plus AVCC_R from 3mA to 8mA
Updated typical operating power on cover page.
Corrected SDA setup time from SCL rising units from “µs” to “ns”.
Added new specifications to the Absolute Maximum Ratings table.
Corrected typical power consumption values
Corrected THD compensation description.
Remove references to Revision W silicon, clarify I2C address description.
Added description for Registers #2, #3 and #9. Register #65 labeled as GPIO
Status. Added register map. Adjusted page number references as needed.
Remove ESS logo from pin diagram
Added Low Power Audio DAC description, removed Advanced Information
Added Cin / Co / Cclk information
Updated I/V converter filter circuit
3.6
3.7
March 26, 2021
April 22, 2021
Updated Register #9 default setting
Update SABRE SOUND® technology
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
40
April 22, 2021
3.7
ES9018K2M Datasheet
© 2021 ESS Technology, Inc.
ESS IC's are not intended, authorized, or warranted for use as components in military applications, medical devices or life support systems. ESS
assumes no liability whatsoever and disclaims any expressed, implied or statutory warranty for use of ESS IC's in such unsuitable applications.
No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic,
mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations
or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology, Inc. assumes no
responsibility for any errors contained herein. U.S. patents pending.
41
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-8800 • www.esstech.com
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