ADM8211

ADM8211 IEEE802.11b WLAN NIC Solution PCI/miniPCI/Cardbus Interface with MAC Unit + Baseband Processor (BBP) DATASHEET Rev. 1.1 Feb, 2003 Information in this document is provided in connection with ADMtek products. ADMtek may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." ADMtek reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The products may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. 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ADMtek Partnership Now & Future 1 REVISION HISTORY Revision Date Revision Description Mar, 2002 0.1 Draft Apr, 2002 0.3 Preliminary version Apr, 2002 0.4 Change EEPROM format Rename GPIO0 May, 2002 0.5 Rename EEPROM [54:60] as Tx Power May, 2002 0.6 Add missed pins in Pin Description, C1, C2, D1, D2 Oct, 2002 0.7 Remove unnecessary chapters Update EEPROM format Nov, 2002 0.8 Remove PWRLEDACT Remove GPIO2 Feb, 2003 1.0 Formal release Mar, 2003 1.1 Correct Chapter 6, Electrical Specifications ADMtek Partnership Now & Future 2 Content 1 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 GENERAL DESCRIPTION .................................................................5 FEATURES ............................................................................................6 HOST PCI INTERFACE .....................................................................................................................6 INDUSTRY STANDARD ......................................................................................................................6 802.11 MAC ....................................................................................................................................6 WEP ................................................................................................................................................6 WLAN TX/RX FIFO .....................................................................................................................7 WLAN SYNTHESIZER INTERFACE .................................................................................................7 EEPROM INTERFACE ....................................................................................................................7 LED DISPLAY ..................................................................................................................................7 MISCELLANEOUS.............................................................................................................................7 3 4 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 APPLICATION DIAGRAM.................................................................8 PIN ASSIGNMENT DIAGRAM..........................................................9 PIN DESCRIPTION............................................................................10 PCI INTERFACE.............................................................................................................................10 EEPROM INTERFACE .................................................................................................................. 11 SERIAL INTERFACE TO SYNTHESIZER ..........................................................................................12 RF I/F ............................................................................................................................................12 LED DISPLAY, GPIO.....................................................................................................................12 MISCELLANEOUS...........................................................................................................................13 ON CHIP REGULATOR PINS ............................................................................................................13 DIGITAL POWER PINS ...................................................................................................................13 ANALOG POWER PINS ...................................................................................................................13 ADMtek Partnership Now & Future 3 5.10 CLOCK PINS ..................................................................................................................................13 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 ELECTRICAL SPECIFICATIONS AND TIMINGS ......................14 ABSOLUTE MAXIMUM RATINGS ...................................................................................................14 OPERATING CONDITION................................................................................................................14 DC SPECIFICATIONS .....................................................................................................................14 EEPROM INTERFACE DC SPECIFICATION..................................................................................14 GPIO INTERFACE DC SPECIFICATION ........................................................................................15 RESET TIMING...............................................................................................................................15 EEPROM INTERFACE TIMING SPECIFICATION ..........................................................................15 7 PACKAGE............................................................................................17 ADMtek Partnership Now & Future 4 1 General Description ADM8211 is a high performance PCI/miniPCI/Cardbus single chip with WLAN MAC controller and Baseband processor integrated. ADMtek is the leading of networking SOC, based on mature experience, ADM8211 is designed as hardwired architecture to reach the cost effective target. With the features of SRAM-needless, power saving, WEP/fix, small-package…etc. ADM8211 is versatile for WLAN system manufacturers to develop IEEE 802.11b wireless product. Tx Buffer Management Tx FIFO Tx MAC Modulator DAC Arbiter WEP Engine Preamble/Header Synthesizer, RF I/F ADMtek Partnership Now & Future PCI/IF Control Rx Buffer Management Rx FIFO Rx MAC Demodulator ADC WLAN CSR Magic Pkt / Wake-up Frame WLAN CR EEPROM I/F LED/GPIO Clock Gen 5 2 Features 2.1 Host PCI interface Provides 32-bit PCI bus master data transfer Supports network operation with PCI system clock from 22 MHz to 33MHz Provides performance meter, PCI bus master latency timer, for tuning the threshold to enhance the performance Provides burst-transmit packet interrupt and transmit/receive early interrupt to reduce host CPU utilization. Supports memory-read, memory-read-line, memory-read-multiple, memory-write, memory-write-and-invalidate command while being bus master Supports big or little endian byte ordering Arbitration between DMA channel to minimize underflow or overflow 2.2 Industry standard PCI 2.2 /Cardbus interface ACPI and PCI power management 1.1 standard compliant IEEE802.11, IEEE802.11b 2.3 802.11 MAC MAC implements with State Machine No External SRAM needed Support auto-fallback from 11Mbps to 5.5, 2 and 1Mbps. Support Infrastructure, Ad-hoc under Distributed Coordination Function (DCF) Implementation the Point Coordination Function (PCF) operation RTS/CTS generation, Fragmentation, Beacon monitor/loss detection/generation. RX DA address filtering (multicast) with 64 entries. TIM (Traffic Indication Map) field decoding at Beacon frame reception Support DSSS (Direct Sequence Spread Spectrum) PHY. Front end chip power sequence control 2.4 WEP Internal encryption engine for WEP function, RC4, 40/104 bits key length selectable. ADMtek Partnership Now & Future 6 Randomly generated IV (Initialization Vector) for TX. ICV (Integrity Check Value) generation and check. 4 default shared key supported. TA/RA WEP individual key management with a 20-entry table. 2.5 WLAN TX/RX FIFO Provides two independent long FIFOs with 4k bytes each for transmission and receiving Bus master descriptor based host memory access Pre-fetch up to two transmit packets to guarantee standard inter frame space (IFS) Re-transmits no-ACKed packet without reloading from host memory. Support two TX descriptors for DCF and PCF application Automatically re-transmitting if TX under-run happened. 2.6 WLAN Synthesizer Interface Support RFMD compatible interface 2.7 EEPROM Interface Provides serial interface for read/write 93C46/93C66 EEPROM Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and Minimum-Grand from the 64 byte contents of 93C46/93C66 after PCI reset de-asserted in PCI environment. CIS data is recalled from 93C66 through ADM8211 in CARDBUS environment. 2.8 LED Display Power: Power on indication Link: Keep on while link Activity: Blinking at 10Hz while activity 2.9 Miscellaneous Low power application Support 3 GPIO pins CMOS .25um Process Provides 156/BGA package On chip 3.3V ~ 2.5V regulator 3.3V power supply with 5V/3.3V I/O tolerance ADMtek Partnership Now & Future 7 3 Application Diagram * Please refer to schematic provided by ADMtek EEPROM PCI / miniPCI / Cardbus Interface ADM8211 MAC+BBP RF PA SAW 44M Hz Crystal LEDs ADMtek Partnership Now & Future 8 4 Pin Assignment Diagram A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Bottom View 156-Pin BGA 1 A B VDDA C Q_in D Q_out E F G VSS 2 VSS GNDA I_in I_out VREF VDDA INTA# 3 4 5 6 7 PA_PE 8 PE1 9 PE2 VD33 MCLK 10 VD33 VD33 11 EECS EECK 12 EEDI EEDO LEDLINK 13 LEDACT 14 LE_IF# SYNDATA SYNCLK RXVGC TXVGC LNA_GS ANTSEL GNDA VSS VD33 VSSPST VD33 VDD VD33 RST# AD17 VDD VDD AD19 AD26 AD27 C-BEB2 AD21 AD20 VD33 VSS IRDY# GNDD VDDD VSSPST OSC44O OSC44I VSSPST CLK_44 GPIO3 VSSPST VSSPST VSSPST VSSPST BW_SEL VSSPST VSENSE VD33 AD2 AD5 GPIO1 VSA VSSPST AD1 AD3 AD11 VSS VSS C-BEB1 VCTL VAUX3.3 VDDAH AD0 H REQ# PCI-CLK J AD31 PME#/ CSTSCHG VCC_DETECT CLKRUN VSSPST AD4 AD8 AD14 AD10 VD33 AD6 C-BEB0 AD7 K GNT# VSSPST VSSPST L AD28 M VDD N AD24 P AD29 FRAME# C-BEB3 IDSEL AD30 VDD AD22 AD23 AD25 DEVSEL# AD16 VSSPST AD18 AD13 SERR# AD9 AD12 AD15 PAR VD33 PERR# STOP# VSS VD33 TRDY# VSSPST VSSPST PCI/CB ADMtek Partnership Now & Future 9 5 Pin Description 5.1 PCI Interface Pin Name G2 INTA# K4 RST# Type O/D I Description PCI interrupt acknowledge. PCI reset signal, at least 100µs. During the reset period, all the output pins of ADM8211 will be set to tri-state and all the O/D pins are floated. This PCI clock inputs to ADM8211. The bus signals are recognized on rising edge of PCI-CLK. The frequency range of PCI-CLK is limited between 20MHz and 33MHz. This signal indicates that the bus request of ADM8211 have been accepted. Bus master device request. The Power Management Event signal is an open drain, active low signal for PCI (PME#) When CSR18.bit19 is set into “1”, means that the ADM8211 is set into Power Save mode. In this mode, when the ADM8211 receives a Beacon (TIM) or ATIM frame from network then the ADM8211 will active this signal too. J1 L3 L2 L1 M5 L5 L7 N1 P3 N3 P5 L6 P4 N8 L4 L9 M11 N13 M8 L11 M12 P13 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 10 I/O Multiplexed address data pin of PCI Bus H2 PCI-CLK I K1 H1 J2 GNT# REQ# I O PME# / I/O CSTSCHG ADMtek Partnership Now & Future L10 M13 N14 L14 K11 L13 K12 J11 J12 H14 N2 N5 P12 M14 P2 M2 P6 P7 L8 M10 M9 N8 N11 J14 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 C-BEB3 C-BEB2 C-BEB1 C-BEB0 IDSEL FRAME# IRDY# TRDY# STOP# PERR# SERR# PAR I I/O I/O I/O I/O I/O O/D I/O Initialization Device Select. This signal is asserted when host issues the configuration cycles to the ADM8211. Begin and duration of bus access, driven by master device Master device is ready to data transaction Slave device is ready to data transaction Device select, target is driving to indicate the address is decoded Target device request the master device to stop the current transaction Data parity error is detected, driven by the agent receiving data Address parity error Parity, even parity (AD[31:0] + C/BE[3:0]), master drives par for address and write data phase, target drives par for read data phase Clock Run for PCI system. In the normal operation situation, Host should assert this signal to indicate ADM8211 about the normal situation. On the other hand, when Host will deassert this signal when the clock is going down to a nonoperating frequency. When ADM8211 recognizes the deasserted status of clk-run, then it will assert clk-run to request host to maintain the normal clock operation. When clk-run function is disabled then the ADM8211 will set clk-run in tri-state. Bonding low to select CARD bus mode. Internal pull up. 5V-tolerant I/O Bus command and byte enable DEVSEL# I/O CLKRUN I/O O/D P10 PCI/CB I 5.2 EEPROM Interface Pin Name Type B11 EECK I/O A12 EEDI I/O Description ECK: Clock output to serial EEPROM. pull-up, 5V tolerant EDI: Data output to serial EEPROM. pull-up, 5V tolerant ADMtek Partnership Now & Future 11 B12 A11 EEDO EECS I/O O EDO: Data input from serial EEPROM pull-up, 5V tolerant Chip Select of serial EEPROM Pull-down, 5V tolerant 5.3 Serial Interface to Synthesizer Pin B5 B7 B6 Name LEIF# SYNCLK SYNDATA Type O, pull-up O, pull-up O, pull-up Description Synthesizer 2 Chip Select Clock Data 5.4 RF I/F Pin Name Type Description A8 A9 E12 A7 C1 D1 C2 D2 PE1 PE2 BW_SEL PA_PE Q_in Q_out I_in I_out O, pull-up O, pull-up O O, pull-up I O I O Power enable 1 Power enable 2 Channel 14 control pin Transmit PA Power Enable Analog Q input Analog Q output 1.6V-1.8V Analog I input Analog I output 1.6V-1.8V 5.5 LED display, GPIO Pin Name Type Description LED Drive. C12 LEDLINK O, pull-up 10 Hz blinking while either of following 2 conditions effective, even at D3-Cold. (1) Association successful with AP (2) Beacon reception when join IBSS A13 F12 D14 GPIO3 I/O LEDACT GPIO1 O, pull-up I/O LED Drive. 10 Hz blinking while TX/RX Frame is detected General-purpose I/O pins, refer to GPIOEN setting (CSR11A). Pull-up, 5V tolerant General-purpose I/O pins, capable of event, rise/fall edge or toggle, capturing to generate interrupt to host, if enabled. Pull-up, 5V tolerant ADMtek Partnership Now & Future 12 5.6 Miscellaneous Pin Name H13 Vaux3.3 Type I, Schmmit 5V tolerant J13 VDD_detect I, Schmmit 5V tolerant Description When asserted, it indicates an auxiliary power source is supported ACPI purpose, for detecting the auxiliary power source. When asserted, it indicates PCI power source is supported. ACPI purpose, for detecting the main power is remained or not, this pin should be connected to PCI bus power source +3.3V. 5.7 On chip regulator Pins Pin Name Type Description G13 G12 G14 G11 REGCTL VSA VDDAH VSENSE I/O Power Power I Regulator control pin GND for regulator 3.3V for regulator 2.5V sense input 5.8 Digital Power Pins Pin Name Type Description F4, H4, J4, M6, B9, A10, B10,H11, N10, P11, VDD33 J14 K2, K3, G4, M7, P8, P9, D11, E11, F11, D12, VSSPST H12, E13, K13, B14, E14 G1, M1, J1, M3, M4, N4, M12, N12 A2, G3, N6, N9, D8 D7 VDD VSS VDDD GNDD Power Power Power Power Power Power 3.3V for IO Gnd for IO 2.5V for core Gnd for core Vcc for BBP (leave open) Gnd for BBP 5.9 Analog Power Pins Pin Name Type Description B1, F2 B2, F3 VDDA GNDA Power Power 3.0V for BBP Analog Gnd for BBP 5.10 Clock Pins Pin Name Type Description A13 C13 C14 OSC44I OSC44O CLK44 I O O, pull-up 44 MHz clock input 44 MHz clock output Buffered 44Mhz clock output This signal will be stopped, forced low, during MAC enter into power saving mode. ADMtek Partnership Now & Future 13 6 Electrical Specifications and Timings 6.1 Absolute Maximum Ratings Supply Voltage (VDD) DC Input Voltage (VIN) DC Output Voltage (VOUT) Storage Temperature Ambient Temperature ESD Rating -0.3 V to 3.6 V -0.5 V to VDD+0.5V -0.5 V to VDD+0.5V -65 C to 150 C 0 C to 70 C 2000V 6.2 Operating Condition Symbol VDD Parameter Supply Voltage Condition Min 3.0 Max 3.6 Units V 6.3 DC Specifications Symbol Parameter Vih Vil Iih Vcm Voh Vol Vcrs Input High Voltage Input Low Voltage Differential Input Sensitivity Differential Common Mode Range Output High Voltage Output Low Voltage Output Voltage Signal Crossover 0.1 0.8 2.8 0.0 0.8 2.5 3.6 0.3 2.5 Condition Min 2.0 0.8 Max Units V V V V V V V 6.4 EEPROM Interface DC specification Standard Vcc (4.5V to 5.5V) DC Specification Symbol Parameter Vih Vil Iih Iil Vol Voh Cin Input High Voltage Input Low Voltage Input High Leakage Current 0