AV2188

AVS Technology FEATURES • Six Channel 24/20-bit DACs. - 102 dB SNR - 104 dB Dynamic Range. - -90 dB THD + N Ratio. - 32, 44.1 48 and 96 KHz. Sampling rates. - 20-bit and 24-bit Digital Inputs. - Containing Digital De-emphasis Filters. - Digital Volume Control. - I2S, Left and Right Justified Digital Input Formats. - Auto-Mute Control. - On -chip Reconstruction Filters. • Two Channel Stereo ADCs - 32, 44.1 and 48 KHz. Sampling Rate. - 100 dB SNR and Dynamic Range. - -96 dB THD + N Ratio. AV2188 Multi-Channel Audio CODEC - I2S and Left Justified Output Formats. • System clock: 384 fs for 32, 44.1 or 48 KH. Sampling Rates, 194 fs for 96 KHz. Sampling Rate. General • Automatic input format detection. • 5-volt Power Supply. • 3.3 -volt Digital Interface Frindly. • I2C Interface for Mode Setting. Applications • Digital Surround Sound For Home Theater • DVD • Car Audio. Ordering Information • 28 pin SOJ package SDA SCL 80 I2C Serial Control Port AV2188 D/A D/A 40KHz 40KHz 40KHz 40KHz 40KHz 40KHz VOR3 VOL3 SD1 SD2 SD3 5th Order Σ∆ Modulators Digital Volume De-Emphasis 96 Times Over-sampling Filters 80 D/A D/A D/A D/A VOR2 VOL2 VOR1 VOL1 Audio I/F Serial 77 SDOUT 80 SF SC 77 78 High Pass Filter Format Detect'n PLL Decimation Filter A/D A/D BIN AIN 15 XCK RST AVS Technology Inc. 4110 Clipper Ct., Fremont CA94538 Tel: (510) 353-0848 Fax: (510) 353-0856 1-20 June 2, 2000 AV2188 Item PERFORMANCE SPECIFICATIONS Audio DAC Spec. 1 2 3 4 5 6 7 8 9 10 Audio Output Level Audio Bandwidth 20Hz - 20 KHz SNR (A-weight, Muted) SNR (A-weight, Not Muted) THD + N (A-weight, 0.5 FFS Output) THD + N (A-weight, FFS Output) Dynamic Range Channel Separation Nonlinear Distortion Channel Gain Error 1 Vrms +/- 0.5 dB >102 dB >96 dB < -100 dB < -92 dB 104 dB < -97 dB < 0.25 dB < 0.1 dB Audio ADC 1 2 2 3 4 4 Full Scale Audio Input Level Maximum Input Level Audio Bandwidth SNR THD + N (A-weight, 0.5 FFS Input) Dynamic Range 1.5 Vp-p 5.0 Vp-p 20 KHz 98 dB 96 dB 98 dB All Measurement were taken with only one channel active. 2-20 June 2, 2000 AV2188 DESCRIPTION The AV2188 is a mixed signal CMOS monolithic audio CODEC. It consists six channels sigma delta DACs and two channels sigma delta ADCs. The DACs support 20-bit and 24-bit input data, while the ADCs provides 24-bit MSB justified data output. XCK REQUIREMENT The AV2188 support 384 and 256 times sampling clock for 32, 44.1 and 48 K audio; 192 and 128 times for the 96 K audio.; and 96 and 64 times for the 192K audio. . XCK Requirement Sampling Rate 32 K 44.1 48 K 96 K 192 K XCK Freq. 384*fs 12.288 MHz 16.934 Mhz 18.432 MHz 18.432 MHz 18.432 Mhz 256*fs 8.192 MHz 11.29 Mhz. 12.288 Mhz. 12.288 Mhz. 12.288 Mhz. 3-20 June 2, 2000 AV2188 PIN ASSIGNMENT SD1 SD2 SD3 SDOUT SC SF DGND DVDD DGND XCK SCL SDA TST RST 1 2 3 4 5 28 27 26 25 24 AR3 AL3 AR2 AL2 AR1 AL1 AGND CM2 AVDD CM1 AGND RIN LIN N/C AV2188 6 7 8 9 10 11 12 13 14 23 22 21 20 19 18 17 16 15 PIN DESCRIPTION Pin Name DIGITAL SD1 SD2 SD3 SDOUT SC SF 1 2 3 4 5 6 I I I O I I Audio Serial Data Input 1, data can be 20bit/24bit, Right justified, or 24bit Left justified, or 24bit I2S, all in 2’s complement format. Audio Serial Data Input 2, data can be 20bit/24bit, Right justified, or 24bit Left justified, or 24bit I2S, all in 2’s complement format. Audio Serial Data Input 3, data can be 20bit/24bit, Right justified, or 24bit Left justified, or 24bit I2S, all in 2’s complement format. Serial Audio Output pin, data can be in 20bit Right justified or 20bit I2S format. Audio Serial Data Clock pin. Left/Right Channel Clock pin. For Left justified or Right justified mode, a high in SF indicates Left Channel Data, a low in SF indicates Right Channel Data. For I2S mode, a low in SF indicates Left Channel Data, a high in SF indicates Right Channel Data. Digital ground Digital power supply. Pin # Type Description DVSS DVDD 7 8 GND +5V 4-20 June 2, 2000 AV2188 PIN DESCRIPTION (Continued) Pin Name DVSS XCK SCL SDA TEST RST Pin # 9 10 11 12 11 12 Type GND I I I/O O I Digital ground External Master Clock Input. I2C clock input. I2C DATA bus. Open drain ouput. Externally this pin should tie to a 680 ohm pull up resistor. Test fs reference pin. For test vector verification. For normal operation this pin must be tied to ‘0’. Active low power down reset. When low, the chip is reset and all programmable registers are reset to default values. Must activate this pin if the P/S or ADDR[1:0] change state. Description Analog VOL3 VOR3 VOL2 VOR2 VOL1 VOR1 AVSS VCM2 AVDD VCM1 AVSS AINR AINL N/C 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND I I +5V O O O O O O GND Analog left channel output 3 Analog right channel output 3. Analog left channel output 2. Analog right channel output 2. Analog left channel output 1. Analog right channel output 1. Analog circuits ground Common voltage output pin for the DAC. Analog circuits power supply Common voltage output pin for the ADC. Analog circuits ground ADC right cahnnel input. 1 volt rms input. ADC left channel input. 1 volt rms input. No connection, should be tied to AVSS 5-20 June 2, 2000 AV2188 DIGITAL AUDIO SERIAL INTERFACE The digital serial interface consists of 3 serial input pins, SD1, SD2, and SD3, one serial output pin, SDOUT, one serial clock input pin, SC, and one left/right indicator input pin, SF. The data are 2’s complement MSB first numbers. The AV2188 supports four resolutiont, which are selected either by setting the FMT[1] and FMT[0] pins or by programming the control register CREG0[5:4] via the I 2C serial control port. Table 1 describes these four resolution. . Table (1): Audio Serial Data Input Format Format 0 1 2 3 CREG0[5] 0 0 1 1 CREG0[4] 0 1 0 1 SD1, SD2, and SD3 24-bit 20-bit 18-bit 16-bit 24-bit SDOUT The SD3, SD2 and SD1 can be either 24-bit or 32-bit per frame as well as left justified, right justified or I2S. The SDOUT only support left justified and I2S format. The AV1488 counts the number of BCK per frame to determine whether the input is 24 or 32 bits format. Table (1): Audio Serial Data Input Modes Mode 0 1 2 3 CREG0[7] 0 0 1 1 0REG0[6] 0 1 0 1 SD1, SD2, and SD3 Right Justified I2S Left Justified Invalid SDOUT Left Justified I2S Left Justified 6-20 June 2, 2000 AV2188 Figure 1. Audio Serial Input Data Timing Diagram 1/fs SF SC MSB SD1,2,3 LEFT CHANNEL RIGHT CHANNEL LSB 2 1 0 MSB 2 1 LSB 0 Right justified, CREG0[7,6]=[1 1] LEFT CHANNEL 1/fs RIGHT CHANNEL SF SC MSB SD1,2,3 LSB 0 MSB 1 LSB 0 Left justified, CREG0[7,6]=[1 0] 1/fs LEFT CHANNEL SF SC MSB SD1,2,3 1 0 RIGHT CHANNEL LSB MSB 1 LSB 0 IIS, CREG0[7,6]=[0 1] Figure 2. 7-20 June 2, 2000 AV2188 Figure 3. Audio Serial Output Data Timing Diagram 1/fs SF SC MSB SD1,2,3 23 22 21 LEFT CHANNEL RIGHT CHANNEL LSB 2 1 0 MSB 23 22 21 2 1 0 LSB Left justified, CREG0[7,6]=[X 0] LEFT CHANNEL SF SC SD1,2,3 MSB 23 22 21 2 1/fs RIGHT CHANNEL LSB 1 0 MSB 23 22 21 2 LSB 1 0 IIS, CREG0[7,6]=[0 1] 8-20 June 2, 2000 AV2188 INFINITE ZERO DETECTION The AV2188 has an Infinite Zero Detection circuit which detects zero in the Audio Serial Port that lasts for approximately 0.5 sec. By default, the zero detection circuit is on. To disable this feature, bit 7 of the programmable register TREG1[7] must be programmed to a “one”. SERIAL COMMAND PORT The user can use the pin to select the chip operation or by programming the internal control registers through the 7 bit address I2C port. The Chip Address for the AV2188 is 31H. The protocal for write operation consists of sending 3 byte data to AV2188, following each byte are the acknowledges generated by AV2188. The first byte is the 7-bit Chip Address followed by the read/write bit (read is high write is low). The second byte is the control register address. The third byte is the control register data. Upon power up, all programmable registers are set to default values. Figure 4 describes the serial command port timing relationship. Figure 4. Serial Command Port Timing I2 C Bus Control Register write example: Start CA6 CA0 R/W ACK A7 A0 ACK D7 D0 ACK Stop SDA 1 1 1 SCL Chip adrress: CA = 31H Register address: A = 00H DATA: D = 30H 9-20 June 2, 2000 AV2188 SERIAL PORT CONTROL REGISTER ASSIGNMENT There are 3 registers dedicated to the AV2188 for chip functional programmin,. One register for testinging. The register addresse assignments are Address (decimal) 0 1 2 3 Register CREG0[7:0] CREG1[7:0] VOLREG[7:0] TREG1[7:0] Default Value 00 00 80 00 Register Function Data input format, de-emphasis filter selection DAC and ADC power down control Volume control Test control 10-20 June 2, 2000 AV2188 CONTROL REGISTERS DESCRIPTION Control Register 0(ADDR=hex00, default=hex80) CREG0[7:0] ADDR[4:0] BIT 7 Hex 00 Default Value R/W LT BIT 6 IIS BIT 5 BIT 4 BIT 3 AMUTE 0 R/W BIT 2 BIT 1 BIT 0 FMT[1:0] DEM[1:0] 0 R/W 0 R/W 0 R/W 0 R/W [LT, IIS] Digital Serial Bus Format Select 00: - Normal or Right Justified Format. (default) 01: - I2S Format. 10: - Left Justified Format. 10: - Not allowed. FMT[1:0]: - These two bits define the seial audio input resolution 00: - 24-bit resolution . (default) 01: - 20-bit resolution. 10: - 18-bit resolution. 11: - 16-bit resolution. AMUTE: - Active low automute detection enable. 0: - Automute enabled. (default) 1: - No automute. DEML: - De-emphasis Control 00: - No De-emphasis. (default) 01: - Select 44.1K de-emphasis filter. 10:- Select 48 K de-emphasis filter. Control Register 1 (ADRS=hex01, default=hex80) CREG1[7:0] ADDR[4:0] BIT 7 Hex 01 Default Value R/W ADCPWD 1 R/W 0 BIT 6 BIT 5 fs384 0 R/W BIT 4 px4s 0 R/W BIT 3 px2s BIT 2 DACPWD12 0 R/W BIT 1 DACPWD34 0 R/W BIT 0 DACPWd56 0 R/W ADCPWD: ADC Control. 0 - ADC operational. 1 - Power down the ADC. 11-20 June 2, 2000 AV2188 DACPWD56: DAC5 and DAC6 Control. 0 - DAC5 and DAC 6 operational. 1 - Power down the DAC5 and DAC6. DACPWD43: DAC3 and DAC4 Control. 0 - DAC3 and DAC4 operational. 1 - Power down the DAC3 and DAC4. DACPWD21: DAC2 and DAC1 Control. 0 - DAC2 and DAC1 operational. 1 - Power down the DAC2 and DAC1. Volume Registers, (ADRS=hex02, default=hex80) Volume Registers ADDR[4:0] BIT 7 Hex 02 Default Value VLREG[7:0] 1 0 0 0 0 0 0 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VOLREG:- Control the volume of the 6 DAC’s 80h- corresponds to 0 dB setting. 12-20 June 2, 2000 AV2188 Application Connection Example: Digital 12 ohm Analog +5 Volt 20 AVCC 28 22 uF 8 DVCC 1 SD1 2 SD2 3 SD3 22 uF 22 uF AR3 AV2188 27 AL3 26 22 uF 22 uF 22 uF 22 uF 22 uF Digital Audio Interface 4 SDOUT 5 CF 6 SF AR1 AL2 AR2 25 24 23 384 or 256 Times SF C lock 10 XCK AL1 +5 Volt 680 ohm 11 I C Serial Interface 2 21 CM2 47uF SCL 12 SDA 19 CM1 47uF 13 TST RIN 17 220 ohm 22 uF 200K 14 Reset RST LIN DVSS 16 220 ohm 22 uF 200K AVSS 15 18 22 All Unmarked Capacitors are 0.1 uF 7 9 13-20 June 2, 2000 AV2188 TIMING DIAGRAM Figure 5. Audio Serial Interface Timing Requirement tsc SC tsdhd tsdsu SD1 SD2 SD3 tscsf SF tsfsc tscH tscL Figure 6. Serial Data Output Timing Requirement tscH SC tscL tscsdo SDOUT tsfsdo SF 14-20 June 2, 2000 AV2188 Figure 7. Serial Command Port Write Timing Requirement tBUF tSU;STA SDA tHD;STA tHIGH tSU;DAT tSU;STO SCL P S tLOW tR tF tHD;DAT Sr P Figure 8. Power Down / Reset Timing trst PWD 15-20 June 2, 2000 AV2188 ABSOLUTE MAXIMUM RATINGS Symbol VDD Vi Ai Vo Ao TDsc TASC Ta Tstg Tj Tsol Tvsol Tstor Notes: Characteristics Power Supply Voltage (Measured to GND) Digital Input Applied Voltage2 Digital Input Forced Current3,4 Digital Output Applied Voltage2 Digital Output Forced Current3,4 Digital Short Circuit Duration (single output high state to Vss) Min -0.5 GND-0.5 -100 GND-0.5 -100 Max +7.0 Units V V 100 VDD+0.5 100 1 infinite mA V mA Sec Sec o o o o o o Analog Short Circuit Duration (single output to VSS1) Ambient Operating Temperature Range Storage Temperature Range Junction Temperature (Plastic Package) Lead Soldering Temperature (10 sec., 1/4” from pin) Vapor Phase Soldering (1 minute) Storage Temperature -65 -25 -65 -65 +125 +150 +150 300 220 +150 C C C C C C 1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. Applied voltage must be current limited to specified range, and measured with respect to VSS. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device. 16-20 June 2, 2000 AV2188 RECOMMENDED OPERATING CONDITIONS Symbol VDD VVCM RL Ta Characteristics Power supply voltage Reference voltage Analog output load Ambient operating temperature range Min 4.5 Typical 5 2.25 37.5 Max 5.5 2.41 70 70 Units V V Ω o 0 C ELECTRICAL CHRACTERISTICS Parameter Supply IDD IDDQ Characteristics Min Typ Max Units Total Power Supply Current, Analog + Digital Total Power Supply Current,ADC Power Down 135 115 145 120 mA mA Digital Characteristics VIH VIL IIH IIL CIN VOH VOL IOZH IOZL CI CO Digital Input Voltage, Logic HIGH, TTL Compatible Inputs. Digital Input Voltage, Logic LOW, TTL Compatible Inputs Digital Input Current, Logic HIGH, (VIN=4.0V) Digital Input Current, Logic LOW, (VIN=0.4V) Digital Input Capacitance (f=1Mhz, VIN=2.4V) Digital Output Voltage, Logic HIGH, (IOH= -1mA) Digital Output Voltage, Logic LOW, (IOL=4.0 mA) Hi-Z Leakage Current, HIGH, VDD=Max, VIN=VDD) Hi-Z Leakage Current, LOW, VDD=Max, VIN=VSS) Digital Input Capacitance (TA=25oC, f=1Mhz) Digital Output Capacitance (TA=25oC, f=1Mhz) 3.2 VSS 3.4 2.0 VSS VDD 0.8 10 -10 7 3.5 0.4 10 -10 8 10 V V µA µA pF V V µA µA pF pF 17-20 June 2, 2000 AV2188 Parameter Characteristics Min Typ Max Units Audio Serial Interface Timing tsc SC Cycle Time SC Pulse Width, HIGH SC Pulse Width, LOW Audio Data Setup Time With Respect To Rising Edge of SC Audio Data Hold Time With Respect to Rising Edge of SC Audio SFSetup Time With Respect To Rising Edge of SC Audio SF Hold Time With Respect To Rising Edge of SC SC falling edge to SDOUT SF transition to SDOUT 120 50 50 30 30 30 30 50 30 ns ns ns ns ns ns ns ns ns tscH tscL tsdsu tsdhd tsfsc tscsf tscsdo tsfsdo Reset Signal trst Active low reset time 1 µs Serial Command Port fsc tsu;sta thd;sta tsu;sto tLOW tHIGH tr tf tsu;DAT thd;DAT tvd;DAT tBUF SCL Clock Frequency Start condition set up time Start condition hold time Stop condition set up time SCL Low time SCL High time SCL & SDA rise time SCL & SDA fall time Data set-up time Data hold time SCL LOW to data out valid Bus Free time 4.7 250 0 4.7 4.0 4.0 4.7 4.0 100 kHz us us us us us 1.0 0.3 us us ns ns 3.4 us us 18-20 June 2, 2000 AV2188 Parameter Characteristics Min Typ Max Units Audio DAC Characteristics SNR THD+N Signal To Noise Ratio Total Harmonic Distortion + Noise Dynamic Range Channel Separation Full Scale Output Voltage Center Voltage Inter-channel Gain Mismatch Analog Output Load Resistance Analog Output Load Capacitance 5 100 102 84 .95 2.15 101 103 94 104 97 1 2.25 0.1 1.09 2.4 dB dB dB dB Vrms V dB KΩ pF Audio ADC Characteristic SNR THD+N Signal To Noise Ratio Total Harmonic Distortion + Noise Dynamic Range Channel Separation Full Scale Input Voltage Center Voltage Inter-channel Gain Mismatch Analog Input Load Capacitance 98 94 104 96 1.1 2.25 0.1 30 2.4 dB dB dB dB Vrms V dB pF 19-20 June 2, 2000 AV2188 PACKAGING INFORMATION Dimensions Mils min A A1 norm max min Mils norm max 93 4 14 9 691 100 8 16 10 702 104 12 19 12 713 E1 E2 291 394 295 406 50 299 419 b C D e L 20 30 40 28-Pin (SOP) D E1 E2 A1 A b e L 20-20 June 2, 2000