BQ2050SNN

bq2050 Lithium Ion Power Gauge™ IC Features ➤ Conservative and repeatable measurement of available capacity in Lithium Ion rechargeable batteries ➤ Designed for battery pack integration General Description The bq2050 Lithium Ion Power Gauge™ IC is intended for batterypack or in-system installation to maintain an accurate record of available battery capacity. The IC monitors a voltage drop across a sense resistor connected in series between the negative battery termina l a n d g r ou n d t o d e t e r m i n e charge and discharge activity of the battery. Compensations for battery temperature and rate of charge or discharge are applied to the charge, discharge, and self-discharge calculations to provide available capacity information across a wide range of operating conditions. Battery capacity is automatically recalibrated, or “learned,” in the course of a discharge cycle from full to empty. Nominal available capacity may be directly indicated using a fivesegment LED display. These segments are used to graphically indicate available capacity. The bq2050 supports a simple single-line bidirectional serial link to an external processor (common ground). The bq2050 outputs battery information in response to external commands over the serial link. The bq2050 may operate directly from one cell (VBAT > 3V). With the REF output and an external transistor, a simple, inexpensive regulator can be built for systems with more than one series cell. Internal registers include available capacity, temperature, scaled available energy, battery ID, battery status, and programming pin settings. To support subassembly testing, the outputs may also be controlled. The external processor may also overwrite some of the bq2050 power gauge data registers. - 120µ A typical operating current Small size enables implementations in as little as 1 2 square inch of PCB ➤ Integrate within a system or as a stand-alone device - Display capacity via singlewire serial communication port or direct drive of LEDs ➤ Measurements compensated for current and temperature ➤ Self-discharge compensation using internal temperature sensor ➤ 16-pin narrow SOIC Pin Connections Pin Names LCOM LED common output LED segment 1/ program 1 input LED segment 2/ program 2 input RBI SEG3/PROG3 LED segment 3/ program 3 input LED segment 4/ program 4 input LED segment 5/ program 5 input Program 6 input SB DISP SR SEG5/PROG5 PROG6 VCC VSS REF N/C DQ SEG2/PROG2 Voltage reference output No connect Serial communications input/output Register backup input Battery sense input Display control input Sense resistor input 3.0–6.5V System ground LCOM SEG1/PROG1 SEG2/PROG2 SEG3/PROG3 SEG4/PROG4 SEG5/PROG5 PROG6 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC REF N/C DQ RBI SB DISP SR SEG1/PROG1 SEG4/PROG4 16-Pin Narrow SOIC PN205001.eps 9/96 C 1 bq2050 Pin Descriptions LCOM LED common output Open-drain output switches VCC to source current for the LEDs. The switch is off during initialization to allow reading of the soft pull-up or pull-down program resistors. LCOM is also high impedance when the display is off. SEG1– SEG5 LED display segment outputs (dual function with PROG1–PROG6) Each output may activate an LED to sink the current sourced from LCOM. PROG1– PROG2 Programmed full count selection inputs (dual function with SEG1–SEG2) These three-level input pins define the programmed full count (PFC) thresholds described in Table 2. PROG3– PROG4 Power gauge rate selection inputs (dual function with SEG3–SEG4) These three-level input pins define the scale factor described in Table 2. PROG5 Self-discharge rate selection (dual function with SEG5) This three-level input pin defines the selfdischarge and battery compensation factors as shown in Table 1. PROG6 Capacity initialization selection This three-level pin defines the battery state of charge at reset as shown in Table 1. N/C No connect DQ RBI SB DISP SR Sense resistor input The voltage drop (VSR) across the sense resistor RS is monitored and integrated over time to interpret charge and discharge activity. The SR input is tied between the negative terminal of the battery and the sense resistor. VSR < VSS indicates discharge, and VSR > VSS indicates charge. The effective voltage drop, VSRO, as seen by the bq2050 is VSR + VOS . Display control input DISP high disables the LED display. DISP tied to VCC allows PROGX to connect directly to VCC or VSS instead of through a pull-up or pull-down resistor. DISP floating allows the LED display to be active during charge. DISP low activates the display. See Table 1. Secondary battery input This input monitors the battery cell voltage potential through a high-impedance resistive divider network for end-of-discharge voltage (EDV) thresholds, and battery removed. Register backup input This pin is used to provide backup potential to the bq2050 registers during periods when VCC ≤ 3V. A storage capacitor or a battery can be connected to RBI. Serial I/O pin This is an open-drain bidirectional pin. REF Voltage reference output for regulator REF provides a voltage reference output for an optional micro-regulator. VCC VSS Supply voltage input Ground 2 bq2050 Functional Description General Operation The bq2050 determines battery capacity by monitoring the amount of current input to or removed from a rechargeable battery. The bq2050 measures discharge and charge currents, measures battery voltage, estimates self-discharge, monitors the battery for low battery voltage thresholds, and compensates for temperature and charge/discharge rates. The current measurement is made by monitoring the voltage across a small-value series sense resistor between the negative battery terminal and ground. The estimate of scaled available energy is made using the remaining average battery voltage during the discharge cycle and the remaining nominal available charge. The scaled available energy measurement is corrected for the environmental and operating conditions. Figure 1 shows a typical battery pack application of the bq2050 using the LED display capability as a chargestate indicator. The bq2050 is configured to display capacity in relative display mode. The relative display mode uses the last measured discharge capacity of the battery as the battery “full” reference. A push-button display feature is available for momentarily enabling the LED display. The bq2050 monitors the charge and discharge currents as a voltage across a sense resistor (see RS in Figure 1). A filter between the negative battery terminal and the SR pin may be required if the rate of change of the battery current is too great. R1 bq2050 Power Gauge IC REF C1 0.1 F LCOM SEG1/PROG1 SEG2/PROG2 SEG3/PROG3 SEG4/PROG4 SEG5/PROG5 PROG6 PSTAT VSS RBI DQ DISP SR RS VCC SB VCC VCC C2 RB2 RB1 1M Q1 ZVNL110A Indicates optional. Directly connect to VCC across 1 cell (VBAT > 3V). Otherwise, R1, C1, and Q1 are needed for regulation of > 1 cell. Programming resistors (6 max.) and ESD-protection diodes are not shown. R-C on SR may be required, application-specific. A series Zener may be used to limit discharge current at low voltages in designs using 3 or more cells. Charger Load FG205001.eps Figure 1. Battery Pack Application Diagram—LED Display 3 bq2050 Voltage Thresholds In conjunction with monitoring VSR for charge/discharge currents, the bq2050 monitors the battery potential through the SB pin. The voltage is determined through a resistor-divider network per the following equation: RB1 = 2N − 1 RB2 where N is the number of cells, RB1 is connected to the positive battery terminal, and RB2 is connected to the negative battery terminal. The single-cell battery voltage is monitored for the end-of-discharge voltage (EDV). EDV threshold levels are used to determine when the battery has reached an “empty” state. Two EDV thresholds for the bq2050 are programmable with the default values fixed at: EDV1 (early warning) = 1.52V EDVF (empty) = 1.47V If VSB is below either of the two EDV thresholds, the associated flag is latched and remains latched, independent of VSB, until the next valid charge. The VSB value is also available over the serial port. During discharge and charge, the bq2050 monitors VSR for various thresholds used to compensate the charge and discharge rates. Refer to the count compensation section for details. EDV monitoring is disabled if the discharge rate is greater than 2C (typical) and resumes 1 second after the rate falls below 2C. 2 TMP (hex) 0x 1x 2x 3x 4x 5x 6x 7x 8x 9x Ax Bx Cx Temperature Range < -30°C -30°C to -20°C -20°C to -10°C -10°C to 0°C 0°C to 10°C 10°C to 20°C 20°C to 30°C 30°C to 40°C 40°C to 50°C 50°C to 60°C 60°C to 70°C 70°C to 80°C > 80°C RBI Input The RBI input pin is intended to be used with a storage capacitor or external supply to provide backup potential to the internal bq2050 registers when VCC drops below 3.0V. VCC is output on RBI when VCC is above 3.0V. A diode is required to isolate the external supply. Layout Considerations The bq2050 measures the voltage differential between the SR and VSS pins. VOS (the offset voltage at the SR pin) is greatly affected by PC board layout. For optimal results, the PC board layout should follow the strict rule of a single-point ground return. Sharing high-current ground with small signal ground causes undesirable noise on the small signal nodes. Additionally: n Reset The bq2050 can be reset either by removing VCC and grounding the RBI pin for 15 seconds or by writing 0x80 to register 0x39. Temperature The bq2050 internally determines the temperature in 10°C steps centered from approximately -35°C to +85°C. The temperature steps are used to adapt charge and discharge rate compensations, self-discharge counting, and available charge display translation. The temperature range is available over the serial port in 10°C increments as shown in the following table: n The capacitors (C1 and C2) should be placed as close as possible to the VCC and SB pins, respectively, and their paths to VSS should be as short as possible. A high-quality ceramic capacitor of 0.1µ f is recommended for VCC. The sense resistor capacitor should be placed as close as possible to the SR pin. The sense resistor (RS) should be as close as possible to the bq2050. n 4 bq2050 Gas Gauge Operation The operational overview diagram in Figure 2 illustrates the operation of the bq2050. The bq2050 accumulates a measure of charge and discharge currents, as well as an estimation of self-discharge. Charge and discharge currents are temperature and rate compensated, whereas self-discharge is only temperature compensated. The main counter, Nominal Available Capacity (NAC), represents the available battery capacity at any given time. Battery charging increments the NAC register, while battery discharging and self-discharge decrement the NAC register and increment the DCR (Discharge Count Register). The Discharge Count Register (DCR) is used to update the Last Measured Discharge (LMD) register only if a complete battery discharge from full to empty occurs without any partial battery charges. Therefore, the bq2050 adapts its capacity determination based on the actual conditions of discharge. The battery's initial capacity is equal to the Programmed Full Count (PFC) shown in Table 2. Until LMD is updated, NAC counts up to but not beyond this threshold during subsequent charges. This approach allows the gas gauge to be charger-independent and compatible with any type of charge regime. 1. Last Measured Discharge (LMD) or learned battery capacity: LMD is the last measured discharge capacity of the battery. On initialization (application of VCC or battery replacement), LMD = PFC. During subsequent discharges, the LMD is updated with the latest measured capacity in the Discharge Count Register (DCR) representing a discharge from full to below EDV1. A qualified discharge is necessary for a capacity transfer from the DCR to the LMD register. The LMD also serves as the 100% reference threshold used by the relative display mode. Inputs Charge Current Rate and Temperature Compensation Discharge Current Rate and Temperature Compensation Self-Discharge Timer Temperature Compensation + Main Counters and Capacity Reference (LMD) Measured < Discharged (LMD) Last + + Nominal Available Charge (NAC) Discharge Count Qualified Register (DCR) Transfer Temperature Translation Temperature Step, Other Data Outputs Compensated Available Charge LED Display, etc. Serial Port FG205002.eps Figure 2. Operational Overview 5 bq2050 2. Programmed Full Count (PFC) or initial battery capacity: The initial LMD and gas gauge rate values are programmed by using PROG1–PROG4. The bq2050 is configured for a given application by selecting a PFC value from Table 2. The correct PFC may be determined by multiplying the rated battery capacity in mAh by the sense resistor value: Battery capacity (mAh) * sense resistor (Ω ) = PFC (mVh) Selecting a PFC slightly less than the rated capacity provides a conservative capacity reference until the bq2050 “learns” a new capacity reference. Example: Selecting a PFC Value Given: Sense resistor = 0.05Ω Number of cells = 2 Capacity = 1000mAh, Li-Ion battery, coke-anode Current range = 50mA to 1A Relative display mode Serial port only Self-discharge = NAC 512 per day @ 25°C Voltage drop over sense resistor = 2.5mV to 50mV Nominal discharge voltage = 3.6V Therefore: 1000mAh * 0.05Ω = 50mVh Table 1. bq2050 Programming Pin Connection H Z L Note: PROG5 Compensation/ Self-Discharge Table 4/Disabled Table 4/ Table 3/ NAC NAC 512 512 PROG6 NAC on Reset PFC 0 0 DISP Display State LEDs disabled LEDs on when charging LEDs on for 4 sec. PROG5 and PROG6 states are independent. Table 2. bq2050 Programmed Full Count mVh Selections Programmed Full Count (PFC) 49152 45056 40960 36864 33792 30720 27648 25600 22528 PROGx 1 H H H Z Z Z L L L 2 H Z L H Z L H Z L PROG4 = L PROG3 = H SCALE = 1/80 614 563 512 461 422 384 346 320 282 90 PROG4 = Z Units mVh/ count mVh mVh mVh mVh mVh mVh mVh mVh mVh mV PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L SCALE = 1/160 307 282 256 230 211 192 173 160 141 45 SCALE = 1/320 154 141 128 115 106 96.0 86.4 80.0 70.4 22.5 SCALE = 1/640 76.8 70.4 64.0 57.6 53.0 48.0 43.2 40.0 35.2 11.25 SCALE = 1/1280 38.4 35.2 32.0 28.8 26.4 24.0 21.6 20.0 17.6 5.6 SCALE = 1/2560 19.2 17.6 16.0 14.4 13.2 12.0 10.8 10.0 8.8 2.8 VSR equivalent to 2 counts/sec. (nom.) 6 bq2050 Select: PFC = 30720 counts or 48mVh PROG1 = float PROG2 = low PROG3 = high PROG4 = float PROG5 = float PROG6 = float The initial full battery capacity is 48mVh (960mAh) until the bq2050 “learns” a new capacity with a qualified discharge from full to EDV1. 3. Nominal Available Capacity (NAC): NAC counts up during charge to a maximum value of LMD and down during discharge and self-discharge to 0. NAC is reset to 0 on initialization and on the first valid charge following discharge to EDV1. To prevent overstatement of charge during periods of overcharge, NAC stops incrementing when NAC = LMD. 4. Discharge Count Register (DCR): The DCR counts up during discharge independent of NAC and could continue increasing after NAC has decremented to 0. Prior to NAC = 0 (empty battery), both discharge and self-discharge increment the DCR. After NAC = 0, only discharge increments the DCR. The DCR resets to 0 when NAC = LMD. The DCR does not roll over but stops counting when it reaches FFFFh. The DCR value becomes the new LMD value on the first charge after a valid discharge to VEDV1 if: No valid charge initiations (charges greater than 256 NAC counts, where VSRO > VSRQ) occurred during the period between NAC = LMD and EDV1 detected. The self-discharge count is not more than 4096 counts (8% to 18% of PFC, specific percentage threshold determined by PFC). The temperature is ≥ 0°C when the EDV1 level is reached during discharge. The valid discharge flag (VDQ) indicates whether the present discharge is valid for LMD update. 5. Scaled Available Energy (SAE): SAE is useful in determining the available energy within the battery, and may provide a more useful capacity reference in battery chemistries with sloped voltage profiles during discharge. SAE may be converted to a mWh value using the following formula: E(mWh) = (SAEH * 256 + SAEL) * 2.4 ∗ SCALE ∗ (R B1 + R B2 ) R S ∗ R B2 where RB1, RB2 and RS are resistor values in ohms. SCALE is the selected scale from Table 2. SAEH and SAEL are digital values read via DQ. 6. Compensated Available Capacity (CAC) CAC counts similar to NAC, but contains the available capacity compensated for discharge rate and temperature. Charge Counting Charge activity is detected based on a positive voltage on the VSR input. If charge activity is detected, the bq2050 increments NAC at a rate proportional to VSR and, if enabled, activates an LED display. Charge actions increment the NAC after compensation for temperature. The bq2050 determines charge activity sustained at a continuous rate equivalent to VSRO > VSRQ. A valid charge equates to sustained charge activity greater than 256 NAC counts. Once a valid charge is detected, charge counting continues until VSRO (VSR + VOS) falls below VSRQ. VSRQ is 210µ V, and is described in the Digital Magnitude Filter section. Discharge Counting Discharge activity is detected based on a negative voltage on the VSR input. All discharge counts where VSRO < VSRD cause the NAC register to decrement and the DCR to increment. VSRD is -200µ V, and is described in the Digital Magnitude Filter section. Self-Discharge Estimation The bq2050 continuously decrements NAC and increments DCR for self-discharge based on time and temperature. The self-discharge count rate is programmed to be a nominal 1 512 * NAC per day or disabled. This is the rate for a battery whose temperature is between 20°–30°C. The NAC register cannot be decremented below 0. Count Compensations Discharge Compensation Corrections for the rate of discharge, temperature, and anode type are made by adjusting an internal compensation factor. This factor is based on the measured rate of discharge of the battery. Tables 3A and 3B outline the correction factor typically used for graphite anode Li-Ion batteries, and Tables 4A and 4B outline the factors typically used for coke anode Li-Ion batteries. The compensation factor is applied to CAC and is based on discharge rate and temperature. 7 bq2050 Table 3A. Graphite Anode Approximate Discharge Rate < 0.5C ≥ 0.5C Discharge Compensation Factor 1.00 1.05 Charge Compensation The bq2050 applies the following temperature compensation to NAC during charge: Efficiency 100% 95% Temperature < 10°C ≥ 10°C Temperature Compensation Factor 0.95 1.00 Efficiency 95% 100% This compensation applies to both types of Li-Ion cells. Table 3B. Graphite Anode Temperature Compensation Factor 1.00 1.10 1.35 2.50 Self-Discharge Compensation The self-discharge compensation is programmed for a nominal rate of 1 512 * NAC per day. This is the rate for a battery within the 20°C–30°C temperature range. This rate varies across 8 ranges from < 10°C to > 70°C, changing with each higher temperature (approximately 10°C). See Table 5 below: Temperature ≥ 10°C 0°C to 10°C -10°C to 0°C ≤ -10°C Efficiency 100% 90% 74% 40% Table 5. Self-Discharge Compensation Typical Rate Temperature Range < 10°C PROG5 = Z or L NAC NAC 2048 1024 512 256 128 64 32 16 Table 4A. Coke Anode Approximate Discharge Rate 70°C NAC NAC NAC Self-discharge may be disabled by connecting PROG5 = H. Table 4B. Coke Anode Temperature Compensation Factor 1.00 1.25 2.00 8.00 Digital Magnitude Filter The bq2050 has a digital filter to eliminate charge and discharge counting below a set threshold. The bq2050 setting is 200µ V for VSRD and 210µV for VSRQ. Temperature ≥ 10°C 0°C to 10°C -10°C to 0°C ≤ -10°C Efficiency 100% 80% 50% 12% 8 bq2050 Table 6. bq2050 Current-Sensing Errors Symbol INL INR Parameter Integrated non-linearity error Integrated nonrepeatability error Typical ±2 ±1 Maximum ±4 ±2 Units % % Notes Add 0.1% per °C above or below 25°C and 1% per volt above or below 4.25V. Measurement repeatability given similar operating conditions. Error Summary Capacity Inaccurate The LMD is susceptible to error on initialization or if no updates occur. On initialization, the LMD value includes the error between the programmed full capacity and the actual capacity. This error is present until a valid discharge occurs and LMD is updated (see the DCR description on page 7). The other cause of LMD error is battery wear-out. As the battery ages, the measured capacity must be adjusted to account for changes in actual battery capacity. A Capacity Inaccurate counter (CPI) is maintained and incremented each time a valid charge occurs (qualified by NAC; see the CPI register description) and is reset whenever LMD is updated from the DCR. The counter does not wrap around but stops counting at 255. The capacity inaccurate flag (CI) is set if LMD has not been updated following 64 valid charges. eight bits that have a maximum transmission rate of 333 bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. Data input from the bq2050 may be sampled using the pulsewidth capture timers available on some microcontrollers. If a communication error occurs, e.g. tCYCB > 6ms, the bq2050 should be sent a BREAK to reinitiate the serial interface. A BREAK is detected when the DQ pin is driven to a logic-low state for a time, tB or greater. The DQ pin should then be returned to its normal readyhigh logic state for a time, tBR. The bq2050 is now ready to receive a command from the host processor. The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq2050 taking the DQ pin to a logic-low state for a period, tSTRH,B. The next section is the actual data transmission, where the data should be valid by a period, tDSU, after the negative edge used to start communication. The data should be held for a period, tDV, to allow the host or bq2050 to sample the data bit. The final section is used to stop the transmission by returning the DQ pin to a logic-high state by at least a period, tSSU, after the negative edge used to start communication. The final logic-high state should be held until a period, tSV, to allow time to ensure that the bit transmission was stopped properly. The timings for data and break communication are given in the serial communication timing specification and illustration sections. Communication with the bq2050 is always performed with the least-significant bit being transmitted first. Figure 3 shows an example of a communication sequence to read the bq2050 NAC register. Current-Sensing Error Table 5 illustrates the current-sensing error as a function of VSRO. A digital filter eliminates charge and discharge counts to the NAC register when VSRO is between VSRQ and VSRD. Communicating With the bq2050 The bq2050 includes a simple single-pin (DQ plus return) serial data interface. A host processor uses the interface to access various bq2050 registers. Battery characteristics may be easily monitored by adding a single contact to the battery pack. The open-drain DQ pin on the bq2050 should be pulled up by the host system, or may be left floating if the serial interface is not used. The interface uses a command-based protocol, where the host processor sends a command byte to the bq2050. The command directs the bq2050 to either store the next eight bits of data received to a register specified by the command byte or output the eight bits of data specified by the command byte. The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of 9 bq2050 Written by Host to bq2050 CMDR = 03h LSB MSB Received by Host to bq2050 NAC = 65h LSB MSB Break 1 1 0 0 0 0 0 0 DQ 1 0 1 0 011 0 TD205002.eps Figure 3. Typical Communication With the bq2050 bq2050 Registers The bq2050 command and status registers are listed in Table 7 and described below. Primary Status Flags Register (FLGS1) The read-only FLGS1 register (address=01h) contains the primary bq2050 flags. The charge status flag (CHGS) is asserted when a valid charge rate is detected. Charge rate is deemed valid when VSRO > VSRQ. A VSRO of less than VSRQ or discharge activity clears CHGS. The CHGS values are: FLGS1 Bits 7 CHGS 6 5 4 3 2 1 0 - Command Register (CMDR) The write-only CMDR register is accessed when eight valid command bits have been received by the bq2050. The CMDR register contains two fields: n n W/R bit Command address The W/R bit of the command register is used to select whether the received command is for a read or a write function. The W/R values are: CMDR Bits 7 W/R 6 5 4 3 2 1 0 - Where CHGS is: 0 1 Either discharge activity detected or VSRO < VSRQ VSRO > VSRQ Where W/R is: 0 1 The bq2050 outputs the requested register contents specified by the address portion of CMDR. The following eight bits should be written to the register specified by the address portion of CMDR. The battery replaced flag (BRP) is asserted whenever the bq2050 is reset either by application of VCC or by a serial port command. BRP is reset when either a valid charge action increments NAC to be equal to LMD, or a valid charge action is detected after the EDV1 flag is asserted. BRP = 1 signifies that the device has been reset. The BRP values are: FLGS1 Bits 7 6 BRP 5 4 3 2 1 0 - The lower seven-bit field of CMDR contains the address portion of the register to be accessed. Attempts to write to invalid addresses are ignored. CMDR Bits 7 6 5 4 AD4 3 AD3 2 AD2 1 AD1 0 AD0 (LSB) Where BRP is: 0 1 Battery is charged until NAC = LMD or discharged until the EDV1 flag is asserted bq2050 is reset AD6 AD5 10 bq2050 Table 7. bq2050 Command and Status Registers Symbol CMDR Register Name Loc. Read/ Control Field (hex) Write 7(MSB) 6 AD6 00h Write W/R 01h Read 02h Read 03h CHGS TMP3 BRP TMP2 5 AD5 n/u TMP1 4 AD4 CI TMP0 3 AD3 VDQ GG3 2 AD2 n/u GG2 1 AD1 EDV1 GG1 0(LSB) AD0 EDVF GG0 Command register Primary status flags FLGS1 register TMP Temperature register Nominal available caNACH pacity high byte register Nominal available NACL capacity low byte register Battery BATID identification register Last measured disLMD charge register Secondary status FLGS2 flags register Program pin pullPPD down register Program pin pull-up PPU register Capacity CPI inaccurate count register Battery voltage VSB register End-of-discharge threshVTS old select register Compensated availCACH able capacity high byte register Compensated CACL available capacity low byte register Scaled available SAEH energy high byte register Scaled available SAEL energy low byte register RST Reset register Note: n/u = not used R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0 17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0 04h 05h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0 R/W LMD7 n/u n/u n/u CPI7 VSB7 VTS7 LMD6 DR2 n/u n/u CPI6 VSB6 VTS6 LMD5 DR1 PPD6 PPU6 CPI5 VSB5 VTS5 LMD4 DR0 PPD5 PPU5 CPI4 VSB4 VTS4 LMD3 n/u PPD4 PPU4 CPI3 VSB3 VTS3 LMD2 n/u PPD3 PPU3 CPI2 VSB2 VTS2 LMD1 n/u PPD2 PPU2 CPI1 VSB1 VTS1 LMD0 OVLD PPD1 PPU1 CPI0 VSB0 VTS0 06h Read 07h Read 08h Read 09h Read 0Bh Read 0Ch R/W 0Dh Read CACH7 CACH6 CACH5 CACH4 CACH3 CACH2 CACH1 CACH0 0Eh Read CACL7 CACL6 CACL5 CACL4 CACL3 CACL2 CACL1 CACL0 0Fh Read SAEH7 SAEH6 SAEH5 SAEH4 SAEH3 SAEH2 SAEH1 SAEH0 10h Read SAEL7 39h Write RST SAEL6 0 SAEL5 SAEL4 SAEL3 SAEL2 SAEL1 SAEL0 0 0 0 0 0 0 11 bq2050 The capacity inaccurate flag (CI) is used to warn the user that the battery has been charged a substantial number of times since LMD has been updated. The CI flag is asserted on the 64th charge after the last LMD update or when the bq2050 is reset. The flag is cleared after an LMD update. The CI values are: Where EDV1 is: FLGS1 Bits 7 6 5 4 CI 3 2 1 0 0 1 Valid charge action detected, VSB ≥ VTS VSB < VTS providing that the discharge rate is < 2C The EDV1 values are: FLGS1 Bits 7 6 5 4 3 2 1 EDV1 0 - Where CI is: 0 1 When LMD is updated with a valid full discharge After the 64th valid charge action with no LMD updates or the bq2050 is reset The final end-of-discharge warning flag (EDVF) flag is used to warn that battery power is at a failure condition. All segment drivers are turned off. The EDVF flag is latched until a valid charge has been detected. The EDVF threshold is set 50mV below the EDV1 threshold. The EDVF values are: FLGS1 Bits 7 6 5 4 3 2 1 0 EDVF The valid discharge flag (VDQ) is asserted when the bq2050 is discharged from NAC=LMD. The flag remains set until either LMD is updated or one of three actions that can clear VDQ occurs: n The self-discharge count register (SDCR) has exceeded the maximum acceptable value (4096 counts) for an LMD update. A valid charge action sustained at VSRO > VSRQ for at least 256 NAC counts. The EDV1 flag was set at a temperature below 0°C Where EDVF is: 0 1 Valid charge action detected, VSB ≥ (VTS 50mV) VSB < (VTS - 50mV) providing the discharge rate is < 2C n n The VDQ values are: FLGS1 Bits 7 6 5 4 3 VDQ 2 1 0 - Temperature Register (TMP) The read-only TMP register (address=02h) contains the battery temperature. TMP Temperature Bits 7 6 5 4 3 2 1 0 - Where VDQ is: 0 SDCR ≥ 4096, subsequent valid charge action detected, or EDV1 is asserted with the temperature less than 0°C On first discharge after NAC = LMD TMP4 TMP3 TMP2 TMP1 1 The first end-of-discharge warning flag (EDV1) warns the user that the battery is almost empty. The first segment pin, SEG1, is modulated at a 4Hz rate if the display is enabled once EDV1 is asserted, which should warn the user that loss of battery power is imminent. The EDV1 flag is latched until a valid charge has been detected. The EDV1 threshold is externally controlled via the VTS register (see Voltage Threshold Register on this page). The bq2050 contains an internal temperature sensor. The temperature is used to set charge and discharge efficiency factors as well as to adjust the self-discharge coefficient. The temperature register contents may be translated as shown in Table 7. The bq2050 calculates the gas gauge bits, GG3-GG0 as a function of CACH and LMD. The results of the calculation give available capacity in 1 16 increments from 0 to 15 16. 12 bq2050 Table 7. Temperature Register TMP3 0 0 0 0 0 0 0 0 1 1 1 1 1 TMP2 0 0 0 0 1 1 1 1 0 0 0 0 1 TMP1 0 0 1 1 0 0 1 1 0 0 1 1 0 TMP0 0 1 0 1 0 1 0 1 0 1 0 1 0 Temperature T < -30°C -30°C < T < -20°C -20°C < T < -10°C -10°C < T < 0°C 0°C < T < 10°C 10°C < T < 20°C 20°C < T < 30°C 30°C < T < 40°C 40°C < T < 50°C 50°C < T < 60°C 60°C < T < 70°C 70°C < T < 80°C T > 80°C DR2 0 0 0 0 GG0 7 6 5 FLGS2 Bits 4 3 2 1 0 OVLD DR1 0 0 1 DR0 0 1 0 Discharge Rate DRATE < 0.5C 0.5C ≤ DRATE < 2C DRATE ≥ 2C (OVLD = 1) 7 6 DR2 Last Measured Discharge Register (LMD) LMD is a read/write register (address=05h) that the bq2050 uses as a measured full reference. The bq2050 adjusts LMD based on the measured discharge capacity of the battery from full to empty. In this way the bq2050 updates the capacity of the battery. LMD is set to PFC during a bq2050 reset. Secondary Status Flags Register (FLGS2) The read-only FLGS2 register (address=06h) contains the secondary bq2050 flags. FLGS2 Bits 5 4 3 DR1 DR0 2 1 0 The discharge rate flags, DR2–0, are bits 6–4. TMPGG Gas Gauge Bits 7 6 5 4 3 GG3 2 GG2 1 GG1 They are used to determine the current discharge regime as follows: Nominal Available Charge Registers (NACH/NACL) The read/write NACH high-byte register (address=03h) and the read-only NACL low-byte register (address=17h) are the main gas gauging register for the bq2050. The NAC registers are incremented during charge actions and decremented during discharge and self-discharge actions. The correction factors for charge/discharge efficiency are applied automatically to NAC. NACH and NACL are set to 0 during a bq2050 reset. Writing to the NAC registers affects the available charge counts and, therefore, affects the bq2050 gas gauge operation. Do not write the NAC registers to a value greater than LMD. The overload flag (OVLD) is asserted when a discharge rate in excess of 2C is detected. OVLD remains asserted as long as the condition persists and is cleared 0.5 seconds after the rate drops below 2C. The overload condition is used to stop sampling of the battery terminal characteristics for end-of-discharge determination. Program Pin Pull-Down Register (PPD) The read-only PPD register (address=07h) contains some of the programming pin information for the bq2050. The segment drivers, SEG1–6, have a corresponding PPD register location, PPD1–6. A given location is set if a pull-down resistor has been detected on its corresponding segment driver. For example, if SEG1 and SEG4 have pull-down resistors, the contents of PPD are xx001001. Battery Identification Register (BATID) The read/write BATID register (address=04h) is available for use by the system to determine the type of battery pack. The BATID contents are retained as long as VCC is greater than 2V. The contents of BATID have no effect on the operation of the bq2050. There is no default setting for this register. Program Pin Pull-Up Register (PPU) The read-only PPU register (address=08h) contains the rest of the programming pin information for the bq2050. The segment drivers, SEG1–6, have a corresponding PPU register location, PPU1–6. A given location is set if a pull-up resistor has been detected on its corresponding segment 13 bq2050 driver. For example, if SEG3 and SEG6 have pull-up resistors, the contents of PPU are xx100100. 7 PPD/PPU Bits 7 6 5 4 3 2 1 0 6 5 VTS Register Bits 4 3 2 1 0 VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0 PPU6 PPU5 PPU4 PPU3 PPU2 PPU1 PPD6 PPD5 PPD4 PPD3 PPD2 PPD1 Compensated Available Charge Registers (CACH/CACL) The read-only CACH high-byte register (address = 0Dh) and the read-only CACL low-byte register (address = 0Eh) represent the available charge compensated for discharge rate and temperature. CACH and CACL use piece-wise corrections as outlined in Tables 3A, 3B, 4A, and 4B, and will vary as conditions change. The NAC and LMD registers are not affected by the discharge rate and temperature. Capacity Inaccurate Count Register (CPI) The read-only CPI register (address=09h) is used to indicate the number of times a battery has been charged without an LMD update. Because the capacity of a rechargeable battery varies with age and operating conditions, the bq2050 adapts to the changing capacity over time. A complete discharge from full (NAC=LMD) to empty (EDV1=1) is required to perform an LMD update assuming there have been no intervening valid charges, the temperature is greater than or equal to 0°C, and the self-discharge counter is less than 4096 counts. The CPI register is incremented every time a valid charge is detected. When NAC > 0.94 * LMD, however, the CPI register increments on the first valid charge; CPI does not increment again for a valid charge until NAC < 0.94 * LMC. This prevents continuous trickle charging from incrementing CPI if self-discharge decrements NAC. The CPI register increments to 255 without rolling over. When the contents of CPI are incremented to 64, the capacity inaccurate flag, CI, is asserted in the FLGS1 register. The CPI register is reset whenever an update of the LMD register is performed, and the CI flag is also cleared. Scaled Available Energy Registers (SAEH/SAEL) The read-only SAEH high-byte register (address = 0Fh) and the read only SAEL low-byte register (address = 10h) are used to scale battery voltage and CAC to a value which can be translated to watt-hours remaining under the present conditions. SAEL and SAEH may be converted to mWh using the formula on page 7. Reset Register (RST) The reset register (address = 39h) enables a softwarecontrolled reset of the device. By writing the RST register contents from 00h to 80h, a bq2050 reset is performed. Setting any bit other than the most-significant bit of the RST register is not allowed and results in improper operation of the bq2050. Resetting the bq2050 sets the following: n n n Battery Voltage Register (VSB) The read-only battery voltage register is used to read the single-cell battery voltage on the SB pin. The VSB register (address = 0Bh) is updated approximately once per second with the present value of the battery voltage. VSB = 2.4V * (VSB/256). VSB Register Bits 7 6 5 4 3 2 1 0 LMD = PFC CPI, VDQ, NACH, and NACL = 0 CI and BRP = 1 Note: Self-discharge is disabled when PROG5 = H. Display The bq2050 can directly display capacity information using low-power LEDs. If LEDs are used, the program pins should be resistively tied to VCC or VSS for a program high or program low, respectively. The bq2050 displays the battery charge state in relative mode. In relative mode, the battery charge is represented as a percentage of the LMD. Each LED segment represents 20% of the LMD. The capacity display is also adjusted for the present battery temperature. The temperature adjustment reflects the available capacity at a given temperature but does VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0 Voltage Threshold Register (VTS) The end-of-discharge threshold voltages (EDV1 and EDVF) can be set using the VTS register (address = 0Ch). The read/write VTS register sets the EDV1 trip point. EDVF is set 50mV below EDV1. The default value in the VTS register is A2h, representing EDV1 = 1.52V and EDVF = 1.47V. EDV1 = 2.4V * (VTS/256). 14 bq2050 not affect the NAC register. The temperature adjustments are detailed in the CACH and CACL register descriptions. When DISP is tied to VCC, the SEG1–5 outputs are inactive. When DISP is left floating, the display becomes active whenever the bq2050 detects a charge in progress VSRO > VSRQ . When pulled low, the segment outputs become active for a period of four seconds, ± 0.5 seconds. The segment outputs are modulated as two banks, with segments 1, 3, and 5 alternating with segments 2 and 4. The segment outputs are modulated at approximately 100Hz with each segment bank active for 30% of the period. SEG1 blinks at a 4Hz rate whenever VSB has been detected to be below VEDV1 (EDV1 = 1), indicating a lowbattery condition. VSB below VEDVF (EDVF = 1) disables the display output. Microregulator The bq2050 can operate directly from one cell. A micropower source for the bq2050 can be inexpensively built using the FET and an external resistor to accommodate a greater number of cells; see Figure 1. 15 bq2050 Absolute Maximum Ratings Symbol VCC All other pins REF Parameter Relative to VSS Relative to VSS Relative to VSS Minimum -0.3 -0.3 -0.3 Maximum 7.0 7.0 8.5 Unit V V V Current limited by R1 (see Figure 1) Minimum 100Ω series resistor should be used to protect SR in case of a shorted battery (see the bq2050 application note for details). Commercial Industrial Notes VSR Relative to VSS -0.3 7.0 V TOPR Note: Operating temperature 0 -40 70 85 °C °C Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. DC Voltage Thresholds (TA = TOPR; V = 3.0 to 6.5V) Symbol VEDVF VEDV1 VSRO VSRQ VSRD VMCV Note: Parameter Final empty warning First empty warning SR sense range Valid charge Valid discharge Maximum single-cell voltage Minimum 1.44 1.49 -300 210 2.20 Typical 1.47 1.52 2.25 Maximum 1.50 1.55 2000 -200 2.30 Unit V V mV µV µV V SB SB SR, VSR + VOS VSR + VOS (see note) VSR + VOS (see note) SB Notes VOS is affected by PC board layout. Proper layout guidelines should be followed for optimal performance. See “Layout Considerations.” 16 bq2050 DC Electrical Characteristics (TA = TOPR) Symbol VCC VOS VREF RREF ICC VSB RSBmax IDISP ILCOM IRBI RDQ VSR RSR VIH VIL VIZ VOLSL VOLSH VOHLCL VOHLCH IIH IIL IOLS IOL VOL VIHDQ VILDQ RPROG RFLOAT Note: Parameter Supply voltage Offset referred to VSR Reference at 25°C Reference at -40°C to +85°C Reference input impedance Normal operation Battery input SB input impedance DISP input leakage LCOM input leakage RBI data retention current Internal pulldown Sense resistor input SR input impedance Logic input high Logic input low Logic input Z SEGX output low, low VCC SEGX output low, high VCC LCOM output high, low VCC LCOM output high, high VCC PROG1-6 input high current PROG1-6 input low current SEG1-5 sink current Open-drain sink current Open-drain output low DQ input high DQ input low Soft pull-up or pull-down resistor value (for programming) Float state external impedance All voltages relative to VSS. Minimum 3.0 5.7 4.5 2.0 0 10 -0.2 500 -0.3 10 VCC - 0.2 float VCC - 0.3 VCC - 0.6 -33 2.5 Typical 4.25 ±50 6.0 5.0 90 120 170 0.1 0.4 1.2 1.2 5 Maximum 6.5 ±150 6.3 7.5 135 180 250 VCC 5 0.2 100 2.0 VSS + 0.2 float 11.0 5.0 0.5 0.8 200 Unit V µV V V MΩ µA µA µA V MΩ µA µA nA KΩ V MΩ V V V V V V V µA µA mA mA mA V V V KΩ MΩ VSR < VSS = discharge; VSR > VSS = charge -200mV < VSR < VCC PROG1–PROG6 PROG1–PROG6 PROG1–PROG6 VCC = 3V, IOLS ≤ 1.75mA SEG1–SEG5 VCC = 6.5V, IOLS ≤ 11.0mA SEG1–SEG5 VCC = 3V, IOHLCOM = -5.25mA VCC = 6.5V, IOHLCOM = -33.0mA VPROG = VCC/2 VPROG = VCC/2 At VOHLCH = VCC - 0.6V At VOLSH = 0.4V At VOL = VSS + 0.3V DQ IOL ≤ 5mA, DQ DQ DQ PROG1–PROG6 PROG1–PROG6 0 < VSB < VCC VDISP = VSS DISP = VCC VRBI > VCC < 3V Notes VCC excursion from < 2.0V to ≥ 3.0V initializes the unit. DISP = VCC IREF = 5µ A IREF = 5µ A VREF = 3V VCC = 3.0V, DQ = 0 VCC = 4.25V, DQ = 0 VCC = 6.5V, DQ = 0 IOHLCOM LCOM source current 17 bq2050 Serial Communication Timing Specification (TA = TOPR) Symbol tCYCH tCYCB tSTRH tSTRB tDSU tDH tDV tSSU tSH tSV tB tBR Notes: Parameter Cycle time, host to bq2050 Cycle time, bq2050 to host Start hold, host to bq2050 Start hold, bq2050 to host Data setup Data hold Data valid Stop setup Stop hold Stop valid Break Break recovery Minimum 3 3 5 500 750 1.50 700 2.95 3 1 Typical Maximum 6 750 2.25 Unit ms ms ns µs µs µs ms ms µs ms ms ms Notes See note The open-drain DQ pin should be pulled to at least VCC by the host system for proper DQ operation. DQ may be left floating if the serial interface is not used. Serial Communication Timing DQ (R/W "1") DQ (R/W "0") tSTRH tSTRB tDSU tDV tSSU DQ (BREAK) tSV tCYCH, tCYCB, tB tBR tSH tDH TD201002.eps 18 bq2050 16-Pin SOIC Narrow (SN) 16-Pin SN (0.150" SOIC) D e Inches Millimeters Min. 1.52 0.10 0.33 0.18 9.78 3.81 1.14 5.72 0.38 Max. 1.78 0.25 0.51 0.25 10.16 4.06 1.40 6.22 0.89 B Dimension A A1 B C D E Min. 0.060 0.004 0.013 0.007 0.385 0.150 0.045 0.225 0.015 Max. 0.070 0.010 0.020 0.010 0.400 0.160 0.055 0.245 0.035 E H A A1 .004 L C e H L Data Sheet Revision History Change No. 1 Page No. 4 Description Changed reset procedure Was: Is: Nature of Change Reset by issuing command over serial port Reset by removing VCC and grounding RBI for 15 s. Min. was 1.45; Max. was 1.49 Min. now is 1.44; Max. now is 1.50 Min. was 1.50; Min. now is 1.49 Min. was 2.5; Min. now is 3.0 Max. was 150 Max. now is 180 1 2 11, 14 16 Deleted reset register Changed values VEDVF: VEDV1: VCC: VOS: 2 2 2 Notes: 17 Changed values 4, 11, 13, 14 Reinserted reset register 9 Maximum offset Change 1 = June 1995 B changes from Dec. 1994. Change 2 = Sept. 1996 C changes from June 1995 B. 19 bq2050 Ordering Information bq2050 Temperature Range: blank = Commercial (-20 to +70°C) N = Industrial (-40 to +85°C)* Package Option: SN = 16-pin narrow SOIC Device: bq2040 Gas Gauge IC With SMB Interface * Contact factory for availability. 17919 Waterview Parkway Dallas, Texas 75252 Fax: (972) 437-9198 Tel: (972) 437-9195 www.benchmarq.com or www.unitrode.com Copyright © 1996, Unitrode Corporation All rights reserved. No part of this data sheet may be reproduced in any form or means, without express permission from Unitrode. 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