CH1005C

CH7005C CHRONTEL Digital PC to TV Encoder with MacrovisionTM Features • Supports Macrovision TM General Description 7.X anti-copy protection Chrontel’s CH7005 digital PC to TV encoder is a standalone integrated circuit which provides a PC 99 compliant solution for TV output. Suggested application use with the Intel I740.* It provides a universal digital input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts this directly into NTSC or PAL TV format. This circuit integrates a digital NTSC/PAL encoder with 9-bit DAC interface, and new adaptive flicker filter, and high accuracy low-jitter phase locked loop to create outstanding quality video. Through its TrueScaleTM scaling and deflickering engine, the CH7005 supports full vertical and horizontal underscan capability and operates in 5 different resolutions including 640x480 and 800x600. A new universal digital interface along with full programmability make the CH7005 ideal for system-level PC solutions. All features are software programmable through a standard I2C port, to enable a complete PC solution using a TV as the primary display. • Function compatible with CH7004 • Universal digital interface accepts YCrCb (CCIR601 or 656) or RGB (15,16 or 24-bit) video data in both non-interlaced and interlaced formats • TrueScale TM rendering engine supports undescam operations for various graphic resolutions† ¥ • Enhanced text sharpness and adaptive flicker removal with up to 5-lines of filtering † • Enhanced dot crawl control and area reduction • Fully programmable through I2C port • Supports NTSC, NTSC-EIA (Japan), and PAL (B, D, G, H, I, M and N) TV formats • Provides Composite, S-Video and SCART outputs • Auto-detection of TV presence • Supports VBI pass-through • Programmable power management • 9-bit video DAC outputs • Complete Windows and DOS driver software • Offered in 44-pin PLCC, 44-pin TQFP † Patent number 5,781,241 ¥ Patent number 5,914,753 LINE MEMORY YUV-RGB CONVERTER RGB-YUV CONVERTER DIGITAL D[15:0] PIXEL DATA INPUT INTERFACE TRUE SCALE SCALING & DEFLICKERING ENGINE NTSC/PAL ENCODER & FILTERS Y/R TRIPLE DAC C/G CVBS/B SYSTEM CLOCK RSET I2C REGISTER & CONTROL BLOCK PLL TIMING & SYNC GENERATOR SC SD RESET* XCLK H V XI XO/FIN CSYNC P-OUT DS/BCO Figure 1: Functional Block Diagram 201-0000-025 Rev 2.1, 8/2/99 *Intel I740 is a Trademark of Intel Corp 1 CHRONTEL CH7005C DS/BCO 41 P-OUT D GN D 6 5 4 3 2 1 44 43 42 D[3] D[4] D[5] D[6] DVDD D[7] D[8] DGND] D[9] D[10] D[11] 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 40 39 38 37 36 A GN D DVDD XCL K D[2] D[1] D[0] H V XO/FIN XI AVDD DVDD RESET* DGND SC SD VDD RSET GND CHRONTEL CH7005 35 34 33 32 31 30 29 D[12] D[13] D[14] D[15] DVDD CSYNC D GN D GN D CVBS C Figure 2: 44-Pin PLCC 2 Y 201-0000-025 Rev 2.1, 8/2/99 CHRONTEL CH7005C DS/BCO 35 P-OUT D GN D 44 43 42 41 40 39 XCL K D[2] D[1] D[0] 38 37 36 D[3] D[4] D[5] D[6] DVDD D[7] D[8] DGND] D[9] D[10] D[11] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 34 33 32 31 A GN D DVDD H DVDD V XO/FIN XI AVDD DVDD RESET* ADDR DGND SC SD VDD RSET GND CHRONTEL CH7005 30 29 28 27 26 25 24 23 CSYNC D GN D GN D CVBS C D[12] D[13] D[14] Figure 3: 44-Pin TQFP 201-0000-025 Rev 2.1, 8/2/99 D[15] Y 3 CHRONTEL Table 1. Pin Descriptions 44-Pin PLCC 21-15 13-12, 10-4 CH7005C Type In 44-Pin TQFP 15,14, 13,12, 11,10, 9,7,6, 4,3, 2,1, 44,43, 42 37 Symbol D15-D0 Description Digital Pixel Inputs These pins accept digital pixel data streams with either 8, 12, or 16-bit multiplexed or 16-bit non-multiplexed formats, determined by the input mode setting (see Registers and Programming section). Inputs D0 - D7 are used when operating in 8-bit multiplexed mode. Inputs D0 - D11 are used when operating in 12-bit mode. Inputs D0 - D15 are used when operating in 16-bit mode. The data structure and timing sequence for each mode is described in the section on Digital Input Port. Pixel Clock Output The CH7005, operating in master mode, provides a pixel data clocking signal to the VGA controller. This clock will only be provided in master clock modes and will be tri-stated otherwise. This pin provides the pixel clock output signal (adjustable as 1X,2X or 3x) to the VGA controller (see the section on Digital Video Interface, Registers and Programming for more details). The capacitive loading on this pin should be kept to a minimum. Pixel Clock Input To operate in a pure master mode, the P-OUT signal should be connected to the XCLK input pin. To operate in a pseudo-master mode, the P-OUT clock is used as a reference frequency, and a signal locked to this output (at 1X, 1/2X, or 1/3X the P-OUT frequency) is input to the XCLK pin. To operate in slave mode, the CH7005 accepts an external pixel clock input at this pin. The capacitive loading on this pin should be kept to a minimum. Vertical Sync Input/Output This pin accepts the vertical sync signal from the VGA controller, or outputs a vertical sync to the VGA controller. The capacitive loading on this pin should kept to a minimum. Horizontal Sync Input/Output This pin accepts the horizontal sync from the VGA controller, or outputs a horizontal sync to the VGA controller. The capacitive loading on this pin should be kept to a minimum. Data/Start (input) / Buffered Clock (output) When configured as an input, the rising edge of this signal identifies the first active pixel of data for each active line. When configured as an output this pin provides a buffered clock output. The output clock can be selected using the BCO register (17h) (see Registers and Programming). 43 Out P-OUT 1 39 In XCLK 3 41 In/Out V 2 40 In/Out H 41 35 In/Out DS/BCO 38 32 In XI Crystal Input A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached between XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should be connected to ground. Crystal Output or External Fref A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and XI. An external CMOS compatible clock can be connected to XO/FIN as an alternative. 39 33 In XO/FIN 4 201-0000-025 Rev 2.1, 8/2/99 CHRONTEL Table 1. Pin Descriptions 44-Pin PLCC 30 CH7005C Type In 44-Pin TQFP 24 Symbol RSET Description Reference Resistor A 360 Ω resistor with short and wide traces should be attached between RSET and ground. No other connections should be made to this pin. Luminance Output A 75 Ω termination resistor with short traces should be attached between Y and ground for optimum performance. In normal operating modes other than SCART and RGB bypass, this pin outputs the composite video signal. In SCART and RGB Bypass modes, this pin outputs the red signal. Chrominance Output A 75 Ω termination resistor with short traces should be attached between C and ground for optimum performance. In normal operating modes other than SCART and RGB bypass, this pin outputs the composite video signal. In SCART and RGB Bypass modes, this pin outputs the green signal. Composite Video Output A 75 Ω termination resistor with short traces should be attached between CVBS and ground for optimum performance. In normal operating modes other than SCART and RGB bypass, this pin outputs the composite video signal. In SCART and RGB Bypass modes, this pin outputs the blue signal. Composite Sync Output A 75 Ω termination resistor with short traces should be attached between CSYNC and ground for optimum performance. In SCART mode, this pin outputs the composite sync signal. Serial Data (External pull-up required) This pin functions as the serial data pin of the I2C interface port (see the I2C Port Operation section for details). This pin uses the DVDD supply and is not 5V tolerant. Serial Clock (Internal pull-up) This pin functions as the serial clock pin of the I2C interface port (see the I2C Port Operation section for details). This pin uses the DVDD supply and is not 5V tolerant. Reset Input When this pin is low, the CH7005 is held in the power-on reset condition. When this pin is high, the device operates normally and reset is controlled through the I2C register. Analog ground This pin provides the ground reference for the analog section of the CH7005, and MUST be connected to the system ground, to prevent latchup. Refer to the Application Information section for information on proper supply decoupling. Analog Supply Voltage This pins supplies the 5V power to the analog section of the CH7005. DAC Power Supply This pins supplies the 5V power to CH7005’s internal DAC’s. 28 22 Out Y/R 27 21 Out C/G 26 20 Out CVBS/B 23 17 Out CSYNC 32 26 In/Out SD 33 27 In SC 35 29 In Reset* 40 34 Power AGND 37 31 31 25 Power Power AVDD VDD 201-0000-025 Rev 2.1, 8/2/99 5 CHRONTEL Table 1. Pin Descriptions 44-Pin PLCC 29, 25 CH7005C Type Power 44-Pin TQFP 19,23 Symbol GND Description DAC Ground These pins provide the ground reference for CH7005’s internal DACs. For information on proper supply decoupling, please refer to the Application Information section. Digital Supply Voltage These pins supply the 3.3V power to the digital section of CH7005. Digital Ground These pins provide the ground reference for the digital section of CH7005, and MUST be connected to the system ground to prevent latchup. R (Red) Component Output This pin provides the analog Red component of the digital RGB input in the RGB Pass-Through mode. G (Green) Component Output This pin provides the analog Green component of the digital RGB input in the RGB Pass-Through mode. B (Blue) Component Output This pin provides the analog Blue component of the digital RGB input in the RGB Pass-Through mode. 44, 36, 22, 11 42, 34, 24, 14 5,16, 30,38 8,18, 28,36 Power Power DVDD DGND N/A N/A Out R N/A N/A Out G N/A N/A Out B Digital Video Interface The CH7005 digital video interface provides a flexible digital interface between a computer graphics controller and the TV encoder IC, forming the ideal quality/cost configuration for performing the TV-output function. This digital interface consists of up to 16 data signals and 4 control signals, all of which are subject to programmable control through the CH7005 register set. This interface can be configured as 8, 12 or 16-bit inputs operating in either multiplexed mode or 16-bit input operation in demultiplexed mode. It will also accept either YCrCb or RGB (15, 16 or 24-bit) data formats and will accept both non-interlaced and interlaced data formats. A summary of the input data format modes is as follows: Table 2. Input Data Formats Bus Width Transfer Mode Color Space and Depth Format Reference 16-bit 15-bit 16-bit 8-bit 8-bit 8-bit 8-bit 12-bit 12-bit 16-bit Non-multiplexed Non-multiplexed Non-multiplexed 2X-multiplexed 2X-multiplexed 3X-multiplexed 2X-multiplexed 2X-multiplexed 2X-multiplexed 2X-multiplexed RGB 16-bit RGB 15-bit YCrCb (24-bit) RGB 15-bit RGB 16-bit RGB 24-bit YCrCb (24-bit) RGB 24 RGB 24 RGB 24 (32) 5-6-5 each word 5-5-5 each word CbY0,CrY1...(CCIR656 style) 5-5-5 over two bytes 5-6-5 over two bytes 8-8-8 over three bytes Cb,Y0,Cr,Y1,(CCIR656 style) 8-8-8 over two words - ‘C’ version 8-8-8 over two words - ‘I’ version 8-8,8X over two words 6 201-0000-025 Rev 2.1, 8/2/99 CHRONTEL CH7005C The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode. The CH7005 can operate in either master (the CH7004 generates a pixel frequency which is either returned as a phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock). The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X, or 3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7005 will automatically use both clock edges, if a multiplexed data format is selected. Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be selected to be generated by the CH7005. In the case of CCIR656 style input (IDF = 1 or 9), embedded sync may also be used. (In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, time the first value of the (Total Pixels/line x Total Lines/Frame) column of Table 16 on page 31 (Display Mode Register 00H description). The leading edge of the horizontal sync is used to determine the start of each line. The Vertical sync signal must be able to be set to the second value in the (Total Pixels/Line x Total Lines/Frame) column of Table 16 on page 31.) Master Clock Mode: The CH7005 generates a clock signal (output at the P-OUT pin) which will be used by the VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity). Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock signal will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the pixel data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC transmits back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet the specified setup and hold times with respect to the pixel clock. Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after the leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count), plus horizontal sync width, will determine when the chip will begin to sample pixels. Non-multiplexed Mode In the 15/16-bit mode shown in Figure 4, the pixel data bus represents a 15/16-bit non-multiplexed data stream, which contains either RGB or YCrCb formatted data. When operating in RGB mode, each 15/16-bit Pn value will contain a complete pixel encoded in either 5-6-5 or 5-5-5 format. When operating in YCrCb mode, each 16-bit Pn word will contain an 8-bit Y (luminance) value on the upper 8 bits, and an 8-bit C (color difference) value on the lower 8 bits. The color difference will be transmitted at half the data rate of the luminance data, with the sequencebeing set as Cb followed by Cr. The Cb and Cr data will be cosited with the Y value transmitted with the Cb value, with the data sequence described in Table 3. The first active pixel is SAV pixels after the leading edge of horizontal sync, where SAV is a bus-controlled register. 201-0000-025 Rev 2.1, 8/2/99 7 CHRONTEL tHSW HSYNC tHD POut/ XCLK Pixel Data AVR SAV CH7005C tP P1 t tPH t SP1 tPH 1 P0a P0 P0b P1 tSP t tHP1 HP P1a P2 P1b P3 P2a P4 P2b P5 Figure 4: Non-multiplexed Data Transfers When IDF = 1, (YCrCb 16-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the embedded sync will be similar to the CCIR656 convention (not identical, since that convention is for 8-bit data streams), and the first byte of the ‘video timing reference code’ will be assumed to occur when a Cb sample would occur – if the video stream was continuous. This is delineated in Table 4 below. Table 3. YCrCb Non-multiplexed Mode with Embedded Syncs IDF# Format Pixel# Bus Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P1 S[7] S[6] S[5] S[4] S[3] S[2] S[1] S[0] 0 0 0 0 0 0 0 0 P2 Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] 1 YCrCb 16-bit P3 Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] P4 Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P5 Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0] Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P6 Y4[7] Y4[6] Y4[5] Y4[4] Y4[3] Y4[2] Y4[1] Y4[0] Cb4[7] Cb4[6] Cb4[5] Cb4[4] Cb4[3] Cb4[2] Cb4[1] Cb4[0] P7 Y5[7] Y5[6] Y5[5] Y5[4] Y5[3] Y5[2] Y5[1] Y5[0] Cr4[7] Cr4[6] Cr4[5] Cr4[4] Cr4[3] Cr4[2] Cr4[1] Cr4[0] In this mode, the S[7-0] byte contains the following data: S[6] S[5] S[4] = = = F V H = = = 1 during field 2, 0 during field 1 1 during field blanking, 0 elsewhere 1 during EAV (the synchronization reference at the end of active video) 0 during SAV (the synchronization reference at the start of active video) Bits S[7] and S[3-0] are ignored. 8 201-0000-025 Rev 2.1, 8/2/99 CHRONTEL Multiplexed Mode CH7005C Each rising edge (or each rising and falling edge) of the XCLK signal will latch data from the graphics chip. The multiplexed input data formats are shown in Figure 5 and 6. The Pixel Data bus represents an 8, 12, or 16-bit multiplexed data stream, which contains either RGB or YCrCb formatted data. In IDF settings of 2, 4, 5, 7, 8 and 9, the input data rate is 2X PCLK, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel, encoded as shown in the tables below. When IDF = 6, the input data rate is 3X PCLK, and each triplet of Pn values (e.g., P0a, P0b and P0c) will contain a complete pixel, encoded as shown in the tables below. When the input is YCrCb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb, Y, Cr, Y where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples — and the following Y1 byte refers to the next luminance sample, per CCIR656 standards. However, the clock frequency is dependent upon the current mode, (not 27MHz, as specified in CCIR656). tHSW HS tHD XCLK DEC = 0 tP2 tPH2 tSP2 tHP2 XCLK DEC = 1 tSP2 tHP2 tSP2 tHP2 D[15:0] P0a P0b P1a P1b P2a P2b Figure 5: Multiplexed Pixel Data Transfer Mode Table 4. RGB 8-bit Multiplexed Mode IDF# Format Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a G0[2] G0[1] G0[0] B0[4] B0[3] B0[2] B0[1] B0[0] 7 RGB 5-6-5 P0b R0[4] R0[3] R0[2] R0[1] R0[0] G0[5] G0[4] G0[3] P1a G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] P1b R1[4] R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] P0a G0[2] G0[1] G0[0] B0[4] B0[3] B0[2] B0[1] B0[0] 8 RGB 5-5-5 P0b x R0[4] R0[3] R0[2] R0[1] R0[0] G0[4] G0[3] P1a G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] P1b x R1[4] R1[3] R1[2] R1[1] R1[0] G1[4] G1[3] 201-0000-025 Rev 2.1, 8/2/99 9 CHRONTEL Table 5. RGB 12-bit Multiplexed Mode IDF# Format Pixel# Bus Data D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0] 4 12-bit RGB (12-12) P0b R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] G0[7] G0[6] G0[5] G0[4] P1a G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] P1b R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] G1[6] G1[5] G1[4] P0a G0[4] G0[3] G0[2] B0[7] B0[6] B0[5] B0[4] B0[3] G0[0] B0[2] B0[1] B0[0] CH7005C 5 12-bit RGB (12-12) P0b R0[7] R0[6] R0[5] R0[4] R0[3] G0[7] G0[6] G0[5] R0[2] R0[1] R0[0] G0[1] P1a G1[4] G1[3] G1[2] B1[7] B1[6] B1[7] B1[4] B1[3] G1[0] B1[2] B1[1] B1[0] P1b R1[7] R1[6] R1[5] R1[4] R1[3] G1[7] G1[6] G1[5] R1[2] R1[1] R1[0] G1[1] Table 6. RGB 16-bit Muliplexed Mode IDF# Format Pixel# Bus Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a G0[7] G0[6] G0[5] G0[4] G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0] P0b A0[7] A0[6] A0[5] A0[4] A0[3] A0[2] A0[1] A0[0] R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] 2 16-bit RGB (16-8) P1a G1[7] G1[6] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B0[1] B0[0] P1b R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] A1[7] A1[6] A1[5] A1[4] A1[3] A1[2] A1[1] A1[0] Note: The AX[7:0] data is ignored. Table 7. YCrCb Multiplexed Mode IDF# Format Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] P0b Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] P1a Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] 9 YCrCb 8-bit P1b Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] P2a Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0] 10 201-0000-025 Rev 2.1, 8/2/99 CHRONTEL CH7005C When IDF = 9 (YCrCb 8-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the embedded sync will follow the CCIR656 convention, and the first byte of the “video timing reference code” will be assumed to occur when a Cb sample would occur if the video stream was continuous. This is delineated in Table 8 shown below. Table 8. YCrCb Multiplexed Mode with Embedded Syncs IDF# Format Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a FF FF FF FF FF FF FF FF P0b 0 0 0 0 0 0 0 0 P1a 0 0 0 0 0 0 0 0 9 YCrCb 8-bit P1b S[7] S[6] S[5] S[4] S[3] S[2] S[1] S[0] P2a Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0] In this mode the S[7.0} contains the following data: S[6] S[5] S[4] = = = F V H = = = 1 during field 2, 0 during field 1 1 during field blanking, 0 elsewhere 1 during EAV (the synchronization reference at the end of active video) 0 during SAV (the synchronization reference at the start of active video) Bits S[7] and S[3-0] are ignored. tHSW HSYNC tHD POut/ XCLK tSP3 Pixel D[7:0] Data P0a P0b tHP3 P0c P1a P1b P1c tP3 tPH3 Figure 6: Multiplexed Pixel Data Transfer Mode (IDF = 6) Table 9. RGB 8-bit Multiplexed Mode (24-bit Color) IDF# Format Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0] P0b G0[7] G0[6] G0[5] G0[4] G0[3] G0[2] G0[1] G0[0] P0c R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] 6 RGB 8-bit P1a B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] P1b G1[7] G1[6] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] P1c R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] P2a B2[7] B2[6] B2[5] B2[4] B2[3] B2[2] B2[1] B2[0] P2b G2[7] G2[6] G2[5] G2[4] G2[3] G2[2] G2[1] G2[0] P2c R2(7) R2(6) R2(5) R2(4) R2(3) R2(2) R2(1) R2(0) 201-0000-025 Rev 2.1, 8/2/99 11 CHRONTEL Functional Description CH7005C The CH7005 is a TV-output companion chip to graphics controllers providing digital output in either YUV or RGB format. This solution involves both hardware and software elements which work together to produce an optimum TV screen image based on the original computer generated pixel data. All essential circuitry for this conversion are integrated onchip. Onchip circuitry includes memory, memory control, scaling, PLL, DAC, filters, and NTSC/PAL encoder. All internal signal processing, including NTSC/PAL encoding, is performed using digital techniques to ensure that the high-quality video signals are not affected by drift issues associated with analog components. No additional adjustment is required during manufacturing. CH7005 is ideal for PC motherboards, web browsers, or VGA add-in boards where a minimum of discrete support components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation. Architectural Overview The CH7005 is a complete TV output subsystem which uses both hardware and software elements to produce an image on TV which is virtually identical to the image that would be displayed on a monitor. Simply creating a compatible TV output from a VGA input involves a relatively straightforward process. This process includes a standard conversion from RGB to YUV color space, converting from a non-interlaced to an interlaced frame sequence, and encoding the pixel stream into NTSC or PAL compliant format. However, creating an optimum computer-generated image on a TV screen involves a highly sophisticated process of scaling, deflickering, and filtering. This results in a compatible TV output that displays a sharp and subtle image, of the right size, with minimal artifacts from the conversion process. As a key part of the overall system solution, the CH7005 software establishes the correct framework for the VGA input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600), the CH7005 software may be invoked to establish the appropriate TV output display. The software then programs the various timing parameters of the VGA controller to create an output signal that will be compatible with the chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates, total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7005 can render a superior TV image without the added cost of a full frame buffer memory – normally used to implement features such as scaling and full synchronization. The CH7005 hardware accepts digital RGB or YCrCb inputs, which are latched in synchronization with the pixel clock. These inputs are then color-space converted into YUV in 4-2-2 format, and stored in a line buffer memory. The stored pixels are fed into a block where scan-rate conversion, underscan scaling and 2-line, 3-line, 4-line and 5line vertical flicker filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to either NTSC or PAL scan rates; the vertical flicker filter eliminates flicker at the output while the underscan scaling reduces the size of the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through digital filters to minimize aliasing problems. The digital encoder receives the filtered signals and transforms them to composite and S-Video outputs, which are converted by the three 9-bit DACs into analog outputs. Color Burst Generation* The CH7005 allows the subcarrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving the subcarrier frequency independent of the sampling rate. As a result, the CH7005 may be used with any VGA chip (with an appropriate digital interface) since the CH7005 subcarrier frequency can be generated without being dependent on the precise pixel rates of VGA controllers. This feature is a significant benefit, since even a ± 0.01% subcarrier frequency variation may be enough to cause some television monitors to lose color lock. In addition, the CH7005 has the capability to genlock the color burst signal to the VGA horizontal sync frequency, which enables a fully synchronous system between the graphics controller and the television. When genlocked, the CH7005 can also stop “dot crawl” motion (for composite mode operation in NTSC modes) to eliminate the annoyance of moving borders. Both of these features are under programmable control through the register set. Display Modes The CH7005 display mode is controlled by three independent factors: input resolution, TV format, and scale factor, which are programmed via the display mode register. It is designed to accept input resolutions of 640x480, 800x600, 640x400 (including 320x200 scan-doubled output), 720x400, and 512x384. 12 * Patent number 5,874,846 201-0000-025 Rev 2.1, 8/2/99 CHRONTEL Display Modes (continued) CH7005C It is disigned to support output to either NTSC or PAL television formats. The CH7005 provides interpolated scaling with selectable factors of 5:4, 1:1, 7:8, 5:6, 3:4 and 7:10 in order to support adjustable overscan or underscan operation when displayed on a TV. This combination of factors results in a matrix of useful operating modes which are listed in detail in Table 10. Table 10. CH7005 Display Modes TV Format Standard NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL Input (active) Resolution 640x480 640x480 640x480 800x600 800x600 800x600 640x400 640x400 640x400 720x400 720x400 512x384 512x384 640x480 640x480 640x480 800x600 800x600 800x600 640x400 640x400 720x400 720x400 512x384 512x384 Scale Factor 1:1 7:8 5:6 5:6 3:4 7:10 5:4 1:1 7:8 5:4 1:1 5:4 1:1 5:4 1:1 5:6 1:1 5:6 3:4 5:4 1:1 5:4 1:1 5:4 1:1 Active TV Lines 480 420 400 500 450 420 500 400 350 500 400 480 384 600 480 400 600 500 450 500 400 500 400 480 384 Percent (1) Overscan 10% (3%) (8%) 16% 4% (3%) 16% (8%) (19%) 16% (8%) 10% (11%) 14% (8%) (29%) 14% (4%) (15%) (4%) (29%) (4%) (29%) (8%) (35%) Pixel Clock 24.671 28.196 30.210 39.273 43.636 47.832 21.147 26.434 30.210 23.790 29.455 20.140 24.671 21.000 26.250 31.500 29.500 36.000 39.000 25.000 31.500 28.125 34.875 21.000 26.250 Horizontal Total 784 784 800 1040 1040 1064 840 840 840 945 936 800 784 840 840 840 944 960 936 1000 1008 1125 1116 840 840 Vertical Total 525 600 630 630 700 750 420 525 600 420 525 420 525 500 625 750 625 750 836 500 625 500 625 500 625 (1) Note:Percent underscan is a calculated value based on average viewable lines on each TV format, assuming an average TV overscan of 10%. (Negative values) indicate modes which are operating in underscan. For NTSC: 480 active lines - 10% (overscan) = 432 viewable lines (average) For PAL: 576 active lines - 10% (overscan) = 518 viewable lines (average) The inclusion of multiple levels of scaling for each resolution have been created to enable optimal use of the CH7005 for different application needs. In general, underscan (modes where percent overscan is negative provides an image that is viewable in its entirety on screen; it should be used as the default for most applications (e.g., viewing text screens, operating games, running productivity applications and working within Windows). Overscanning provides an image that extends past the edges of the TV screen, exactly like normal television programs and movies appear on TV, and is only recommended for viewing movies or video clips coming from the computer. In addition to the above mode table, the CH7005 also support interlaced input modes, both in CCIR 656 and proprietary formats (see Display Mode Register section.) Flicker Filter and Text Enhancement The CH7005 integrates an advanced 2-line, 3-line, 4-line and 5-line (depending on mode) vertical deflickering filter circuit to help eliminate the flicker associated with interlaced displays. This flicker circuit provides an adaptive filter algorithm for implementing flicker reduction with selections of high, medium or low flicker content for both luma and chroma channels (see register descriptions). In addition, a special text enhancement circuit incorporates 201-0000-025 Rev 2.1, 8/2/99 13 CHRONTEL Display Modes (continued) CH7005C additional filtering for enhancing the readability of text. These modes are fully programmable via I2C under the flicker filter register. Internal Voltage Reference An onchip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a reference resistor at pin RSET, and register controlled divider, sets the output ranges of the DACs. The CH7005 bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal (for PAL or NTSC-J), which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor RSET is 360 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for DAC output is 1/48th. Therefore, for each DAC, the current output per LSB step is determined by the following equation: ILSB = V(RSET)/RSET reference resistor * 1/GAIN For DACG=0, this is: ILSB = 1.235/360 * 1/48 = 71.4 µA (nominal) For DACG=1, this is: ILSB = 1.317/360 * 1/48 = 76.2 µA (nominal) Power Management The CH7005 supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off, and Composite Off to provide optimal power consumption for the application involved. Using the programmable power down modes accessed over the I2C port, the CH7005 may be placed in either Normal state, or any of the four power managed states, as listed below (see “Power Management Register” under the Register Descriptions section for programming information). To support power management, a TV sensing function (see “Connection Detect Register” under the Register Descriptions section) is provided, which identifies whether a TV is connected to either S-Video or composite. This sensing function can then be used to enter into the appropriate operating state (e.g., if TV is sensed only on composite, the S-Video Off mode could be set by software). Table 11. Power Management Operating State Normal (On): Power Down: Functional Description In the normal operating state, all functions and pins are active In the power-down state, most pins and circuitry are disabled.The DS/BCO pin will continue to provide either the VCO divided by K3, or 14.318 MHz out when selected as an output, and the P-OUT pin will continue to output a clock reference when in master clock mode. Power is shut off to the unused DACs associated with S-Video outputs. In Composite-off state, power is shut off to the unused DAC associated with CVBS output. In this power-down state, all but the I2C circuits are disabled. This places the CH7005 in its lowest power consumption mode. S-Video Off: Composite Off: Full Power Down: Luminance and Chrominance Filter Options The CH7005 contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and SVideo outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown, the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and chrominance video bandwidth output is shown in Table 12. MacrovisionTM Anti-copy Protection The CH7005 implements the Macrovision 7.X anti-copy protection process. This process changes the encoded output of the NTSC/PAL signals to inhibit recording on VCR devices while not affecting viewing on a TV. The parameters that control this process are fully programmable and can be described by Chrontel only after a suitable Non-Disclosure Agreement has been executed between MacrovisionTM, Inc. and the customer. 14 201-0000-025 Rev 2.1, 8/2/99 CHRONTEL VBI Pass-Through Support CH7005C The CH7005 provides the ability to pass-through data with minimal filtering, on vertical blanking lines 10-21 for Intercast or close captioned applications (see register descriptions). Table 12. Video Bandwidth Mode Chrominance CVBS 00 0.62 0.78 0.53 0.65 0.83 1.03 0.70 0.87 0.74 0.93 0.63 0.78 0.89 0.62 0.78 0.93 0.64 0.74 0.79 0.77 0.95 1.02 0.77 0.86 0.94 0.71 0.71 0.47 0.38 Luminance Bandwidth with Sin(X) /X (MHz) S-Video 1 3.37 4.21 2.87 3.52 4.51 5.59 3.81 4.72 4.01 5.05 3.39 4.24 4.84 3.37 4.21 5.05 3.50 4.02 4.31 4.20 5.13 5.56 4.20 4.66 5.11 3.85 3.85 2.53 2.04 YSV[1:0], YPEAK 00 01 2.26 3.37 2.82 4.21 1.93 2.87 2.36 3.52 3.03 4.51 3.75 5.59 2.56 3.81 3.17 4.72 2.69 4.01 3.39 5.05 2.28 3.39 2.84 4.24 3.25 4.84 2.26 3.37 2.82 4.21 3.39 5.05 2.35 3.50 2.70 4.02 2.89 4.31 2.82 4.20 3.44 5.13 3.73 5.56 2.82 4.20 3.13 4.66 3.43 5.11 2.58 3.85 2.58 3.85 1.70 2.53 1.37 2.04 =0 1X 5.23 6.53 4.46 5.46 7.00 8.68 5.92 7.33 6.22 7.84 5.26 6.58 7.52 5.23 6.53 7.84 5.43 6.24 6.68 6.53 7.97 8.63 6.52 7.24 7.94 5.97 5.97 3.92 3.17 S-Video YSV[1:0], YPEAK = 1 00 01 1X 2.57 4.44 5.23 3.21 5.56 6.53 2.19 3.79 4.46 2.68 4.64 5.46 3.44 5.95 7.00 4.27 7.38 8.68 2.91 5.04 5.92 3.60 6.23 7.33 3.06 5.29 6.22 3.85 6.67 7.84 2.59 4.48 5.26 3.23 5.59 6.58 3.70 6.39 7.52 2.57 4.44 5.23 3.21 5.56 6.53 3.85 6.67 7.84 2.67 4.62 5.43 3.07 5.30 6.24 3.29 5.68 6.68 3.21 5.55 6.53 3.92 6.77 7.97 4.24 7.34 8.63 3.20 5.54 6.52 3.56 6.16 7.24 3.90 6.75 7.94 2.94 5.08 5.97 2.94 5.08 5.97 1.93 3.34 3.92 1.56 2.69 3.17 YCV 0 2.26 2.82 1.93 2.36 3.03 3.75 2.56 3.17 2.69 3.39 2.28 2.84 3.25 2.26 2.82 3.39 2.35 2.70 2.89 2.82 3.44 3.73 2.82 3.13 3.43 2.58 2.58 1.70 1.37 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CBW[1:0] 01 10 0.68 0.80 0.85 1.00 0.58 0.68 0.71 0.83 0.91 1.07 1.13 1.32 0.77 0.90 0.95 1.12 0.81 0.95 1.02 1.20 0.68 0.80 0.86 1.00 0.98 1.15 0.68 0.80 0.85 1.00 1.02 1.20 0.71 0.83 0.81 0.95 0.87 1.02 0.85 1.00 1.03 1.22 1.12 1.32 0.85 0.99 0.94 1.11 1.03 1.21 0.78 0.91 0.78 0.91 0.51 0.60 0.41 0.48 11 0.95 1.18 0.81 0.99 1.27 1.57 1.07 1.33 1.13 1.42 0.95 1.19 1.36 0.95 1.18 1.42 0.98 1.13 1.21 1.18 1.44 1.56 1.18 1.31 1.44 1.08 1.08 0.71 0.57 The composite luminance and chrominance frequency response is depicted in Figures 7 through 9. 201-0000-025 Rev 2.1, 8/2/99 15 CHRONTEL Luminance and Chrominance Filter Options (continued) 0 0 CH7005C -6 6 -12 12 -18 18 (YCVdB YCVdB nn ) -24 24 -30 30 -36 36 -42 42 0 0 1 1 22 3 3 4 4 55 fn,i f 6 6 n,i 7 7 8 8 9 9 10 10 11 11 12 12 106 10 6 Figure 7: Composite Luminance Frequency Response (YCV = 0) 0 -6 -12 -18 (YSVdB YSVdB )n -24 -30 -36 -42 0 1 2 3 4 5 6 f n, i 6 10 7 8 9 10 11 12 Figure 8: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = 0) 16 201-0000-025 Rev 2.1, 8/2/99 CHRONTEL Luminance and Chrominance Filter Options (continued) CH7005C 0 0 6 -6 -12 12 18 -18 (UVfirdB)n 24 -24 UVfirdB n 30 -30 36 -36 42 -42 00 1 1 2 2 3 4 4 5 5 6 6 f fn,i , i n 7 7 8 8 9 9 10 10 11 11 12 12 1066 10 Figure 9: Chrominance Frequency Response 201-0000-025 Rev 2.1, 8/2/99 17 CHRONTEL NTSC and PAL Operation CH7005C Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to characterize these outputs are listed in Table 13 and shown in Figure 10. (See Figure 13 through 18 for illustrations of composite and S-Video output waveforms.) CCIR624-3 Compliance The CH7005 is predominantly compliant with the recommendations called out in CCIR624-3. The following are the only exceptions to this compliance: • The frequencies of Fsc, Fh, and Fv can only be guaranteed in master or pseudo-master modes, not in slave mode when the graphics device generates these frequencies. • It is assumed that gamma correction, if required, is performed in the graphics device which establishes the color reference signals. • All modes provide the exact number of lines called out for NTSC and PAL modes respectively, except mode 21, which outputs 800x600 resolution, scaled by 3:4, to PAL format with a total of 627 lines (vs. 625). • Chroma signal frequency response will fall within 10% of the exact recommended value. • Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to approximate CCIR624-3 requirements, but will fall into a range of values due to the variety of clock frequencies used to support multiple operating modes Table 13. NTSC/PAL Composite Output Timing Parameters (in µS) Symbol Description NTSC A B C D E F G H Front Porch Horizontal Sync Breezeway Color Burst Back Porch Black Active Video Black 287 0 287 287 287 340 340 340 Level (mV) PAL 300 0 300 300 300 300 300 300 Duration (uS) NTSC 1.49 - 1.51 4.69 - 4.72 0.59 - 0.61 2.50 - 2.53 1.55 - 1.61 0.00 - 7.50 37.66 - 52.67 0.00 - 7.50 PAL 1.48 - 1.51 4.69 - 4.71 0.88 - 0.92 2.24 - 2.26 2.62 - 2.71 0.00 - 8.67 34.68 - 52.01 0.00 - 8.67 For this table and all subsequent figures, key values are: Note: 1. 2. 3. 4. RSET = 360 ohms; V(RSET) = 1.235V; 75 ohms doubly terminated load. Durations vary slightly in different modes due to the different clock frequencies used. Active video and black (F, G, H) times vary greatly due to different scaling ratios used in different modes. Black times (F and H) vary with position controls. 18 201-0000-025 Rev 2.1, 8/2/99 CHRONTEL CH7005C A B C D E F G H Figure 10: NTSC / PAL Composite Output START START OF O F VS NC V YN SY C A AL G N StartA N L O of A O G field FIELD 1 1 FIELD 1 523 520 520 524 521 521 525 522 522 523 523 1 524 524 2 3 525 525 1 1 4 2 2 5 36 3 4 4 7 58 5 9 6 6 10 7 7 11 8 8 12 9 9 Pre-equalizing pulse interval Vertical sync pulse interval Post-equalizing pulse interval Reference Line AN LO phase A AL G NA O vertical sub-carrierG FIELD 1 FIELD 2 t1+V interval color field 2 261 258 258 262 259 259 263 260 260 264 261 261 Start of field 2 265 262 262 266 263 263 267 264 264 268 265 265 269 266 266 270 267 267 271 268 268 272 269 269 273 270 270 274 271 271 275 272 272 Reference A AO NL G sub-carrier phase FIELD 1 t2+V color field 2 START O F VYC SN 523 520 524 521 525 522 523 1 Start of field 3 2 524 525 3 4 1 5 2 6 3 7 4 8 5 9 6 10 7 11 8 12 9 Reference G A AO NL sub-carrier phase FIELD 2 t3+V color field 3 261 258 262 259 263 260 264 261 Start of field 4 262 265 266 263 264 267 265 268 269 266 270 267 268 271 272 269 273 270 274 271 272 275 Reference sub-carrier phase color field 4 Figure 11: Interlaced NTSC Video Timing 201-0000-025 Rev 2.1, 8/2/99 19 CHRONTEL SA T TR O F VYC SN A AO NL G FIELD 1 CH7005C 620 620 621 621 622 622 623 623 624 625 1 2 3 4 5 6 6 7 7 8 8 9 9 10 10 A AO NL G FIELD 2 308 308 309 309 310 310 311 311 312 313 314 315 316 317 318 318 319 319 320 320 321 321 322 322 323 323 A AO NL G FIELD 3 620 620 621 621 622 622 623 623 624 625 1 2 3 4 5 6 6 7 7 8 8 9 9 10 10 A AO NL G FIELD 4 308 308 309 309 310 310 311 311 312 313 314 315 316 317 318 318 319 319 320 320 321 321 322 322 323 323 B RS BU ST UR T B AN I G BL NKN LA KI G N INTERVALS 4 3S B RS P AS = R FE EN E P A E = 1 5 ° EL TI E T U H 35 ° LA IV O BU ST PH SE = RE ER NC P A E = 13 RE ATVE TO U UR T HA E EF RE CE H S R P L S IT H = 0 + C MP N N ET PA SWTC = 0, +V CO PO E T AL WI CH , V OM ON N 2 B RS P AS = R FE E CE P AS +9 ° 2 5 R LA IV T U E C 1 A E 0 = 25 ° EL TI E O H ° BU ST PH SE = RE ER N E PH SE+90 ° 22 RE ATVE TO U UR T HA E EF R N = P L S IT H = 1 -V C MP N N ET PA SWTC = 1, -V CO PO E T AL WI CH , OM ON N Figure 12: Interlaced PAL Video Timing 20 201-0000-025 Rev 2.1, 8/2/99 CHRONTEL CH7005C B lack Blue Red Magenta Green Cyan Yellow White Color/Level White Yellow mA 26.66 24.66 V 1.000 0.925 Color bars: Cyan Green Magenta Red Blue Black Blank 21.37 19.37 16.22 14.22 11.08 9.08 7.65 0.801 0.726 0.608 0.533 0.415 0.340 0.287 Sync 0.00 0.000 Figure 13: NTSC Y (Luminance) Output Waveform (DACG = 0) Blue Re d Magenta Green Cyan Yellow White Black Color/Level White Yellow mA 26.75 24.62 V 1.003 0.923 Color bars: Cyan Green Magenta Red Blue Blank/ Black 21.11 18.98 15.62 13.49 10.14 8.00 0.792 0.712 0.586 0.506 0.380 0.300 Sync 0.00 0.000 Figure 14: PAL Y (Luminance) Video Output Waveform (DACG = 1) 201-0000-025 Rev 2.1, 8/2/99 21 CHRONTEL CH7005C Magenta Yellow Green White Black Cyan Color bars: Color/Level Cyan/Red Green/Magenta mA 25.80 25.01 V 0.968 0.938 Blue Re d Yellow/Blue 22.44 0.842 Peak Burst Blank Peak Burst 18.08 14.29 10.51 0.678 0.536 0.394 3.579545 MHz Color Burst (9 cycles) Yellow/Blue 6.15 0.230 Green/Magenta Cyan/Red 3.57 2.79 0.134 0.105 Figure 15: NTSC C (Chrominance) Video Output Waveform (DACG = 0) Magenta Yellow Green White Black Cyan Color bars: Color/Level Cyan/Red Green/Magenta mA 27.51 26.68 V 1.032 1.000 Blue Re d Yellow/Blue 23.93 0.897 Peak Burst Blank Peak Burst 19.21 15.24 11.28 0.720 0.572 0.423 4.433619 MHz Color Burst (10 cycles) Yellow/Blue 6.56 0.246 Green/Magenta Cyan/Red 3.81 2.97 0.143 0.111 Figure 16: PAL C (Chrominance) Video Output Waveform (DACG = 1) 22 201-0000-025 Rev 2.1, 8/2/99 CHRONTEL CH7005C Magent a Yellow Green White Black Cyan Blue Re d Color/Level Peak Chrome White mA 32.88 26.66 V 1.233 1.000 Color bars: Peak Burst Black Blank 11.44 9.08 7.65 0.429 0.340 0.281 Peak Burst 4.45 0.145 3.579545 MHz Color Burst (9 cycles) Sync 0.00 0.000 Figure 17: Composite NTSC Video Output Waveform (DACG = 0) Magenta Yellow Green White Black Cyan Blue Red Color/Level mA V 1.249 1.003 Color bars: Peak Chrome 33.31 White 26.75 Peak Burst 11.97 0.449 Blank/Black 8.00 0.300 Peak Burst 4.04 0.151 Sync 0.00 0.000 4.433619 MHz Color Burst (10 cycles) Figure 18: Composite PAL Video Output Waveform (DACG = 1) 201-0000-025 Rev 2.1, 8/2/99 23 CHRONTEL I2C Port Operation CH7005C The CH7005 contains a standard I2C control port, through which the control registers can be written and read. This port is comprised of a two-wire serial interface, pins SD (bidirectional) and SC, which can be connected directly to the SDB and SCB buses as shown in Figure 19. The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in Figure 19). The CH7005 acts as a slave, and generation of clock signals on the bus is always the responsibility of the master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred up to 400 kbit/s. +DVDD RP SDB (Serial Data Bus) SCB (Serial Clock Bus) SC DATAN2 OUT MASTER SCLK OUT FROM MASTER SD DATAN2 OUT DATAN2 OUT DATA IN MASTER BUS MASTER SCLK IN1 SLAVE DATA IN1 SCLK IN2 SLAVE DATA IN2 Figure 19: Connection of Devices to the Bus Electrical Characteristics for Bus Devices The electrical specifications of the bus devices’ inputs and outputs and the characteristics of the bus lines connected to them are shown in Figure 19. A pull-up resistor (RP) must be connected to a 3.3V ± 10% supply. The CH7005 is a device with input levels related to DVDD. Maximum and minimum values of pull-up resistor (R P) The value of RP depends on the following parameters: • Supply voltage • Bus capacitance • Number of devices connected (input current + leakage current = Iinput) The supply voltage limits the minimum value of resistor R P due to the specified minimum sink current of 2mA at VOLmax = 0.4 V for the output stages: RP >= (VDD – 0.4) / 2 (RP in kΩ) The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of RP due to the specified rise time. The equation for RP is shown below: RP