CH7202

CH7202 CHRONTEL MPEG to TV Encoder with 8-bit Input Features • Outputs NTSC, PAL (B,D,G,H,I) and PAL-M (NTSCJ or PAL-60 available as options) • 8-bit YCrCb (4:2:2) input format • Master or slave mode operation • Triple 9-bit DAC for composite and S-video output • 27 MHz DAC operating frequency eliminates the need for 1/sinc(x) correction filter • Low-jitter phase-locked loop circuitry operates using a low-cost 14.31818 MHz crystal • 40.5 or 33.9 MHz video decoder clock output • 16.934 or 11.289 MHz audio decoder clock output • 13.5 MHz and 27 MHz video pixel clock outputs • Internal 4.6 MHz (m ax) luminance and 1.3 MHz chrom inance filters • Sub-carrier genlocked to HSYNC* and VSYNC* • Sleep mode • CMOS technology in 44-pin PLCC • 5V single-supply operation Description The CH7202 video encoder integrates a dual PLL clock generator and a digital NTSC/PAL video encoder. By generating all essential clock signals for MPEG playback, and converting digital video inputs to either NTSC or PAL video signals, the CH7202 is an essential component of any low-cost solution for video-CD playback machines. The CH7202 dual PLL clock synthesizer generates all clocks and timing signals from a 14.31818 MHz reference crystal (see application note 19 “Tuning Clock Outputs” for selection and tuning of the 14.31818 MHz crystal). The CH7202 will accept HSYNC*, VSYNC*, and 2XPCLK clock inputs during slave mode operation. Timing signals from the PLLs can be used to generate the horizontal and vertical sync signals which enable operating the CH7202 in master mode. The fully digital video encoder is pin-programmable to generate either a 525-line NTSC or a 625-line PAL compatible video signal. It also features a logic selectable sleep mode which turns the encoder off while leaving both PLL’s running. MOD 0 MOD 1 FS YCSWAP C bSWAP VDD AVDD R SET M/S* IREF BL AN KING H ,V SYNC GEN ERATO R Y FILTER M U X DAC Y YC[7 :0], 8 I NTE RFACE L INE AR INTE RP OLATO R Σ U FILTER M U X DAC C VBS H SYNC* VSYNC* S TAT E M ACHI NE X Σ DAC C PCLK 2XPC LK 1/2 V FILTER PLL1 DCLK M U X X S IN + COSINE GENERATOR B LA NKIN G AC LK PLL2 OSC COL O R-B URST CO NT RO L XI XO/FIN GN D A GN D Figure 1: Functional Block Diagram 201-0000-030 Rev 2.0, 6/2/99 1 CHRONTEL CH7202 2XPCLK XO/FIN AGND ACLK DCLK 41 AVDD GND 6 5 4 3 2 1 44 43 42 YCSWAP FS MOD1 CbSWAP YC[7] YC[6] YC[5] YC[4] YC[3] YC[2] YC[1] 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 40 39 38 37 36 GND VDD VDD XI PCLK MOD0 VSYNC* VDD HSYNC* GND GND Y CVBS C AVDD CHRONTEL CH7202 35 34 33 32 31 30 29 M/S* Figure 2: CH7202 Pinout Diagram 2 AGND RSET NC NC NC NC NC NC YC[0] NC 201-0000-030 Rev 2.0, 6/2/99 CHRONTEL Table 1. Pin Descriptions Pin 1 Type Out S ymbol ACLK Description CH7202 Audio Decoder Clock Output 16.934 MHz or 11.289 MHz clock output (selectable by FS) for MPEG audio decoder operation. The output swing is 5V. Digital Supply Voltage These pins supply the 5V power to the digital section of the CH7202. Crystal Output or External F REF Input 1 A parallel resonance 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and XI. An external CMOS compatible clock can be connected to XO/FIN as an alternative. Crystal Input 1 A parallel resonance 14.31818 MHz ( ± 50 ppm) crystal should be attached between XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should be connected to ground. Analog ground These pins provide the ground reference for the analog section of the CH7202. These pins MUST be connected to the system ground to prevent latchup. Analog Supply Voltage These pins supply the 5V power to the analog section of the CH7202. Luma/Chroma Swap. Internally pulled-up. YCSWAP=0 indicates a luminance sample is the first sample following the leading edge of HSYNC*. YCSWAP=1 indicates a chroma sample (Cb or CR depending on CbSWAP) is the first sample following the leading edge of HSYNC*. See F igure 5 on page 7. Frequency Select. Internally pulled-up FS = 1 (default), then DCLK = 40.5 MHz, ACLK = 16.934 MHz FS = 0, then DCLK = 33.9 MHz, ACLK = 11.289 MHz Mode bit 1 - I nternally pulled-up This input works in conjunction with the MOD0 input to select NTSC, PAL, or Sleep mode functions. Refer to Table 3, “Video Encoder Modes,” on page 6 f or details. Cb/Cr Swap. Internally pulled-up When CbSWAP=0, the first chroma sample following the leading edge of HSYNC* will be a Cb sample. When CbSWAP=1, the first chroma sample following the leading edge of HSYNC* will be a Cr sample. See Figure 5 on page 7 Video Input These pins accept the YCrCb data in CCIR656 (4:2:2) digital video format. The sequence of the Y, Cb, Cr data is defined by the YCSWAP and CbSWAP pins. For more details, please refer to the timing diagram shown in F igure 5 on page 7. Y has a nominal range of 16–235. Cb & Cr have a nominal range of 16–240, with 128 equal to zero. 2, 36, 42 Power VDD 3 In XO/FIN 4 In XI 5, 27 Power AGND 6,29 Power AVDD 7 In YCSWAP 8 In FS 9 In MOD1 10 In CbSWAP 11 – 18 In YC[7:0] Note: 1. Please refer to crystal manufacturer specifications for proper load capacitances. The optional variable tuning capacitor is required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance value for the tuning capacitor should be obtained from the crystal manufacturer. For further information, request a copy of Application Note AN-19, “Tuning Clock Outputs.” 201-0000-030 Rev 2.0, 6/2/99 3 CHRONTEL Table 2. Pin Descriptions (continued) Pin 26 Type In Symbol M/S* Description Master/Slave* I nternally pulled-up. M/S*=1 then the CH7202 operates in master mode. M/S*=0, then the CH7202 operates in slave mode. No Connect CH7202 19-25 28 In In NC RSET Reference Resistor A 360 Ω resistor with short and wide traces should be attached between RSET and ground. No other connections should be made to this pin. Chrominance Output A 75 Ω termination resistor with short traces should be attached between C and ground for optimum performance. Composite Output A 75 Ω termination resistor with short traces should be attached between CVBS and ground for optimum performance. Luminance Output A 75 Ω termination resistor with short traces should be attached between Y and ground for optimum performance. Digital Ground These pins provide the ground reference for the digital section of the CH7202. These pins MUST be connected to the system ground through independent ground vias. Horizontal Sync Input/Output The horizontal sync output is generated by the CH7202 for master mode operation. HSYNC* is an active low signal. In slave mode, the horizontal sync becomes an input. For additional information, please refer to the timing diagrams shown in F igures 6 and 7 on page 8. Vertical Sync Input/Output The vertical sync output is generated by the CH7202 for master mode operation. VSYNC* is an active low signal. In slave mode, the vertical sync becomes an input. For additional information, please refer to the timing diagrams shown in F igures 6 and 7 on page 8. Mode bit 0 - internally pulled-up This input works in conjunction with the MOD1 input to select NTSC, PAL, or Sleep Mode functions. Refer to Table 3, “Video Encoder Modes,” on page 6 f or details. Video Pixel Clock Output 13.5 MHz clock output. MPEG Decoder Clock Output 40.5 MHz or 33.9 MHz clock output (selectable by FS). Double Pixel Clock Input/Output 27 MHz clock output. In slave mode, this pin becomes a 27 MHz clock input. 30 Out C 31 Out CVBS 32 Out Y 33, 34, 40, 44 Power GND 35 In/Out HSYNC* 37 In/Out VSYNC* 38 In MOD0 39 41 43 Out Out In/Out PCLK DCLK 2XPCLK 4 201-0000-030 Rev 2.0, 6/2/99 CHRONTEL CH7202 25 8 11 - 18 1 41 43 MPEG Decoder and System Controller 39 37 35 7 M/S* Y YC[7:0] ACLK DCLK 2XPCLK PCLK VSYNC* HSYNC* YCSWAP C 30 32 Ferrite Bead 1 Ferrite Bead 1 75 Ω 10 9 38 CbSWAP M OD1 MOD0 CVBS 31 Ferrite Bead 1 75 Ω 28 RSET 27 pF2 3 14.318 MHz 27 pF2 XO/FIN 8 360 Ω 4 XI FS JUMPER Figure 3: CH7202 Interface Diagram Note: Note: 1. 2. Please refer to the Optional Output Filter diagram below. The proper value of these capacitors depends on the crystal manufacturer’s specifications. Please refer to AN06 for the details of the calculation. 47 pF 1.2 µH Y, C, CVBS 75 Ω 1 50 pF 270 pF 1.2 µH OUTPUT Figure 4: Optional Output Filter 201-0000-030 Rev 2.0, 6/2/99 Composite Connector CH7202 S-Video Connector 75 Ω 5 CHRONTEL General Description CH7202 The CH7202 is a fully integrated solution for converting 8-bit YCrCb (4:2:2) digital video inputs into highquality NTSC or PAL video signals while generating all essential clock signals for MPEG playback. All essential circuitry for this conversion and clock generation (Dual PLL’s, linear interpolator, digital filters, NTSC/PAL encoder, DAC’s) are contained in the CH7202 making it an essential component of any low-cost solution for video-CD playback machines. Refer to the Block Diagram on page 1 and the Interface Diagram on page 5. Functional Description The encoded luminance (Y) and color-difference (U,V) values are interpolated and filtered through digital filters to minimize aliasing problems. The filtered signals go to the digital encoder where they are transformed to composite and S-video outputs, and then they are converted by the three 9-bit DACs to analog outputs. 8-bit YCrCb (4:2:2) Input Y data and CrCb data are multiplexed into the CH7202 through the YC[7:0] pins. The order of the multiplexed data is determined by the YCSWAP and CbSWAP pins, and is referenced to the horizontal sync pin. Refer to Figure 5 on page 7. Clock/Data/Synchronization Timing The CH7202 can operate in either master or slave mode. In master mode, it supplies the necessary clocks (1X, 2X, video system and audio) and synchronization (HSYNC* and VSYNC*) signals to other building blocks in the video system. In slave mode, the 2X pixel clock, HSYNC* and VSYNC* become inputs to the CH7202, and the remaining clock signals are still output. The timing relationships are shown in Figures 6 and 7 on page 8. Video Encoder Modes Combinations of the two signals MOD0 and MOD1 select the various TV signal format and power saving modes as shown below. Table 3 • Video Encoder Modes MOD1 1 1 0 0 MOD0 1 0 1 0 Video Encoder Mode NTSC PAL PAL-M Sleep mode (Encoder off, both PLLs running) Frequency Select Modes The frequency select input FS affects the DCLK and ACLK outputs as shown below. FS = 1 (default) DCLK = 40.5 MHz, ACLK = 16.934 MHz FS = 0 DCLK = 33.9 MHz, ACLK = 11.289 MHz 6 201-0000-030 Rev 2.0, 6/2/99 CHRONTEL CH7202 HSYNC* HS 2Xpixel Clock CRSEN* = YCSWAP = 00 CbSWAP = 00 CRS = Pixel YC[7:0] Data YCSWAP == 0 CRSEN* 0 CbSWAP == 1 1 CRS YC[7:0] Y0 Y0 Cb0 Cb0 Y1 Y1 Cr0 Y2 Y2 Cb2 Cb2 Y3 Y3 Pixel Data Y0 Y0 Cr0 Y1 Y1 Cb0 Cb0 Y2 Y2 Cr2 Cr2 Y3 Y3 YCSWAP = 11 CRSEN* = CbSWAP ==00 CRS YC[7:0] Data Pixel Cb0 Y0 Y0 Cr0 Cr0 Y1 Y1 Cb2 Cb2 Y2 Y2 Cr2 Cr2 YCRSEN* = 1 CSWAP=1 CbSWAP=1= 1 CRS Pixel YC[7:0] Data Cr0 Cr0 Y0 Y0 Cb0 Y1 Y1 Cr2 Cr2 Y2 Y2 Cb2 Cb2 Figure 5: Data Input Format 201-0000-030 Rev 2.0, 6/2/99 7 CHRONTEL Timing Diagrams CH7202 HSYNC* t7 VSYNC* O DD FI E LD MA S T ER MODE t7 VSYNC* E VE N F IE LD MAS T E R MODE t8 VSYNC* O DD FI E LD S LA V E MODE VSYNC* E V E N FI E LD S LA V E MO DE t8 t9 t9 Figure 6: HSYNC* and VSYNC* Timing t1 2Xpixel Clock t3 Pixel Data t3 HSYNC*,VSYNC (Slave Mode) HSYNC*,VSYNC (Master Mode) t5 t4 t4 t2 t6 HSYNC*=64 2XPCLK, VSYNC*=2 Lines Figure 7: Clock/Data/Synchronization Timing Diagram Note: Refer to Table 8 on page 15 for timing values 8 201-0000-030 Rev 2.0, 6/2/99 CHRONTEL STAR ST T ART OF OF VSYN VS C YNC AN LOG S tart ANA o f ALOG fi el d FIELD 1 1IELD 1 F CH7202 5 23 520 520 5 24 521 521 52 5 522 522 1 523 523 2 524 524 525 525 3 1 1 4 5 2 2 36 3 47 4 8 5 5 69 6 1 70 7 11 8 8 12 9 9 Pre -e qu al iz in g pu lse ve rtica l Ver ti ca l syn c p ul se i nte rva l Po st-e qu al izi ng pp ul seinnte rva l ul se i te rva l Li ne ReAN n ce fere LOG ANA ALOG ver ti ca l su b- car rie r ph a se in ter val coFIELD 1 lo Fr fi el d 2 IELD 2 t1 +V 2 61 258 258 26 2592 259 26 2603 260 26 4 261 261 S ta rt of fi el d 2 2 65 262 262 26 2636 263 2 67 264 264 2 68 265 265 2 69 266 266 27 0 267 267 2 71 268 268 27 2692 269 27 2703 270 2 74 271 271 275 272 272 ST T AR OF VS C YN AN LOG A Re fere n ce suIELD 1 p ha se Fb -ca rrie r t2 +V co lo r fi el d 2 52 3 520 5 24 521 52 5 522 1 523 S ta rt of fi el d 3 2 524 3 525 4 1 5 2 6 3 7 4 8 5 9 6 10 7 11 8 12 9 AN LOG A Re fere n ce su b- ca rrie r ph a se F IELD 2 t3 +V co lo r fie ld 3 2 61 258 26 2 259 263 260 26 4 261 Sta rt o f fie ld 4 2 65 262 26 6 263 26 7 264 26 8 265 2 69 266 27 0 267 27 1 268 272 269 27 2703 2 74 271 27 5 272 R efe re nce su b-c arr ie r ph as e c ol or fie ld 4 Figure 8: Interlaced NTSC Timing Diagram 201-0000-030 Rev 2.0, 6/2/99 9 CHRONTEL CH7202 TA T SR O F VN SY C ALO A AL G N OG F LD 1 IE 620 0 62 1 62 2 62 3 62 4 62 5 62 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 ALO A AL G N OG F LD 2 IE 30 8 30 9 31 0 31 1 31 2 31 3 31 4 315 31 5 316 31 6 317 31 7 318 31 8 319 31 9 320 32 0 321 32 1 322 32 2 323 32 3 ALO A AL G N OG F LD 3 IE 620 62 0 62 1 62 2 62 3 62 4 62 5 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 ALO A AL G N OG F LD 4 IE 30 8 30 9 31 0 31 1 31 2 31 3 31 4 315 5 31 316 6 31 317 7 31 318 8 31 319 9 31 320 0 32 321 1 32 322 2 32 323 3 32 B RST BU ST UR B KIN BLAN ING LAN G K IN TE R VA L S 4 3 B RST PH SE = E E EN E P A EF R NC H EL T IV BU ST P AS = R FE E CE PH SE = 13 ° R AT E TO U UR HA E 5° ELA IVE T O P SW CH = 0 +V C M ON N AL SW C IT H 0, C PO 2 T OM N P AL IT , OP E ° 2 5° ELA VE O B RST PH SE = E E EN E 1H EF R NC P A 25 E T E BU ST P AS = R FE E CE PH SE+ 90° = 22 ° R LA IV T U UR HA E TI P SW C IT 1, V C MP N N PAL SW CH = 1 - V CO PO E T AL IT H , OM O Figure 9: Interlaced PAL Timing Diagram 10 201-0000-030 Rev 2.0, 6/2/99 CHRONTEL CH7202 Color / Level Wh ite Yellow Cyan Green Magenta Red Blue Black Blank mA 24.60 26.59 22.85 24.59 19.85 21.30 18.11 19.30 15.23 16.15 13.49 14.15 10.49 11.00 8.74 9.00 7.49 7.58 V 0.922 0.997 0.857 0.922 0.745 0.799 0.679 0.724 0.571 0.606 0.506 0.531 0.393 0.413 0.327 0.338 0.281 0.284 COLOR BARS : Sync 0.50 0.00 0.019 0.000 Note: 1 100% amplitude, 100% saturation color bars are shown Note: 2 Vref = 1.235V, RSET = 360 Ω, 75 Ω d oubly terminated load Figure 10: NTSC Y (Luminance) Output Waveform Color / Level Wh ite Yellow Cyan Green Magenta Red Blue Black Blank Blank mA 24.60 26.83 22.85 24.69 19.85 21.19 18.11 19.05 15.23 15.70 13.49 13.57 10.49 10.21 8.74 8.08 7.49 V 0.922 1.006 0.857 0.926 0.745 0.795 0.679 0.715 0.571 0.589 0.506 0.509 0.393 0.383 0.327 0.303 0.281 COLOR BARS : Sync 0.50 0.00 0.019 0.000 Note: 1 100% amplitude, 100% saturation color bars are shown Note: 2 Vref = 1.235V, RSET = 360 Ω, 75 Ω d oubly terminated load Figure 11: PAL Y (Luminance) Video Output Waveform 201-0000-030 Rev 2.0, 6/2/99 11 CHRONTEL CH7202 Color / Level Cyan / Red Green / Magenta Yellow / Blue mA 22.60 25.37 21.85 24.59 19.61 22.16 V 0.848 0.951 0.819 0.922 0.735 0.831 0.599 0.681 0.468 0.536 0.337 0.391 COLOR BARS : Peak Burst Blank Peak Burst 15.98 18.15 12.49 14.294 8.99 10.44 3.579545 MHz Color Burst (9 cycles) Yellow / Blue Green / Magenta Cyan / Red 5.37 6.43 3.12 4.00 2.37 3.21 0.201 0.241 0.117 0.150 0.089 0.121 Note: 1 100% amplitude, 100% saturation color bars are shown Note: 2 Vref = 1.235V, RSET = 360Ω, 75 Ω doubly terminated load Figure 12: NTSC C (Chrominance) Video Output Waveform Color / Level Cyan / Red Green / Magenta Yellow / Blue mA 22.60 27.06 21.85 26.22 19.61 23.63 16.23 19.21 12.49 15.24 8.74 11.28 5.37 6.85 3.12 4.27 2.37 3.43 V 0.848 1.015 0.819 0.983 0.735 0.886 0.609 0.720 0.468 0.572 0.328 0.423 0.201 0.257 0.117 0.160 0.089 0.129 COLOR BARS : Peak Burst Blank Peak Burst 4.433619 MHz Color Burst (10 cycles) Yellow / Blue Green / Magenta Cyan / Red Note: 1 100% amplitude, 100% saturation color bars are shown Note: 2 Vref = 1.235V, RSET = 360Ω, 75 Ω d oubly terminated load Figure 13: PAL C (Chrominance) Video Output Waveform 12 201-0000-030 Rev 2.0, 6/2/99 CHRONTEL M EN A AG T YE LLOW CH7202 BLA K C BLA K C GR EN E W IT HE CN YA Color / Level Pea C k hrom a W hite mA 33.89 32.45 26.59 27.37 V 1.271 1.217 0.997 1.026 COLOR BARS : 3.5795 M z 45 H C rB olo urst (9 C les yc ) Pea Bu t k rs Black Blank Pea Bu t k rs 12.00 11.43 9.00 9.62 7.58 8.16 4.32 3.72 0.450 0.429 0.338 0.360 0.306 0.284 0.162 0.139 Sy nc 0.50 0.00 0.019 0.000 Figure 14: Composite NTSC Video Output Waveform Note: Vref = 1.235V, RSET = 360 Ω, 75Ω d oubly terminated load M EN A AG T YE LLOW GR EN E W IT HE CN YA Color / Level Pea C k hrom a W hite mA 33.89 33.08 27.37 26.83 V 1.271 1.240 1.026 1.006 COLOR BARS : 4.4336 M z 19 H C rB olo urst (10 C le yc s) Pea Bu t k rs Blank/ Blac k Pea Bu t k rs 12.00 12.04 8.64 8.08 4.58 4.12 0.450 0.452 0.324 0.303 0.171 0.154 Sy nc 0.50 0.00 0.019 0.000 Figure 15: Composite PAL Video Output Waveform Note: Vref = 1.235V, RSET = 360 Ω, 75 Ω doubly terminated load 201-0000-030 Rev 2.0, 6/2/99 BLU E R ED BLU E R ED 13 CHRONTEL Electrical Specifications Table 4 • Absolute Maximum Ratings CH7202 Description Min Typ Max Units VDD relative to GND - 0.5 7.0 V Input voltage of all digital pins 1 GND - 0.5 VDD + 0.5 V T SC Analog output short circuit duration Indefinite Sec Ambient operating temperature - 55 125 °C TAMB TSTOR Storage temperature - 65 150 °C TJ Junction temperature 150 °C TVPS Vapor phase soldering (one minute) 220 °C PMAX Maximum power dissipation TBD W Note: Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the normal operating conditions is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect reliability. T he device is fabricated using high-performance CMOS technology. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce destructive latchup. Symbol Table 5 • Recommended Operating Conditions Symbol AVDD DVDD TA RL Description Analog supply voltage Digital supply voltage Ambient operating temperature Output load to DAC outputs Min Typ 5.00 5.00 25 37.5 Max Units 0 70 °C Ω Table 6 • Electrical Characteristics (Operating Conditions: TA = 0°C – 70°C, VDD = 5V ± 5%) Symbol Description Min Typ Max Unit Video D/A resolution 9 9 9 Bits Full scale output current 33.08 mA Video level error using external reference 5 % using internal reference 10 % Total Current Consumption 135 mA A s applied to Tables 4, 5, and 6, Recommended Operating Conditions are used as test conditions unless otherwise specified. RSET = 360 Ω, and NTSC CCIR601 operation. Typical values are based on 25° C and +5V. Note: Table 7 • Digital Inputs / Outputs Symbol VOH VOL VIH VIL I PU ILK CDIN CDOUT Description Output high voltage Output low voltage Input high voltage Input low voltage Input internal pull-up current Input leakage current Input capacitance Output capacitance Test Condition @ TA = 25°C IOH = - 4 00 µA IOL = 3 .2 mA Min 2.4 2.0 GND - 0.5 5 -10 Typ Units V 0.4 V VDD + 0 .5 V 0.8 V 25 µA 10 µA pF pF Max f = 1 MHz, VIN = 2 .4V 7 10 14 201-0000-030 Rev 2.0, 6/2/99 CHRONTEL Electrical Specifications (continued) Table 8 • AC Characteristics Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 Description 2XPCLK 2XPCLK high time Pixel/Sync setup time Pixel/Sync hold time Sync active delay time Sync inactive delay time HSYNC* to VSYNC* delay HSYNC* to VSYNC* field detect HSYNC* to VSYNC* HSYNC* pulse width VSYNC* pulse width Test Conditions: 16.1 64 x t1 2.0 30 14.8 6 3 3 17 30 15.6 Min Typ 37 22.2 Max CH7202 Units ns ns ns ns ns ns ns µS µS ns Hor. lines Unless otherwise specified, the testing conditions are the same as in Table 5, “Recommended Operating Conditions,” on page 14. TTL input values are 0 – 3V, with input rise / fall times < 3 ns, measured between the VIL and VIH. Timing reference points at 50% for non-TTL inputs and outputs. TTL reference points at 1.5V for inputs and outputs. Analog output load < 10 pF. Since the CH7202 does not have a pixel clock input, all input signal timing is chosen with respect to the output clock timing of 2XPCLK and PCLK. PCLK can be used at the “Qualifying” clock for certain MPEG decoders. 201-0000-030 Rev 2.0, 6/2/99 15 CHRONTEL CH7202 ORDERING INFORMATION Part number CH7202 Package type PLCC Number of pins 44 Voltage supply 5V Chrontel 2210 O’Toole Avenue San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 19 97 Ch rontel , Inc. All R igh ts Re served . C hron te l PRODU CTS ARE NOT AUTHORIZED FOR AN D SHOUL D NOT BE USED WITH IN LIFE SU PPOR T SYSTEMS OR NU CLEAR FACILITY APPLICATION S WITHOUT TH E SPEC IFIC WRITTEN CONSEN T OF Chro ntel. Life su ppo rt systems are th ose in te nde d to sup port or sustai n li fe and w hose fa ilu re to p erform w hen used a s dire cte d can re ason abl y e xpect to resu lt i n p erson al in jury or dea th . C hron te l reserve s the rig ht to make chan ges at any ti me witho ut no ti ce to imp rove an d su ppl y the be st po ssibl e prod uct an d is n ot re spon sibl e and d oes no t assu me any li abi lity fo r mi sapp lica ti on or use o utside the li mits sp ecifie d in this do cumen t. We pro vi e n o warra nty for the use of our pro ducts and a ssume no d l iab ili ty for errors con ta ine d in this do cumen t. Printed i n th e U.S.A. 16 201-0000-030 Rev 2.0, 6/2/99