CH7301A-T

CH7301A CHRONTEL Chrontel CH7301 DVI Output Device Features • • • • • • • • • • DVI Transmitter up to 165MHz DVI low jitter PLL DVI hot plug detection Provides 10-bit high speed video DAC for RGB output DAC connection detect Programmable power management Fully programmable through I 2 C port Complete Windows and DOS driver support Low voltage interface support to graphics device Offered in a 64-pin LQFP package General Description The CH7301 is a Display controller device which accepts a digital graphics input signal, and encodes and transmits data through a DVI (TMDSTM link) or DFP (Digital flat panel) can also be supported. The device accepts data over one 12-bit wide variable voltage data port which supports four different RGB data formats. The DVI processor includes a low jitter PLL for generation of the high frequency serialize clock, and all circuitry required to encode, serialize and transmit data. The CH7301 comes in versions able to drive a DFP display at a pixel rate of up to 165MHz, supporting UXGA resolution displays. No scaling of input data is performed on the data output to the DVI device. XCLK,XCLK* Clock Driver DVI Encode DVI (TMDS T M link) PLL DVI Serialize DVI Driver TLC,TLC* TDC0,TDC0* TDC1,TDC1* TDC2,TDC2* VSWING Three 8-bit DAC's R G B D[11:0] 12 Data Latch, Demux H,V,DE VREF 3 H,V,DE Latch ISET IIC Control C/H SYNC HPDET GPIO[1:0] TLDET* AS SC SD BCO RESET* Figure 1: Functional Block Diagram 201-0000-036 Rev 1.1, 3/20/2000 *TMDS is Trademark of Silicon Image Inc 1 CHRONTEL Pin Descriptions Package Diagram CH7301A XCLK* DGND DVDD DE VREF H V DGND GPIO[1] / TLDET* GPIO[0] HPDET AS DGND DVDD RESET* SD SC AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DVDD XCLK D[10] D[11] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] C / H SYNC BCO TLDET* DVDDV AVDD NC GND AGND GND B R G NC ISET GND VDD Chrontel CH7301 TDC0 TDC1 TGND TGND TDC2 TVDD TLC TDC0* TDC1* AVDD VSWING Figure 2: 64-Pin LQFP 2 TDC2* AGND 201-0000-036 Rev 1.1, 3/20/2000 TGND TVDD TLC* 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CHRONTEL Table 1: Pin Description 64-Pin # Pins Type LQFP 2 1 In CH7301A Symbol DE Description Data Enable This pin accepts a data enable signal which is high when active video data is input to the device, and low all other times. The levels are 0 to DVDDV, and the VREF signal is used as the threshold level. This input is used by the DVI links. 3 1 In VREF Reference Voltage Input The VREF pin inputs a reference voltage of DVDDV / 2. The signal is derived externally through a resistor divider and decoupling capacitor, and will be used as a reference level for data, sync, data enable and clock inputs. 4 5 7 1 1 2 In/Out In/Out In/Out H V GPIO[1] / TLDET* Horizontal Sync Input / Output This output is only for use with the TV-Out function. Vertical Sync Input / Output This output is only for use with the TV-Out function. General Purpose Input - Output[1] / DVI Link Detect Output (internal pull-up) This pin provides a general purpose I/O controlled via the IIC bus. The internal pull-up will be to the DVDD supply. When the GPIO[1] pin is configured as an input, this pin can be used to output the DVI link detect signal (pulls low when a termination change has been detected on the HPDET input). This is an open drain output. The output is released through IIC control. 8 2 In/Out GPIO[0] General Purpose Input - Output[0] (internal pull-up) This pin provides a general purpose I/O controlled via the IIC bus. The internal pull-up will be to the DVDD supply. 9 1 In HPDET Hot Plug Detect (internal pull-down) This input pin determines whether the TMDSTM link is connected to a DVI monitor. When terminated, the monitor is required to apply a voltage greater than 2.4 volts. Changes on the status of this pin will be relayed to the graphics controller via the P-Out/TLDET* or GPIO[1]/TLDET* pin pulling low. 10 1 In AS Address Select (Internal pull-up) This pin determines the IIC address of the device (1,1,1,0,1,AS*,AS). 13 1 In RESET* Reset * Input (Internal pull-up) When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the IIC register. 14 1 In/Out SD Serial Data Input / Output This pin functions as the serial data pin of the IIC interface port, and uses the DVDD supply. 15 1 In SC 19 1 In VSWING Serial Clock Input This pin functions as the clock pin of the IIC interface port, and uses the DVDD supply. DVI Link Swing Control This pin sets the swing level of the DVI outputs. A 2.4K ohm resistor should be connected between this pin and TGND using short and wide traces. 201-0000-036 Rev 1.1, 3/20/2000 3 CHRONTEL Table 1: Pin Description 64-Pin # Pins Type LQFP 22, 21 2 Out CH7301A Symbol TDC0, TDC0* Description TMDS TM Data Channel 0 Outputs These pins provide the TMDSTM differential outputs for data channel 0 (blue). 25, 24 2 Out TDC1, TDC1* TMDS TM Data Channel 1 Outputs These pins provide the TMDSTM differential outputs for data channel 1 (green). 28, 27 2 Out TDC2, TDC2* TMDS TM Data Channel 2 Outputs These pins provide the TMDSTM differential outputs for data channel 2 (red). 30, 31 2 Out TLC, TLC* TMDS TM Link Clock Outputs These pins provide the differential clock output for the TMDSTM interface corresponding to data on the TDC[0:2] outputs. 35 1 In ISET Current Set Resistor Input This pin sets the DAC current. A 140 ohm resistor should be connected between this pin and GND (DAC ground) using short and wide traces. 37 38 39 43 46 1 1 1 1 1 Out Out Out Out G R B NC TLDET* Green Output Red Output Blue Output No Connect DVI Link Detect Output This pin provides an open drain output which pulls low when a termination change has been detected on the HPDET input. The output is released through IIC control. 47 1 Out BCO Buffered Clock Output This output pin provides a buffered clock output, driven by the DVDD supply. The output clock can be selected using the BCO register. 48 50 – 55, 58 – 63 57, 56 1 12 Out In C/H SYNC Composite / Horizontal Sync Output This pin is only for use with the TV-Out function. D[11] - D[0] Data[11] through Data[0] Inputs 2 In XCLK, XCLK* These pins accept the 12 data inputs from a digital video port of a graphics controller. The levels are 0 to DVDDV, and the VREF signal is used as the threshold level. External Clock Inputs These inputs form a differential clock signal input to the CH7301 for use with the H, V, DE and D[11:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF. The output clocks from this pad cell are able to have their polarities reversed under the control of the MCP bit. Digital Supply Voltage (3.3V) Digital Ground I/O Supply Voltage (3.3V - 1.1V) DVI Transmitter Supply Voltage (3.3V) DVI Transmitter Ground PLL Supply Voltage (3.3V) PLL Ground DAC Supply Voltage (3.3V) DAC Ground 201-0000-036 Rev 1.1, 3/20/2000 1, 12, 49 6, 11, 64 45 23, 29 20, 26, 32 18, 44 16, 17, 41,42 33 34, 36, 40 4 3 3 1 2 3 2 4 1 3 Power Power Power Power Power Power Power Power Power DVDD DGND DVDDV TVDD TGND AVDD AGND VDD GND CHRONTEL Mode of Operation CH7301A The CH7301 is capable of being operated as a single DVI output link. Descriptions of the single DVI output link operating mode, with a block diagram of the data flow within the device is shown below. DVI Output In DVI Output mode, multiplexed input data, sync and clock signals are input to the CH7301 from the graphics controllers digital output port. Data will be 2X multiplexed, and the clock inputs can be 1X or 2X times the pixel rate. Some examples of modes supported are shown in the table below, and a block diagram of the CH7301 is shown on the following page. For the table below, clock frequencies for given modes were taken from VESA DISPLAY MONITOR TIMING SPECIFICATIONS if they were detailed there, not VESA TIMING DEFINITION FOR FLAT PANEL MONITORS. The device is not dependent upon this set of timing specifications. Any values of pixels/line, lines/frame and clock rate are acceptable, as long as the pixel rate remains below 165MHz. For correct DVI operation, the input data format must be selected to be one of the RGB input formats. Table 2: DVI Output Graphics Resolution 720x400 640x400 640x480 720x4801 720x5761 800x600 1024x768 1280x720 1280x1024 1600x1200 1920x1080 1 2 Active Aspect Ratio 4:3 8:5 4:3 4:3 4:3 4:3 4:3 16:9 4:3 4:3 16:9 Pixel Aspect Refresh Rate Ratio 1.35:1.00 1:1 1:1 9:8 15:12 1:1 1:1 1:1 1:1 1:1 1:1 (Hz)