CH7303

Chrontel CH7303 Preliminary Advanced Information Chrontel CH7303 HDTV / DVI Encoder Features • Digital Visual Interface (DVI) Transmitter up to 165M pixels/second • DVI low jitter PLL • DVI hot plug detection • Analog YPrPb outputs for HDTV • HDTV support for 480p, 576p, 720p, 1080i and 1080p • MacrovisionTM copy protection support for HDTV • Programmable digital input interface supporting RGB (15, 16, 24 or 30 bit) and YCrCb input data formats • Can output either RGB or YPrPb • TV / Monitor connection detect • Programmable power management • Three 10-bit video DAC outputs • Fully programmable through serial port • Complete Windows and DOS driver support • Low voltage interface support to graphics device • Offered in a 64-pin LQFP package • Backward pin compatible with CH7301 or CH7009/11 • Support three additional 15 bit multiplexed RGB Input Data Format (IDF 6,7.8) † Patent number 5,781,241 ¥ Patent number 5,914,753 General Description The CH7303 is a Display Controller device which accepts a digital graphics input signal, and encodes and transmits data through a DVI link (DFP can also be supported), VGA ports (analog RGB) or a HDTV port (YPrPb). The device is able to encode the video signals and generate synchronization signals for analog HDTV interface standards and graphics standards up to UXGA. The device accepts data over one 15-bit wide variable voltage data port which supports 9 different data formats including RGB and YCrCb. The DVI processor includes a low jitter PLL for generation of the high frequency serialized clock, and all circuitry required to encode, serialize and transmit data. The CH7303 is able to drive a DFP display at a pixel rate of up to 165MHz, supporting UXGA resolution displays. No scaling of input data is performed on the data output to the DVI device. In addition to DVI encoder modes, bypass modes are included which perform color space conversion to HDTV standards and generate and insert HDTV sync signals, or output VGA style analog RGB for use as a CRT DAC. Note: Other names and brands may be claimed as property by others. HPDET GPIO[1:0] AS SPC SPD RESET* H,V DE VREF 2 Serial Port Control / 24 DVI PLL DVI Encode DVI Serialize DVI Driver / 2 / 2 / 2 / 2 / 2 TLC, TLC* TDC0, TDC0* TDC1, TDC1* TDC2, TDC2* HSYNC, VSYNC H,V,DE Latch / 2 XCLK,XCLK* 2 Clock Driver / 24 Color Space Conversion Sync Decode HDTV YPbPr DAC 2 DAC 1 DAC 0 DAC[2] DAC[1] DAC[0] D[14:0] ISET 15 Data Latch, Demux MUX RGB / 30 / 30 Three 10-bit DAC's Figure 1: Functional Block Diagram 209-0000-031 Rev. 0.4, 8/26/2002 1 CHRONTEL 1.0 Pin-Out 1.1 Package Diagram CH7303 XCLK* DGND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVDD DE VREF H V DGND GPIO[1] / HPINT GPIO[0] HPDET AS DGND DVDD RESET* SPD SPC AGND DVDD XCLK D[10] D[11] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Chrontel CH7303 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 H SYNC V SYNC D[12] VDDV AVDD D[13] D[14] AGND GND B/Pb R/Pr G/Y N/C ISET GND VDD AGND AVDD TDC0* TDC1* TDC2* TDC0 TDC1 TVDD TDC2 TVDD TGND TGND TLC* TLC VSWING Figure 2: 64-Pin LQFP Package 2 209-0000-031 TGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Rev. 0.4, 8/26/2002 CHRONTEL 1.2 Pin Description # Pins 1 In Type Symbol DE Description Data Enable CH7303 Table 1: Pin Description Pin # 2 This pin accepts a data enable signal which is high when active video data is input to the device, and low all other times. The levels are 0 to VDDV, and the VREF signal is used as the threshold level. This input is used by the DVI. 3 1 In VREF Reference Voltage Input The VREF pin inputs a reference voltage of VDDV / 2. The signal is derived externally through a resistor divider and decoupling capacitor, and will be used as a reference level for data, sync, data enable and clock inputs. 4 1 In H Horizontal Sync Input This pin accepts a horizontal sync input for use with the input data. The amplitude will be 0 to VDDV and the VREF signal is used as the threshold level. 5 1 In V Vertical Sync Input This pin accepts a vertical sync input for use with the input data. The amplitude will be 0 to VDDV and the VREF signal is used as the threshold level. 7 2 In/Out GPIO[1] / HPINT DVI Link Detect Output When the GPIO[1] pin is configured as an output, this pin can be used to output the DVI detect signal (pulls low when a termination change has been detected on the HPDET input). This is an open drain output. The output is released through serial port control. 8 2 In/Out GPIO[0] General Purpose Input - Output[0] (Weak internal pull-up) This pin provides a general purpose I/O controlled via the serial port. The internal pull-up will be to the DVDD supply. 9 1 In HPDET Hot Plug Detect (internal pull-down) This input pin determines whether the DVI is connected to a DVI monitor. When terminated, the monitor is required to apply a voltage greater than 2.4 volts. Changes on the status of this pin will be relayed to the graphics controller via GPIO[1]/TLDET* pin pulling low. 10 13 14 1 1 1 In In In/Out AS RESET* SPD Address Select (Internal pull-up) This pin determines the serial port address of the device (1,1,1,0,1,AS*,AS). Reset* Input (Internal pull-up) When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port register. Serial Port Data Input / Output This pin functions as the bi-directional data pin of the serial port and operates with inputs from 0 to VDDV. Outputs are driven from 0 to VDDV. 15 19 1 1 In In SPC VSWING Serial Port Clock Input This pin functions as the clock input of the serial port and operates with inputs from 0 to VDDV. DVI Swing Control This pin sets the swing level of the DVI outputs. A 2.4K ohm resistor should be connected between this pin and TGND using short and wide traces. 22, 21 25, 24 2 2 Out Out TDC0, TDC0* TDC1, TDC1* DVI Data Channel 0 Outputs These pins provide the DVI differential outputs for data channel 0 (blue). DVI Data Channel 1 Outputs These pins provide the DVI differential outputs for data channel 1 (green). 209-0000-031 Rev. 0.4, 8/26/2002 3 CHRONTEL Table 1: Pin Description (contd.) Pin # 28, 27 30, 31 35 # Pins 2 2 1 Type Out Out In Symbol TDC2, TDC2* TLC, TLC* ISET Description DVI Data Channel 2 Outputs CH7303 These pins provide the DVI differential outputs for data channel 2 (red). DVI Clock Outputs These pins provide the differential clock output for the DVI interface corresponding to data on the TDC[0:2] outputs. Current Set Resistor Input This pin sets the DAC current. A 140 ohm resistor should be connected between this pin and DAC ground (pins 34 and 40) using short and wide traces. 37 1 Out Y/G (DAC1) Luma / Green Output This pin outputs a selectable video signal. The output is designed to drive a 75ohm doubly terminated load. The output can be selected to be the luminance component of YprPb or Green. 38 1 Out R/Pr (DAC2) Red / Pr Output This pin outputs a selectable video signal. The output is designed to drive a 75ohm doubly terminated load. The output can be selected to be the Pr component of YPrPb or red. 39 1 Out B/Pb (DAC0) Blue / Pb Output This pin outputs a selectable video signal. The output is designed to drive a 75ohm doubly terminated load. The output can be selected to be the Pb component of YPrPb or blue. 47 1 Out VSYNC VSYNC By programming BCO register, a buffered version of VGA vertical sync can be acquired from this pin . This output pin can also provide a buffered clock output, driven by the DVDD supply. 48 1 Out In/Out HSYNC Horizontal Sync Output A buffered version of VGA horizontal sync can be acquired from this pin via DC register) 50 -55, 15 58 –63, 42, 43, 46 57, 56 2 D[14] - D[0] Data[14] through Data[0] Inputs These pins accept the 15 data inputs from a digital video port of a graphics controller. The levels are 0 to VDDV, and the VREF signal is used as the threshold level. In XCLK, XCLK* External Clock Inputs These inputs form a differential clock signal input to the CH7303 for use with the H, V, DE and D[14:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF. The clock polarity used can be selected using the MCP control bit. 1, 12, 49 6, 11, 64 45 23, 29 20, 26, 32 18, 44 16, 17, 41 33 34, 40 3 3 1 2 3 2 3 1 2 Power Power Power Power Power Power Power Power Power DVDD DGND VDDV TVDD TGND AVDD AGND VDD GND Digital Supply Voltage (3.3V) Digital Ground I/O Supply Voltage (1.1V to 3.3V) DVI Transmitter Supply Voltage (3.3V) DVI Transmitter Ground PLL Supply Voltage (3.3V) PLL Ground DAC Supply Voltage (3.3V) DAC Ground 4 209-0000-031 Rev. 0.4, 8/26/2002 CHRONTEL 2.0 Functional Description 2.1 TV Output Operation CH7303 The CH7303 is capable of being operated as in one of several bypass modes for driving monitors requiring component video signals (HDTV, multi-sync monitors, etc.). All modes make use of the same set of DAC’s, and therefore cannot be used simultaneously. Table 2 describes the possible operating modes. A ‘p’ following a number in the Input Scan Type column indicates a progressive scan (non-interlaced) input where the number indicates the active number of lines per frame. An ‘i’ following a number in the Input Scan Type column indicates an interlaced input where the number indicates the active number of lines per frame. Detailed descriptions of each of the operating modes follows Table 2. Table 2: Operating Modes Input Scan Input Data Type Format non-interlaced RGB non-interlaced (480p, 576p, 720p) Interlaced (1080i) non-interlaced (1080p) RGB / YCrCb1 RGB / YCrCb1 RGB / YCrCb1 Output scan Type non-interlaced non-interlaced interlaced non-interlaced Output Format RGB YpbPr2,3 YpbPr3 YpbPr3 Operating Mode RGB bypass HDTV/EDTV bypass HDTV/EDTV bypass (1080i) HDTV/EDTV bypass (1080p) 2.1.1 HDTV / EDTV Bypass In HDTV / EDTV Bypass mode, data, sync and clock signals are input to the CH7303 from a graphics device in the scanning method that matches the display device (interlaced data is sent to the CH7303 to drive an interlaced display, non-interlaced data is sent to the CH7303 to drive a non-interlaced display). The input data format can be YCrCb or RGB. Horizontal and vertical sync signals must either be sent to the CH7303 from the graphics device or embedded in the data stream according to SMPTE standards. Data is 2X multiplexed, and the XCLK clock signal can be 1X or 2X times the pixel rate. Input data is color space converted to the selected video format, has sync signals generated and is output from the video DAC’s. The output format is YPbPr. The graphics resolutions supported for HDTV Bypass mode are shown in Table 3 below. The resolutions supported for EDTV Bypass mode are shown in Table 3 below. Table 3: HDTV Bypass Active Total Resolution Resolution 1280x720 1650x750 1280x720 1920x1080 1920x1080 1920x1080 1920x1080 1648x750 2200x1125 2640x1125 2376x1250 2200x1125 Scan Type Non-Interlaced Non-Interlaced Interlaced Interlaced Interlaced Non-Interlaced Pixel Clock (MHz) 74.25 74.25/1.001 74.160 74.25 74.25/1.001 74.25 74.25 148.5 148.5/1.001 74.25 74.25/1.001 148.5 74.25 74.25 74.25/1.001 74.304 148.5 Frame Rate (Hz) 60 60/1.001 60 30 30/1.001 25 25 60 60/1.001 30 30/1.001 50 25 24 24/1.001 24 50 Standard SMPTE 296M SMPTE 274M SMPTE 274M SMPTE 295M SMPTE 274M 1920x1080 1920x1080 1920x1080 1920x1080 2640x1125 2750x1125 2752x1125 2376x1250 Non-Interlaced Non-Interlaced Non-Interlaced Non-Interlaced SMPTE 274M SMPTE 274M SMPTE 295M 209-0000-031 Rev. 0.4, 8/26/2002 5 CHRONTEL Table 4: EDTV Bypass Active Total Resolution Resolution 720x480 858x525 720x483 858x525 720x480 856x525 720x483 856x525 720x576 864x625 Scan Type Non-Interlaced Non-Interlaced Non-Interlaced Non-Interlaced Non-interlaced Pixel Clock (MHz) 27.0 27.027 26.937 26.964 27.0 Frame Rate (Hz) 60/1.001 60 60/1.001 60 50 Standard EIA-770.2-A SMPTE 293M ITU-R BT.1358 CH7303 2.1.2 RGB Bypass In RGB Bypass mode, data, sync and clock signals are input to the CH7303 from a graphics device, and bypassed directly to the D/A converters to implement a second CRT DAC function. External sync signals must be supplied from the graphics device. These sync signals are buffered internally, and can be output to drive the CRT. The input data format must be RGB in this operating mode. Input data is 2X multiplexed, and the XCLK clock signal can be 1X or 2X times the pixel rate. The CH7303 can support a pixel rate of 165MHz. This operating mode uses all 8 bits of the DAC’s 10-bit range, and provides a nominal signal swing of 0.661V (or 0.7V depending on DAC Gain setting in control registers) when driving a 75Ω doubly terminated load. No scaling, scan conversion or flicker filtering is applied in Bypass modes. 2.2 DVI Output 2.2.1 DVI Transmitter In DVI Output mode, multiplexed input data, sync and clock signals are input to the CH7303 from the graphics controller’s digital output port. Data will be 2X multiplexed, and the clock inputs can be 1X or 2X times the pixel rate. Some examples of modes supported are shown in the table. For the table below, clock frequencies for given modes were taken from VESA DISPLAY MONITOR TIMING SPECIFICATIONS if they were detailed there, not VESA TIMING DEFINITION FOR FLAT PANEL MONITORS. The device is not dependent upon this set of timing specifications. Any values of pixels/line, lines/frame and clock rate are acceptable, as long as the pixel rate remains below 165MHz. The input format can be any RGB format or YCrCb (see Input Data Formats section). Table 9: DVI Output Graphics Active Aspect Resolution Ratio 720x400 640x400 640x480 720x480 720x576 800x600 1024x768 1280x720 4:3 8:5 4:3 4:3 4:3 4:3 4:3 16:9 Pixel Aspect Ratio 1.35:1.00 1:1 1:1 9:8 15:12 1:1 1:1 1:1 Refresh Rate (Hz)