CMT2N7002E

CMT2N7002E SMALL SIGNAL MOSFET GENERAL DESCRIPTION This N-Channel enhancement mode field effect transistor is produced using high cell density, DMOS technology. These products have been designed to minimize on-state resistance while provide rugged, reliable, and fast switching performance. This product is particularly suited for low voltage, low current applications such as small servo motor control, power MOSFET gate drivers, and other switching applications. FEATURES Low On-Resistance: 3Ω Low Threshold: 2V (typ.) Low Input Capacitance: 25pF Fast Switching Speed: 7.5ns Low Input and Output Leakage PIN CONFIGURATION SOT-23 SYMBOL D Top View 3 DRAIN SOURCE GATE G 1 2 S N-Channel MOSFET ORDERING INFORMATION Part Number CMT2N7002E CMT2N7002EG* *Note: G : Suffix for Pb Free Product Package SOT-23 SOT-23 ABSOLUTE MAXIMUM RATINGS Rating Drain Source Voltage Drain-Gate Voltage (RGS = 1.0MΩ) Continuous Drain Current (TJ = 150℃) Pulsed Drain Current (Note 1) Gate-to-Source Voltage Total Power Dissipation TA = 25℃ TA = 70℃ TA = 25℃ TA = 70℃ Symbol VDSS VDGR ID IDM VGS PD TJ, TSTG θJA Value 60 60 240 190 1300 ±20 0.35 0.22 -55 to 150 357 Unit V V mA mA V W ℃ ℃/W Operating and Storage Temperature Range Thermal Resistance － Junction to Ambient Note1: Pulse Width limited by maximum junction temperature. 2004/11/05 Preliminary Rev. 2 Champion Microelectronic Corporation Page 1 CMT2N7002E SMALL SIGNAL MOSFET ELECTRICAL CHARACTERISTICS Unless otherwise specified, TJ = 25℃. CMT2N7002E Characteristic Drain-Source Breakdown Voltage (VGS = 0 V, ID = 10 μA) Zero Gate Voltage Drain Current (VDS = 60 V, VGS = 0 V) (VDS = 60 V, VGS = 0 V, TC = 125℃) Gate Body Leakage (VDS = 0 V, VGS = ±15 V) Gate Threshold Voltage * (VDS = VGS, ID = 250 μA) On-State Drain Current (Note 2) (VDS = 7.5 V, VGS = 10V) (VDS = 10 V, VGS = 4.5V) Static Drain-Source On-Resistance (Note 2) (VGS = 10 V, ID = 0.25A) (VGS = 4.5 V, ID = 0.2A) Diode Forward On-Voltage (IS = 200 mA, VGS = 0V) Forward Transconductance (VDS = 15 V, ID = 200mA) (Note 2) Total Gate Charge Gate-Source Charge Gate-Drain Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time (Note 1,3) Turn-Off Delay Time (Note 1,3) (VDS = 25 V, VGS = 0 V, f = 1.0 MHz) (Note 1) (VDS = 25 V, VGS = 0 V, f = 1.0 MHz) (Note 1) (VDD = 10 V, ID = 250 mA, VGEN = 10 V, RG = 10Ω, RL = 40Ω) VSD gFS Qg Qgs Qgd Ciss Coss Crss td(on) td(off) 150 RDS(on) 1.9 3.5 0.85 260 0.4 0.06 0.06 21 7 2.5 13 18 20 25 0.6 3 4 1.2 V mmhos nC nC nC pF pF pF ns ns Ω Id(on) 800 350 1900 450 mA IGSS VGS(th) 1.0 2.0 IDSS 1.0 500 ±10 2.5 μA μA nA V Symbol V(BR)DSS Min 60 Typ 68 Max Units V Note 1: For Design Aid Only, not subject to production testing. Note 2: Pulse test: PW