FS612509-02

FS612509-01/-02 AMERICAN MICROSYSTEMS, INC. 1:9 Zero-Delay Clock Buffer IC November 2000 1.0 • Features 2.0 Description Generates one bank of five outputs (1Y0 to 1Y4) and one bank of four outputs (2Y0 to 2Y3) from one reference clock input (CLK) Designed to meet the PLL Component Specifications as noted in the PC133 SDRAM Registered DIMM Design Specification External feedback input (FBIN) to synchronize all clock outputs to the clock input Operating frequency: 25MHz to 140MHz Tight tracking skew (spread-spectrum tolerant) On-chip 25Ω series damping resistors for driving point-to-point loads Separate bank controls: M Signal 1G enables or disables outputs 1Y0 - 1Y4 M Signal 2G enables or disables outputs 2Y0 - 2Y3 Available with an auto power-down option that turns off the PLL and forces all outputs low when the reference clock stops (FS612509-02) Packaged in a 24-pin TSSOP • • • • • • The FS612509 is a low skew, low jitter CMOS zero-delay phase-lock loop (PLL) clock buffer IC designed for highspeed motherboard applications, such as those using 133MHz SDRAM. Nine buffered clock outputs are derived from an onboard open-loop PLL. The PLL aligns the frequency and phase of all output clocks to the input clock CLK, including an FBOUT clock that feeds back to FBIN to close the loop. One group of five outputs 1Y0 to 1Y4 are enabled and disabled low by the active-high 1G signal. A second group of four outputs 2Y0 to 2Y3 are enabled and disabled low by the active-high 2G signal. The PLL may be bypassed by pulling AVDD to ground. Figure 2: Pin Configuration AGND VDD 1Y0 1Y1 1Y2 GND GND 1 2 3 4 24 23 22 21 • CLK AVDD VDD 2Y0 2Y1 GND GND 2Y2 2Y3 VDD 2G FBIN • FS612509 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 Figure 1: Block Diagram VDD 1Y3 1Y4 VDD 1G FBOUT 1G 1Y0 1Y1 AVDD 1Y2 1Y3 Table 1: Function Table INPUT PLL AVDD 1G L L H H H L L H H H 2G L H L H H L H L H H CLK H H H H L H H H H L 1Y0-1Y4 L L H H L L L H H L 2Y0-2Y3 L H L H L L H L H L FBOUT H H H H L H H H H L 11.29.00 FBIN PLL CLK AGND 1Y4 2Y0 2Y1 2Y2 OUTPUT 2G PLL Bypass H H H H H L L L L L 2Y3 FS612509 FBOUT GND This document contains information on a new product. Specifications and information herein are subject to change without notice. ISO9001 QS9000 Zero-Delay FS612509-01/-02 1:9 Zero-Delay Clock Buffer IC AMERICAN MICROSYSTEMS, INC. November 2000 Table 2: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN 11 14 3 4 5 8 9 21 20 17 16 23 1 24 13 12 6, 7, 18, 19 2, 10, 15, 22 TYPE DI DI DO DO DO DO DO DO DO DO DO P P DI DI DO P P NAME 1G 2G 1Y0 1Y1 1Y2 1Y3 1Y4 2Y0 2Y1 2Y2 2Y3 AVDD AGND CLK FBIN FBOUT GND VDD DESCRIPTION Output enable stops Bank 1 clocks (1Y0 – 1Y4) in a low state when this pin is low Output enable stops Bank 2 clocks (2Y0 – 2Y3) in a low state when this pin is low Clock output Clock output Clock output Clock output Clock output Clock output Clock output Clock output Clock output Power Supply / Test mode enable. This pin provides the power supply to the internal PLL. When the pin is pulled low, the PLL is bypassed and the output clocks directly follow the input clock PLL supply ground Reference clock input (Note: -02 version has a pull-down on this pin) Feedback clock input, connected to FBOUT to complete the loop Feedback output clock Ground for all clock outputs Power supply for all clock outputs Bank 2 Enabled by 2G Bank 1 Enabled by 1G ISO9001 QS9000 2 FS612509-01/-02 AMERICAN MICROSYSTEMS, INC. 1:9 Zero-Delay Clock Buffer IC November 2000 3.0 Device Operation The FS612509 is a zero-delay buffer intended for use on buffered PC133 SDRAM DIMMs. The FS612509 precisely aligns the frequency and phase of the output clocks to the input CLK by use of an on-chip phase-lock loop (PLL). The PLL generates up to 9 lowskew, low-jitter copies of the CLK, with the outputs adjusted for 50% duty cycle. The FBOUT clock must be hardwired to the FBIN pin to complete the loop. The PLL actively adjusts the output clocks so that there is no phase error between the reference clock (CLK) and the feedback clock (FBIN). Since the device uses a PLL to lock the output clocks to the input clock, there is a power-up stabilization time that is required for the PLL to achieve phase lock. Note that all inputs and outputs use LVCMOS signal levels. logic-high on 1G enables the Bank 1 outputs to swing in phase with the reference clock CLK. A logic-low on 1G forces the Bank 1 to a logic-low state. A second bank of four clock outputs consists of 2Y0 to 2Y3, and the clocks are enabled or disabled by the 2G signal. A logic-high on 2G enables the Bank 2 outputs to swing in phase with the reference clock CLK. A logic-low on 2G forces the Bank 2 to a logic-low state. The function table Table 1 shows the effect of the 1G and 2G enable signals on the clock outputs. 4.0 Tracking Skew PLL-based buffer ICs may be required to follow a spreadspectrum modulated reference clock for frequencies greater than 66MHz. Spread spectrum modulation limits peak EMI emissions by intentionally introducing jitter onto a clock signal, effectively spreading the peak energy over a range of frequencies. A downstream PLL, contained in a clock buffer IC such as this one, must carefully track the modulated input reference clock. A measure of how closely the downstream PLL follows the modulated clock is called the tracking skew. To ensure a tight tracking skew, the loop bandwidth of a downstream PLL is increased and the loop phase angle is reduced over that of typical PLL-based clock generators. The type of modulation profile used impacts tracking skew. The maximum frequency change occurs at the profile limits where the modulation changes the slew rate polarity. To track the sudden reversal in clock frequency, the downstream PLL must have a large loop bandwidth. The ability of the downstream PLL to catch up to the modulating clock is determined by the loop transfer function phase angle. The spread-spectrum reference clock should be either a triangle-wave or a non-linear modulation profile, with a modulation frequency of 50kHz or less. 3.1 PLL Bypass When the AVDD pin is pulled low, the reference clock signal bypasses the PLL and is brought directly through to the outputs. The PLL is powered down, and device acts a fanout buffer. Note that if AVDD is re-established, the PLL requires a power-up and stabilization time to lock to the input clock. 3.2 Power-Down The FS612509-02 version provides an auto power-down feature that shuts off the PLL, drives all outputs low, and places the device into a low current state if the reference clock stops. The power-down circuit is level sensitive, and detects either a DC high or low on the CLK input. 3.3 Bank Output Enable/Disable Two banks of clock outputs are available on this device. Each bank is independently enabled or disabled by the 1G or 2G enable signals. The first bank consists of five outputs 1Y0 to 1Y4, and the clocks are enabled or disabled by the 1G signal. A ISO9001 QS9000 3 FS612509-01/-02 1:9 Zero-Delay Clock Buffer IC AMERICAN MICROSYSTEMS, INC. November 2000 5.0 Electrical Specifications Table 3: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER Supply Voltage, dc, Clock Buffers (VSS = ground) Supply Voltage, dc, Core Input Voltage, dc Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI > VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) SYMBOL AVDD VDD VI VO IIK IOK TS TA TJ MIN. VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 -50 -50 -65 -55 MAX. 7 7 VDD + 0.5 VDD + 0.5 50 50 150 125 125 260 2 UNITS V V V V mA mA °C °C °C °C kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 4: Operating Conditions PARAMETER Supply Voltage, Core and Outputs Ambient Operating Temperature Range Output Load Capacitance Input Frequency Input Duty Cycle Input Rise/Fall Time SYMBOL VDD TA CL fCLK CLK CLK CLK 50 40 CONDITIONS/DESCRIPTION 3.3V ± 10% MIN. 3.0 0 TYP. 3.3 MAX. 3.6 70 15 140 60 3 UNITS V °C pF MHz % ns ISO9001 QS9000 4 FS612509-01/-02 AMERICAN MICROSYSTEMS, INC. 1:9 Zero-Delay Clock Buffer IC November 2000 Table 5: DC Electrical Specifications Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device. PARAMETER Overall Supply Current, Dynamic Supply Current, Static Output Enable Input (1G, 2G) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Clock Inputs (CLK, FBIN) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Loading Capacitance * Clock Outputs (1Y0:4, 2Y0:3, FBOUT) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Source Current * Short Circuit Sink Current * SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS fCLK = 133.33MHz; VDD = 3.3V IDDL VIH VIL II VIH VIL II CL(in) -01 version -02 version has a pull-down on CLK As seen by an external clock driver Outputs low; VDD = 3.3V 2.0 VSS-0.3 -5 130 3 mA mA VDD+0.3 0.8 5 V V µA V V µA pF 2.0 VSS-0.3 -5 28 4 VDD+0.3 0.8 5 IOH IOL zO IOZ IOSH IOSL VDD = 2.9V, VO = 2.0V VDD = 3.7V, VO = 2.0V VDD = 2.9V, VO = 0.8V VDD = 3.7V, VO = 0.8V 12 12 -10 VO = 0V; shorted for 30s, max. VO = 3.3V; shorted for 30s, max. -18 -35 16 17 33 -12 -12 mA mA Ω 10 -60 90 µA mA mA Table 6: Clock Output Drive (1Y0:4, 2Y0:3, FBOUT) Voltage 0.1 V 0.2 V 0.4 V 0.6 V 0.8 V 1.0 V 1.2 V 1.4 V 1.6 V 1.8 V 2.0 V 2.2 V 2.4 V 2.6 V 2.8 V 3.0 V 3.3 V 3.6 V Low Drive Current (mA) -47 -45 -43 -40 -38 -35 -32 -29 -26 -22 -18 -15 -10 -6 -2 0 -59 -58 -56 -55 -52 -50 -47 -45 -41 -38 -35 -31 -28 -24 -20 -15 -9 -2 High Drive Current (mA) 2 4 8 12 16 20 24 27 31 34 38 41 43 45 48 49 2 4 9 13 17 21 25 29 33 36 40 43 46 49 51 53 56 59 60 45 30 Output Current (mA) 15 0 0 -15 -30 -45 -60 0.5 1 1.5 2 2.5 3 3.5 30Ω Output Voltage (V) 50Ω 90Ω ISO9001 QS9000 5 FS612509-01/-02 1:9 Zero-Delay Clock Buffer IC AMERICAN MICROSYSTEMS, INC. November 2000 Table 7: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. PARAMETER Overall Skew, Output to Output * Skew, Tracking * Static Phase Error * Clock Stabilization Time * Loop Bandwidth * Phase Angle * SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS tsk(o) Measured on the rising edge at 1.65V; CL = 15pF Measured using a –0.5% 31.5kHz spread spectrum reference clock at 133.33MHz From rising edge on CLK to rising edge on FBIN Time required for the PLL to achieve phase lock For calculation of Tracking Skew For calculation of Tracking Skew -120 150 150 ps ps ps 3 1.2 -0.031 ms MHz ° Clock Outputs (1Y0:4, 2Y0:3, FBOUT) Duty Cycle * Jitter, Cycle-Cycle * Jitter, Period (peak-peak) * Rise Time * Fall Time * Enable Delay * Disable Delay * dt tj(CC) tj(∆P) tr tf tDLH tDHL Ratio of high pulse width to one clock period, measured at 1.65V Adjacent cycles at 1.65V From rising edge to next rising edge at 1.65V VO = 0.4V to 2.0V; CL = 15pF VO = 2.0V to 0.4V; CL = 15pF via 1G or 2G via 1G or 2G 1 1 1.2 1.4 10 10 ns ns ns ns 45 -75 55 +75 % ps Figure 3: Clock Skew Measurement Any output 50% VDD clock skew (tsk(o)) Any output 50% VDD Figure 4: Phase Error Measurement CLK 50% VDD phase error FBIN 50% VDD Figure 5: Timing Measurement Points tr tf 3.3V 2.4V Figure 6: Output Enable Measurement VDD Output Enable 50% 50% VSS 50% VDD 0.4V 50% Output dt 10% tDLZ 90% VOL tDZL VOH 50% tDHZ tDHZ ISO9001 QS9000 6 FS612509-01/-02 AMERICAN MICROSYSTEMS, INC. 1:9 Zero-Delay Clock Buffer IC November 2000 6.0 Package Information Table 8: 24-pin TSSOP Package Dimensions DIMENSIONS INCHES MIN. A A1 A2 b C D E1 E e L S θ1 θ2 θ3 0.002 0.0315 0.0075 0.0035 0.303 0.169 MAX. 0.047 0.006 0.0413 0.0118 0.0079 0.311 0.177 MILLIMETERS MIN. 0.05 0.80 0.19 0.09 7.70 4.30 MAX. 1.20 0.15 1.05 0.30 0.20 7.90 4.50 1 24 E1 E AMERICAN MICROSYSTEMS, INC. 0.252 0.0256 0.0177 0.0079 0° 12 REF 12 REF 0.0295 8° 6.40 BSC 0.65 BSC 0.45 0.20 0° 12 REF 12 REF 0.75 8° b e A2 D A1 A c S θ2 L SEATING PLANE θ3 θ1 BASE PLANE Table 9: 24-pin TSSOP Package Characteristics PARAMETER Thermal Impedance, Junction to Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL ΘJA L11 L12 L13 C11 C12 C13 CONDITIONS/DESCRIPTION Air flow = 0 m/s Longest lead Longest lead to any 1 adjacent lead Longest lead to any 2nd adjacent lead Longest lead to VSS Longest lead to any 1st adjacent lead Longest lead to any 2nd adjacent lead st TYP. 84 1.7 0.6 0.24 0.3 0.1 0.007 UNITS °C/W nH nH pF pF ISO9001 QS9000 7 FS612509-01/-02 1:9 Zero-Delay Clock Buffer IC AMERICAN MICROSYSTEMS, INC. November 2000 7.0 Ordering Information Table 10: Device Ordering Codes DEVICE NUMBER FS612509-01 FS612509-02 ORDERING CODE PACKAGE TYPE 24-pin TSSOP (Thin Shrink Small Outline Package) 24-pin TSSOP (Thin Shrink Small Outline Package) OPERATING TEMPERATURE RANGE 0°C to 70°C (Commercial) 0°C to 70°C (Commercial) SHIPPING CONFIGURATION Tape and Reel Tape and Reel 12055-802 12055-803 Copyright © 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ISO9001 QS9000 8