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FS6209-01

FS6209-01

  • 厂商:

    ETC

  • 封装:

  • 描述:

    FS6209-01 - DUAL PLL VCXO CLOCK GENERATOR IC - List of Unclassifed Manufacturers

  • 数据手册
  • 价格&库存
FS6209-01 数据手册
     X  T 'XDO 3// 9&;2 &ORFN *HQHUDWRU ,& 3UHOLPLQDU\ ,QIRUPDWLRQ )6 February 1999 1.0 • • • • • Features 2.0 Description Dual phase-locked loop (PLL) device two output clock frequencies On-chip tunable voltage-controlled crystal oscillator (VCXO) allows precise system frequency tuning 3.3V supply voltage Small circuit board footprint (8-pin 0.150″ SOIC) Custom frequency selections available - contact your local AMI Sales Representative for more information Figure 1: Pin Configuration XIN VDD XTUNE VSS 1 8 XOUT VSS CLKB CLKA 2 3 4 7 6 5 The FS6209 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital video/audio systems. At the core of the FS6209 is circuitry that implements a voltage-controlled crystal oscillator when an external resonator (nominally 13.5MHz) is attached. The VCXO allows device frequencies to be precisely adjusted for use in systems that have frequency matching requirements, such as digital satellite receivers. Two high-resolution phase-locked loops generate two output clocks (CLKA and CLKB) through an array of postdividers. All frequencies are ratiometrically derived from the VCXO frequency. The locking of all the output frequencies together can eliminate unpredictable artifacts in video systems and reduce electromagnetic interference (EMI) due to frequency harmonic stacking. 8-pin (0.150″) SOIC Figure 2: Block Diagram FS6209 Table 1: Crystal / Output Frequencies DEVICE FS6209-01 fXIN (MHz) 13.5 CLKA (MHz) 54 CLKB (MHz) 22.5792 (+1.12ppm) NOTE: Contact AMI for custom PLL frequencies XIN VCXO XOUT XTUNE PLL DIVIDER ARRAY PLL CLKA CLKB FS6209 This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. ,62 2.4.99 )6 'XDO 3// 9&;2 &ORFN *HQHUDWRU ,& 3UHOLPLQDU\ ,QIRUPDWLRQ Table 2: Pin Descriptions      X  T February 1999 Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN 1 2 3 4 5 6 7 8 TYPE AI P AI P DO DO DO AO NAME XIN VDD XTUNE VSS CLKA CLKB VSS XOUT VCXO Feedback Power Supply (+3.3V) VCXO Tune Ground Clock Output A Clock Output B Ground VCXO Drive DESCRIPTION 3.0 3.1 Functional Block Description Phase-Locked Loop (PLL) The on-chip PLLs are a standard frequency- and phaselocked loop architecture. The PLL multiplies the reference oscillator to the desired frequency by a ratio of integers. The frequency multiplication is exact with a zero synthesis error. the oscillator circuit. The actual amount that changing the load capacitance alters the oscillator frequency will be dependent on the characteristics of the crystal as well as the oscillator circuit itself. Specifically, the motional capacitance of the crystal (usually referred to by crystal manufacturers as C1), the static capacitance of the crystal (C0), and the load capacitance (CL) of the oscillator determine the warping capability of the crystal in the oscillator circuit. A simple formula to obtain the warping capability of a crystal oscillator is: 3.2 Voltage-Controlled Crystal Oscillator (VCXO) ∆f ( ppm) = The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6209 system components. Loading capacitance for the crystal is internal to the FS6209. No external components (other than the resonator itself) are required for operation of the VCXO. Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. The total change (from one extreme to the other) in effective loading capacitance is t.b.d. nominal. The oscillator operates the crystal resonator in the parallel-resonant mode. Crystal warping, or the “pulling” of the crystal oscillation frequency, is accomplished by altering the effective load capacitance presented to the crystal by 6 C1 × (C L 2 − C L1)× 10 2 × (C 0 + C L 2 )× (C 0 + C L1) where CL1 and CL2 are the two extremes of the applied load capacitance. EXAMPLE: A crystal with the following parameters is used. With C1 = 0.02pF, C0 = 5pF, CL1 = 10pF, and CL2 = 22.66pF, the coarse tuning range is ∆f = 0.02 × (22.66 − 10)× 10 6 = 305 ppm . 2 × (5 + 22.66 )× (5 + 10 ) ,62 2 2.4.99      X  T 'XDO 3// 9&;2 &ORFN *HQHUDWRU ,& 3UHOLPLQDU\ ,QIRUPDWLRQ )6 February 1999 4.0 Electrical Specifications Table 3: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER Supply Voltage (VSS = ground) Input Voltage, dc Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI > VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) SYMBOL VDD VI VO IIK IOK TS TA TJ MIN. VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55 MAX. 7 VDD+0.5 VDD+0.5 50 50 150 125 125 260 2 UNITS V V V mA mA °C °C °C °C kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 4: Operating Conditions PARAMETER Supply Voltage Ambient Operating Temperature Range SYMBOL VDD TA CONDITIONS/DESCRIPTION 3.3V ± 10% MIN. 3.0 0 TYP. 3.3 MAX. 3.6 70 UNITS V °C ,62 3 2.4.99 )6 'XDO 3// 9&;2 &ORFN *HQHUDWRU ,& 3UHOLPLQDU\ ,QIRUPDWLRQ Table 5: DC Electrical Specifications      X  T February 1999 Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device. PARAMETER Overall Supply Current, Dynamic, with Loaded Outputs Voltage Controlled Crystal Oscillator Crystal Resonator Frequency Crystal Loading Capacitance Crystal Resonator Motional Capacitance VCXO Tuning Range VCXO Tuning Characteristic Crystal Drive Level Clock Outputs (CLKA, CLKB, CLKC) High-Level Output Source Current * Low-Level Output Sink Current * Output Impedance * Short Circuit Source Current * Short Circuit Sink Current * SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS IDD fXTAL = 13.5MHz; CL = 10pF 20 mA fXTAL CL(xtal) C1(xtal) Fundamental Mode As seen by a crystal connected to XIN and XOUT (@ VXTUNE = 1.65V) AT cut fXTAL = 13.5MHz; CL = 20pF; CMOT = 25fF Note: positive -F for positive -V RXTAL=20 ohm; CL = 20pF 5. 13.5 20 25 300 100 200 18 MHz pF fF ppm ppm/V uW IOH IOL zOH zOL IOSH IOSL VO = 2.0V VO = 0.4V VO = 0.1VDD; output driving high VO = 0.1VDD; output driving low VO = 0V; shorted for 30s, max. VO = 3.3V; shorted for 30s, max. 40 17 25 25 55 55 mA mA Ω mA mA Table 6: AC Timing Specifications Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. PARAMETER Clock Outputs (CLKx) Duty Cycle * Jitter, Absolute Period (pk-pk) * Jitter, RMS Long Term (σy(τ)) * Rise Time * Fall Time * Output Frequency Synthesis Error VCXO Stabilization Time * PLL Stabilization Time * SYMBOL CONDITIONS/DESCRIPTION CLOCK (MHz) MIN. TYP. MAX. UNITS thi / tclk; Measured at VDD/2 tj(∆P) tj(LT) tr tf tVCXOSTB tPLLSTB From rising edge to next rising edge at VDD/2, CL = 10pF From 0-500µs at VDD/2, CL = 10pF compared to ideal clock source VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF (unless otherwise noted in Frequency Table) From power valid From VCXO stable 43 300 150 1 1 57 % ps ps ns ns 0 10 500 ppm ms us ,62 4 2.4.99      X  T 'XDO 3// 9&;2 &ORFN *HQHUDWRU ,& 3UHOLPLQDU\ ,QIRUPDWLRQ )6 February 1999 5.0 Package Information Table 7: 8-pin SOIC (0.150") Package Dimensions DIMENSIONS INCHES MIN. A A1 A2 B C D E e H h L Θ 0.061 0.004 0.055 0.013 0.0075 0.189 0.150 0.230 0.010 0.016 0° MAX. 0.068 0.0098 0.061 0.019 0.0098 0.196 0.157 0.244 0.016 0.035 8° MILLIMETERS MIN. 1.55 0.102 1.40 0.33 0.191 4.80 3.81 5.84 0.25 0.41 0° MAX. 1.73 0.249 1.55 0.49 0.249 4.98 3.99 6.20 0.41 0.89 8° BASE PLANE 1 ALL RADII: 0.005" TO 0.01" R 8 E H ÅÉ"ÇÅÃÇ"#)#$É#ˆÃDŽ h x 45° B e A2 A D A1 SEATING PLANE 7° typ. 0.050 BSC 1.27 BSC C L θ Table 8: 8-pin SOIC (0.150") Package Characteristics PARAMETER Thermal Impedance, Junction to Free-Air 8-pin 0.150” SOIC Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk SYMBOL ΘJA L11 L12 C11 CONDITIONS/DESCRIPTION Air flow = 0 m/s Corner lead Center lead Any lead to any adjacent lead Any lead to VSS TYP. 110 2.0 1.6 0.4 0.27 UNITS °C/W nH nH pF ,62 5 2.4.99 )6 'XDO 3// 9&;2 &ORFN *HQHUDWRU ,& 3UHOLPLQDU\ ,QIRUPDWLRQ      X  T February 1999 6.0 Ordering Information DEVICE NUMBER PACKAGE TYPE 8-pin (0.150”) SOIC (Small Outline Package) 8-pin (0.150”) SOIC (Small Outline Package) OPERATING TEMPERATURE RANGE 0°C to 70°C (Commercial) 0°C to 70°C (Commercial) SHIPPING CONFIGURATION Tape and Reel Tubes ORDERING CODE 11640-801 11640-811 FS6209-01 FS6209-01 Copyright © 1998 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ,62 6 2.4.99
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