FS6232-01

FS6232-01 AMERICAN MICROSYSTEMS, INC. Two-Way MP Motherboard Clock Generator IC September 2000 1.0 • Features Figure 1: Block Diagram XIN XOUT ISEL_0:1 IREF ÷1 PWR_DWN# SS_EN# SEL133/100# SEL_A:B SSCG PLL Control ÷2 ÷3 ÷4 delay Generates all clocks required for single and two-way multi-processor (MP) platforms, including: M Four differential current-mode Host clock pairs M Four 66.67MHz 3.3V CK66 clock outputs M Ten 33.3MHz 3.3V PCI clock outputs M Two 3.3V Memory Reference clock outputs M Two 48MHz 3.3V CK48 clock outputs M Two buffered copies of the crystal reference Control of current-mode Host clocks via IREF current programming pin and ISEL_0:1 current multiplier pins Host clock frequency selection via the SEL_A, SEL_B, and SEL133/100# pins Active-low PWR_DWN# signal allows one complete clock cycle on each clock outputs and then shuts down the crystal oscillator, PLLs, and outputs Spread-spectrum modulation (-0.5% at 31.5kHz) of SSCG PLL clocks, enabled via SS_EN# input Supports test mode and tristate output control to facilitate board testing Available in a 56-pin SSOP and TSSOP Crystal Oscillator adjust VDD_R REF_0:1 VSS_R VDD_H HOST_P1:4 HOST_N1:4 VSS_H VDD_66 • • • CK66_0:3 VSS_66 VDD_P ÷2 PCI_0:9 VSS_P VDD_M ÷4 MREF_P MREF_N VSS_M VDD_48 • • • PLL CK48_0:1 VSS_48 FS6232 Figure 2: Pin Configuration VSS_R 1 56 VDD_M 55 MREF_P 54 MREF_N 53 VSS_M 52 SS_EN# 51 HOST_P1 50 HOST_N1 49 VDD_H 48 HOST_P2 47 HOST_N2 46 VSS_H 45 HOST_P3 44 HOST_N3 43 VDD_H 42 HOST_P4 41 HOST_N4 40 VSS_H 39 IREF 38 VDD 37 VSS 36 VDD_66 35 CK66_0 34 CK66_1 33 VSS_66 32 VSS_66 31 CK66_2 30 CK66_3 29 VDD_66 REF_0 / ISEL_0 2 REF_1 / ISEL_1 3 Table 1: Clock Parameters CLOCK GROUP HOST_P HOST_N MREF_P MREF_N CK66 PCI CK48 REF # PINS 4 4 1 1 4 10 2 2 3.3V VDD_H SUPPLY VOLTAGE SUPPLY GROUP FREQ. (MHz) 133.33 100.00 66.67 50.00 66.67 33.33 48.008 14.318 PHASE 0° 180° 0° 180° 0° 0° 0° 0° SKEW (MAX) 150ps Pair to Pair 250ps 300ps - VDD_R 4 XIN 5 XOUT 6 VSS_P 7 PCI_0 8 PCI_1 9 VDD_P 10 PCI_2 11 PCI_3 12 VSS_P 13 PCI_4 14 PCI_5 15 VDD_P 16 PCI_6 17 PCI_7 18 Pair 1 Pair 2 3.3V 3.3V 3.3V 3.3V 3.3V VDD_M VDD_66 VDD_P VDD_48 VDD_R Pair 3 FS6232-01 Pair 4 Table 2: Clock Offsets RELATION CK66 leads PCI PHASE 0° MIN 1.5ns TYP MAX 3.5ns VSS_P 19 PCI_8 20 PCI_9 21 VDD_P 22 SEL133/100# 23 VSS_48 24 CK48_0 / SEL_A 25 CK48_1 / SEL_B 26 VDD_48 27 PWR_DWN# 28 Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. ISO9001 9.18.00 IntSKS FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 3: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active-low pin PIN 25 26 35, 34, 31, 30 50, 51 47, 48 44, 45 41, 42 39 54 55 8, 9, 11, 12, 14, 15, 17, 18, 20, 21 28 2 TYPE DIO DIO DO AO AO AO AO AI DO DO DO DI DIO NAME CK48_0 SEL_A CK48_1 SEL_B CK66_0:3 HOST_P1 HOST_N1 HOST_P2 HOST_N2 HOST_P3 HOST_N3 HOST_P4 HOST_N4 IREF MREF_N MREF_P PCI_0:9 PWR_DWN# REF_0 ISEL_0 REF_1 DESCRIPTION One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL One of two latched inputs that select the HOST and MREF output frequency One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL One of two latched inputs that select the HOST and MREF output frequency Four 3.3V 66.67MHz clock outputs, generated from the spread spectrum PLL Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1 Host clock pair #2; one of six pairs of current-steering differential current-mode outputs Host clock pair #3; one of six pairs of current-steering differential current-mode outputs Host clock pair #4; one of six pairs of current-steering differential current-mode outputs A fixed precision resistor from this pin to ground provides a reference current used for the differential current-mode HOST clock outputs One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock to a memory clock driver One clock in a pair of outputs provided as a reference clock to a memory clock driver Ten 3.3V 33.3MHz PCI clocks, lagging the CK66 clock by 1.5 to 3.5ns Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all clocks in low state. Complete clock cycles on all outputs will occur before shut down begins. One of two 3.3V buffered copies of the crystal reference frequency clock One of two latched inputs that select the multiplying factor of the IREF reference current for the HOST pair outputs One of two 3.3V buffered copies of the crystal reference frequency clock One of two latched inputs that select the multiplying factor of the IREF reference current for the HOST pair outputs Selects 133MHz (logic high) or 100MHz (logic low) Host clock frequency Active low spread-spectrum enable turns on spread spectrum modulation 3.3V core power supply 3.3V power supply for CK48 clock outputs 3.3V power supply for CK66 clock outputs 3.3V power supply for the differential HOST clock outputs 3.3V power supply for MREF clock outputs 3.3V power supply for PCI clock outputs 3.3V power supply for the REF clock output and the crystal oscillator Core ground Ground for the CK48 clock outputs Ground for the CK66 clock outputs Ground for the differential HOST clock outputs Ground for the MREF clock outputs Ground for the PCI clock outputs Ground for the REF clock outputs and the crystal oscillator 14.318MHz crystal oscillator input 14.318MHz crystal oscillator output SUPPLY VDD_48 VDD_48 VDD_66 VDD_H VDD_H VDD_H VDD_H VDD VDD_M VDD_M VDD_P VDD_48 VDD_R 3 23 52 38 27 29, 36 43, 49 56 10, 16, 22 4 37 24 32, 33 40, 46 53 7, 13, 19 1 5 6 DIO DI DI P P P P P P P P P P P P P P AI AO ISEL_1 SEL133/100# SS_EN# VDD VDD_48 VDD_66 VDD_H VDD_M VDD_P VDD_R VSS VSS_48 VSS_66 VSS_H VSS_M VSS_P VSS_R XIN XOUT VDD_R VDD_48 VDD_M VDD_R VDD_R ISO9001 9.18.00 2 FS6232-01 AMERICAN MICROSYSTEMS, INC. Two-Way MP Motherboard Clock Generator IC September 2000 2.0 Programming Information Table 4: Function/Clock Enable Configuration CONTROL INPUTS PWR_ DWN# 1 1 1 1 1 1 1 1 0 SEL 133/100# 0 0 0 0 1 1 1 1 X SEL_A 0 0 1 1 0 0 1 1 X SEL_B 0 1 0 1 0 1 0 1 X HOST_P 1:4 100.00 reserved reserved tristate 133.33 reserved reserved XIN ÷ 2 2 × IREF HOST_N 1:4 100.00 reserved reserved tristate 133.33 reserved reserved XIN ÷ 2 tristate CLOCK OUTPUTS (MHz) MREF_P, MREF_N 50.00 reserved reserved tristate 66.67 reserved reserved XIN ÷ 4 low CK66_ 0:3 66.67 reserved reserved tristate 66.67 reserved reserved XIN ÷ 4 low PCI_ 0:9 33.33 reserved reserved tristate 33.33 reserved reserved XIN ÷ 8 low CK48_ 0:1 48.008 reserved reserved tristate 48.008 reserved reserved XIN ÷ 2 low REF 14.318 reserved reserved tristate 14.318 reserved reserved XIN low Table 5: Synthesis Error CLOCK HOST_P1:4, HOST_N1:4 MREF_P, MREF_N CK66 PCI CK48 (1) 1. 2. 3.1 ACTUAL (MHz) 99.9963 133.3072 49.9982 66.6536 66.6642 33.3321 48.008 DEVIATION (ppm) -36.657 -195.924 -36.657 -195.924 -36.657 -36.657 +167 Current Reference TARGET (MHz) 100.0000 133.3333 50.0000 66.6667 66.6667 33.3333 48.000 The HOST output current is a mirrored and scaled copy of the reference current flowing through the programming resistor on the IREF pin. Conceptually, the circuit given in Figure 2 shows how the mirror current is generated. The voltage that appears at the IREF pin is one-third of the voltage at the VDD_I pin. The reference current is I REF 1   × VDD_I  3 . = RIREF 48MHz USB clock is required to be +167ppm off from 48.000MHz to conform to USB standards. Spread spectrum is disabled 3.2 Current Scaling 3.0 HOST Buffer Current Control The current supplied at the HOST outputs is controlled by two parameters: 1) the value of the programming resistor from the IREF pin to ground (VSS), and 2) the multiplier factor determined by the logic setting of the ISEL_0 and ISEL_1 pins. The mirrored reference current can be increased by adding one or more copies of the mirror current together. The additional current is controlled by the logic settings on the ISEL_0 and ISEL_1 pins. Table 6: Current Multiplier ISEL_0 0 0 1 1 ISEL_1 0 1 0 1 MULTPLIER IO = 5 × IREF IO = 6 × IREF IO = 4 × IREF IO = 7 × IREF ISO9001 9.18.00 3 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Figure 2: Current Reference Circuit VDD_I (3.3V) 2R 1.1V Table 8: HOST Buffer Clock Output Additional Mirror Current Output Voltage (V) 3.30 3.14 2.97 2.81 HIGH DRIVE CURRENT (mA) AT PRIMARY SYSTEM CONFIGURATION MIN. 0.00 -3.03 -5.66 -7.87 -9.67 -11.05 -11.98 -12.52 -12.77 -12.91 -12.99 -13.04 -13.07 -13.08 -13.09 -13.11 -13.12 -13.13 -13.13 -13.14 -13.15 TYP. 0.00 -4.22 -7.68 -10.30 -11.91 -12.56 -12.85 -13.07 -13.26 -13.42 -13.54 -13.64 -13.70 -13.73 -13.75 -13.76 -13.78 -13.79 -13.80 -13.81 -13.82 MAX. 0.00 -5.76 -9.86 -11.85 -12.45 -12.84 -13.16 -13.45 -13.72 -13.96 -14.17 -14.36 -14.52 -14.64 -14.71 -14.74 -14.76 -14.78 -14.80 -14.82 -14.83 R Mirror Current ISEL_0:1 IREF Reference Current IREF RIREF HOST_N RS RP HOST_P RS RP 2.64 2.48 2.31 2.14 1.98 1.81 1.65 Table 7: HOST Current Selection PROGRAM RESISTOR RIREF 475 Ω (1%) 475 Ω (1%) 475 Ω (1%) 475 Ω (1%) 221 Ω (1%) 221 Ω (1%) 221 Ω (1%) 221 Ω (1%) REFERENCE CURRENT CURRENT MULTIPLIER IREF 2.32mA 2.32mA 2.32mA 2.32mA 5mA 5mA 5mA 5mA IO = 5 × IREF IO = 6 × IREF IO = 4 × IREF IO = 7 × IREF IO = 5 × IREF IO = 6 × IREF IO = 4 × IREF IO = 7 × IREF TRACE IMPEDANCE 60 Ω 50 Ω 60 Ω 50 Ω 60 Ω 50 Ω 60 Ω 50 Ω 30 Ω 25 Ω 30 Ω 25 Ω 30 Ω 25 Ω 30 Ω 25 Ω OUTPUT VOLTAGE 0.71V 0.59V 0.85V 0.71V 0.56V 0.47V 0.99V 0.82V 0.75V 0.62V 0.75V 0.60V 0.50V 1.05V 0.84V 0.90V 1.48 1.32 1.15 0.99 0.82 0.66 0.49 0.33 0.16 0.00 Output Voltage (V) 0 0 -2 1 2 3 Output Current (mA) -4 -6 -8 -10 -12 -14 -16 -18 -20 NOTE: Shaded row indicates the Primary System Configuration 30Ω 50Ω 90Ω Max VOH Data in this table represents nominal characterization data only ISO9001 9.18.00 4 FS6232-01 AMERICAN MICROSYSTEMS, INC. Two-Way MP Motherboard Clock Generator IC September 2000 4.0 Power Management Table 9: Latency Table SIGNAL SIGNAL STATE Power OFF Power ON Output: Device: LATENCY MIN. 2 clocks 2× REF clocks 3ms MAX. 3 clocks 3× REF clocks The PWR_DWN# signal is an asynchronous, active-low LVTTL input that places the device in a low power inactive state without removing power from the device. All internal clocks are turned off, and all clock outputs are held low. Since PWR_DWN# is asynchronous, the signal is synchronized internally to each individual clock. As shown in Figure 3, a falling-rising-falling edge sequence on any individual clock output is required before that clock output is disabled low. This edge sequence ensures that one complete clock cycle will occur before the clock stops. PWR_ DWN# 0 1 Upon the release of PWR_DWN# (power-up), external circuitry should allow a minimum of 3ms for the PLL to lock before enabling any clocks. Figure 3: PWR_DWN# Timing Any Clock (internal) PWR_DWN# Any Clock (output) After REF output shuts off... VCO Crystal Oscillator Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active. 3ms until clock is valid 5.0 Dual Function I/O Pins Figure 4: I/O Pin Programming Termination Resistor Device Solder Pads Several pins on this device serve as dual function input/output pins. During the initial application of VDD to the device, this type of pin functions as an input pin. Upon completion of power-up, the logic state present on the pin is latched internally, and the pin is converted to an output driver. An external 10kΩ pull-down resistor to ground is required for a logic low and a 10kΩ pull-up resistor to the clock output VDD is required for a logic high. The 10kΩ resistor presents an insignificant load to the output driver that should not affect the output clock. Note that the latching of the logic state occurs only on the application of the chip supply voltage (VDD). The logic state on the pin is not latched if the PWR_DWN# signal is used to power-down the device with VDD still applied. Clock Trace 10kΩ Programming Resistor Ground or Power Via ISO9001 9.18.00 5 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 6.0 Electrical Specifications Table 10: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER Supply Voltage (VSS = ground) Input Voltage, dc Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI > VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) SYMBOL VDD VI VO IIK IOK TS TA TJ MIN. VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55 MAX. 7 VDD+0.5 VDD+0.5 50 50 150 125 125 260 2 UNITS V V V mA mA °C °C °C °C kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 11: Operating Conditions PARAMETER Supply Voltage Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance SYMBOL VDD TA fXTAL CXL XIN, XOUT pins MREF_P, MREF_N PCI_0:9 Load Capacitance CL CK66_0:3 CK48_0:1 REF_0:1 Load Resistance Maximum High-Level Output Voltage RL VOH HOST_P1 to HOST_P4, HOST_N1 to HOST_N4 HOST_P1 to HOST_P4, HOST_N1 to HOST_N4 CONDITIONS/DESCRIPTION Core (VDD) Clock Buffers (VDD_48, VDD_66, VDD_H, VDD_M, VDD_P, VDD_R) MIN. 3.135 3.135 0 14.316 13.5 10 10 10 10 10 20 14.318 18 TYP. 3.3 3.3 MAX. 3.465 3.465 70 14.32 22.5 30 30 30 20 20 105 1.20 Ω V pF V °C MHz pF UNITS ISO9001 9.18.00 6 FS6232-01 AMERICAN MICROSYSTEMS, INC. Two-Way MP Motherboard Clock Generator IC September 2000 Table 12: DC Electrical Specifications Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical. Negative currents indicate current flows out of the device. PARAMETER Overall Supply Current, Dynamic, with Loaded Outputs Supply Current, Static SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS IDD IDDs fHOST=133MHz; VDD=3.465V, RIREF=475Ω, IOH=6IREF fHOST=100MHz; VDD=3.465V, RIREF=475Ω, IOH=6IREF 260 250 mA µA PWR_DWN# low, all supplies = 3.465V, RIREF= 475 Ω, IOH = 6 × IREF 2.0 VSS-0.3 -5 VDD+0.3 0.8 +5 Digital Inputs (PWR_DWN#, SEL133/100#, SS_EN#) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Crystal Oscillator Feedback (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current Crystal Loading Capacitance * Input Loading Capacitance * Crystal Oscillator Drive (XOUT) High Level Output Source Current Low Level Output Sink Current Current Reference (IREF) Bias Voltage Short Circuit Output Source Current VOH IOH no load VO = 0V VDD_M, VDD_66, VDD_P = 3.135V, VO = 1.0V VDD_M, VDD_66, VDD_P = 3.465V, VO = 3.135V VDD_M, VDD_66, VDD_P = 3.135V, VO = 1.95V VDD_M, VDD_66, VDD_P = 3.465V, VO = 0.4V Measured at 1.65V, output driving low Measured at 1.65V, output driving high VO = 0V; shorted for 30s, max. VO = 3.3V; shorted for 30s, max. 12 12 -10 -51 62 30 mA 38 55 55 10 Ω µA mA mA 1.1 V mA IOH IOL VI (XIN) = 3.3V, VO = 0V VI (XIN) = 0V, VO = 3.3V -8.0 8.7 mA mA VTH IIH IIL CL(xtal) CL(XIN) VIH = 3.3V VIL = 0V As seen by an external crystal connected to XIN and XOUT As seen by an external clock driver on XOUT; XIN unconnected 13.5 1.5 32 -32 18 36 22.5 V µA µA pF pF VIH VIL IIL V V µA MREF_P, MREF_N, CK66_0:3, PCI_0:9 Clock Outputs (Type 5 Clock Driver) IOH min High Level Output Source Current IOH max IOL min Low Level Output Sink Current IOL max Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current zOL zOH IOZ IOSH IOSL -33 mA -33 ISO9001 9.18.00 7 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 13: DC Electrical Specifications, continued Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS HOST_P1:4, HOST_N1:4 Clock Outputs (Type X1 Clock Driver) Crossover Voltage High-Level Output Source Current Output Source Current Tolerance Output Impedance Tristate Output Current VX IOH ∆IOH zOH IOZ RS = 33.2 Ω, RP = 49.9 Ω, RIREF = 475 Ω, IOH = 6 × IREF VO = 0.65V, RIREF = 475 Ω, IOH = 6 × IREF VO = 0.74V, RIREF = 475 Ω, IOH = 6 × IREF VDD = 3.3V, over settings in Table 7 VDD_I = 3.3V±5%, over settings in Table 7 ∆VO/∆IO, where VO1 = 1.0V, VO2 = VSS, RIREF = 475 Ω, IOH = 6 × IREF -7 -12 3000 -10 10 45 12.9 14.9 +7 +12 55 %VOH mA %IOH Ω µA REF_0 / ISEL_0, REF_1 / ISEL_1 Clock Driver I/O, (Type 3) CK48_0 / SEL_A, CK48_1 / SEL_B Clock Driver I/O (Type 3) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-up) High Level Output Source Current Low Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current Output Input VIH VIL IIH IIL IOH IOL zOL zOH IOZ IOSH IOSL VO = 0V; shorted for 30s, max. VO = 3.3V; shorted for 30s, max. VIL = 0.4V VDD_R, VDD_48 = 3.465V, VO = 2.4V VDD_R, VDD_48 = 3.465V, VO = 0.4V Measured at 1.65V, output driving low Measured at 1.65V, output driving high 20 20 -10 -41 40 -9 -32 13 60 60 10 2.0 VSS-0.3 VDD+0.3 0.8 5 V V µA µA mA mA Ω µA mA mA Figure 5: DC Measurement Diagram VDD = 3.3V VOH = 2.4V VOL = 0.4V VIH = 2.0V VIL = 0.8V Figure 6: AC Measurement Diagram tr tf 3.3V 2.4V 1.5V 0.4V dt Figure 7: HOST Clock VX Crossover Point HOST_P VX HOST_N Figure 8: HOST Clock Test Circuit From output under test Test node RS RP ISO9001 9.18.00 8 FS6232-01 AMERICAN MICROSYSTEMS, INC. Two-Way MP Motherboard Clock Generator IC September 2000 Table 14: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER Overall Spread Spectrum Modulation Frequency * Spread Spectrum Modulation Index * Clock Offset Output Tristate Enable Delay * Output Tristate Disable Delay * Power-up PLL Lock Time SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS fm δm tpd tDZL, tDZH tDLZ, tDHZ tL SS_EN# low SS_EN# low CK66 leads @ 1.5V, CL=30pF to PCI @ 1.5V, CL = 30pF (measured on rising edges) SEL_A:B = 00, SEL133/100# = 0 SEL_A:B = 11, SEL133/100# = 0 via PWR_DWN# HOST pair to HOST pair @ VX, RIREF = 475Ω, IOH = 6 × IREF, RS = 33.2 Ω, RP = 49.9Ω Ratio of high pulse width to one clock period at VX, RIREF = 475 Ω, IOH = 6 × IREF, RS=33.2Ω, RP=49.9Ω Rising edge to rising edge at VX, RIREF = 475Ω, IOH = 6 × IREF RS = 33.2 Ω, RP = 49.9Ω Measured at 20% – 80% of VOH; RIREF = 475Ω, IOH = 6 × IREF RS = 33.2 Ω, RP = 49.9Ω Measured at 20% – 80% of VOH; RIREF = 475Ω, IOH = 6 × IREF RS = 33.2 Ω, RP = 49.9Ω Ratio of high pulse width to one clock period, measured at 1.5V From rising edge to rising edge at 1.5V, CL=30pF Measured @ 0.4V – 2.4V; CL=10pF Measured @ 0.4V – 2.4V; CL=30pF Measured @ 2.4V – 0.4V; CL=10pF Measured @ 2.4V – 0.4V; CL=30pF 0.4 0.4 175 45 1.5 1.0 1.0 31.5 -0.5 3.5 10 10 3.0 kHz % ns ns ns ms HOST_P1:4, HOST_N1:4 Clock Outputs Clock Skew * Duty Cycle * Jitter, Period (peak-peak) * Rise Time * Rise/Fall Time Matching* MREF_P, MREF_N Clock Outputs Duty Cycle * Jitter, Period (peak-peak) * Rise Time * Fall Time * dt tj(∆P) tr min tr max tf min tf max 45 55 250 1.6 1.6 % ps ns ns tsk(o) dt tj(∆P) tr 150 55 200 450 20 ps % ps ps % ISO9001 9.18.00 9 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 15: AC Timing Specifications, continued Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER PCI_0:9 Clock Outputs Duty Cycle * Clock Skew * Jitter, Period (peak-peak) * Rise Time * Fall Time * CK66_0:3 Clock Outputs Duty Cycle * Clock Skew * Jitter, Period (peak-peak) * Rise Time * Fall Time * REF_0:1 Clock Outputs Duty Cycle * Jitter, Period (peak-peak) * Rise Time * Fall Time * CK48_0:1 Clock Outputs Duty Cycle * Jitter, Period (peak-peak) * Rise Time * Fall Time * SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS dt tsk(o) tj(∆P) tr min tr max tf min tf max Ratio of high pulse width to one clock period, measured at 1.5V One clock output relative to another at 1.5V From rising edge to rising edge at 1.5V, CL = 30pF Measured at 0.4V – 2.4V; CL = 10pF Measured at 0.4V – 2.4V; CL = 30pF Measured at 2.4V – 0.4V; CL = 10pF Measured at 2.4V – 0.4V; CL = 30pF Ratio of high pulse width to one clock period, measured at 1.5V One clock output relative to another at 1.5V From rising edge to rising edge at 1.5V, CL = 30pF Measured at 0.4V – 2.4V; CL = 10pF Measured at 0.4V – 2.4V; CL = 30pF Measured at 2.4V – 0.4V; CL = 10pF Measured at 2.4V – 0.4V; CL = 30pF Ratio of high pulse width to one clock period, measured at 1.5V From rising edge to rising edge at 1.5V, CL = 20pF Measured at 0.4V – 2.4V; CL = 10pF Measured at 0.4V – 2.4V; CL = 20pF Measured at 2.4V – 0.4V; CL = 10pF Measured at 2.4V – 0.4V; CL = 20pF Ratio of high pulse width to one clock period, measured at 1.5V From rising edge to rising edge at 1.5V, CL = 20pF Measured at 0.4V – 2.4V; CL = 10pF Measured at 0.4V – 2.4V; CL = 20pF Measured at 2.4V – 0.4V; CL = 10pF Measured at 2.4V – 0.4V; CL = 20pF 45 55 500 500 % ps ps ns ns 0.5 2.0 0.5 2.0 dt tsk(o) tj(∆P) tr min tr max tf min tf max 45 55 250 300 % ps ps ns ns 0.5 2.0 0.5 2.0 dt tj(∆P) tr min tr max tf min tf max 45 55 1000 % ps ns ns 1.0 4.0 1.0 4.0 dt tj(∆P) tr min tr max tf min tf max 45 55 350 % ps ns ns 1.0 4.0 1.0 4.0 ISO9001 9.18.00 10 FS6232-01 AMERICAN MICROSYSTEMS, INC. Two-Way MP Motherboard Clock Generator IC September 2000 Table 16: MCLK_P, MCLK_N, PCI_0:9, CK66_0:3 Clock Outputs Voltage (V) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 High Drive Current (mA) MIN. 0 11 21 30 37 43 47 50 53 54 55 55 55 56 56 56 TYP. 0 17 32 45 56 65 73 78 82 84 85 85 86 86 86 87 87 MAX. 0 24 45 64 79 92 103 112 117 120 121 122 123 123 124 124 124 125 Voltage (V) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 Low Drive Current (mA) MIN. -49 -48 -48 -47 -47 -46 -46 -45 -43 -41 -37 -33 -28 -22 -14 -6 TYP. -83 -83 -82 -81 -80 -79 -78 -76 -74 -70 -65 -59 -52 -43 -32 -20 -7 MAX. -132 -131 -130 Output Current (mA) -129 -127 -126 -124 -121 -117 -112 -105 -97 -87 -74 -60 -45 -27 -7 150 125 100 75 50 25 0 -25 -50 -75 -100 -125 -150 0 0.5 1 1.5 2 2.5 3 3.5 30Ω Output Voltage (V) 50Ω 90Ω Data in this table represents nominal characterization data only Table 17: REF_0:1, CK48_0:1 Clock Outputs Voltage (V) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 High Drive Current (mA) MIN. 0 8 15 22 27 31 35 37 39 39 40 40 41 41 41 41 TYP. 0 13 24 33 41 48 53 57 60 61 62 63 63 63 63 64 64 MAX. 0 18 33 47 58 68 76 82 86 88 89 90 90 90 91 91 91 91 Voltage (V) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 Low Drive Current (mA) MIN. -38 -37 -37 -37 -36 -36 -35 -34 -33 -31 -29 -25 -21 -17 -11 -5 TYP. -64 -64 -63 -63 -62 -61 -60 -59 -57 -54 -50 -46 -40 -33 -25 -16 -6 MAX. -102 -101 -100 120 100 80 60 Output Current (mA) -99 -98 -97 -95 -93 -90 -87 -81 -75 -67 -57 -47 -34 -21 -5 40 20 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 2 2.5 3 3.5 30Ω Output Voltage (V) 50Ω 90Ω Data in this table represents nominal characterization data only ISO9001 9.18.00 11 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 7.0 Package Information Table 18: 56-pin SSOP (0.300") Package Dimensions DIMENSIONS INCHES MIN. A A1 b c D E E1 e h L 0.095 0.008 0.008 0.005 0.720 0.395 0.291 0.015 0.020 0° 56 MILLIMETERS MIN. 2.41 0.20 0.20 0.13 18.29 10.03 7.39 0.38 0.51 0° MAX. 0.110 0.016 0.0135 0.010 0.730 0.420 0.299 0.025 0.040 8° MAX. 2.79 0.41 0.34 0.25 18.54 10.67 7.59 0.64 1.01 8° D 1 E1 E AMERICAN MICROSYSTEMS, INC. b e SEATING PLANE h × 45° c L θ 0.025 BSC 0.64 BSC A A1 θ Table 19: 56-pin SSOP (0.300") Package Characteristics PARAMETER Thermal Impedance, Junction to Free-Air Lead Inductance, Self SYMBOL ΘJA L11 L12 CONDITIONS/DESCRIPTION Air flow = 0 m/s Longest trace + wire Shortest trace + wire Longest trace + wire to first adjacent trace Shortest trace + wire to first adjacent trace Longest trace + wire to next adjacent trace Shortest trace + wire to next adjacent trace Longest trace + wire to VSS Shortest trace + wire to VSS Longest trace + wire to first adjacent trace Shortest trace + wire to first adjacent trace Longest trace + wire to next adjacent trace Shortest trace + wire to next adjacent trace TYP. 73 6.41 2.49 3.65 1.35 2.50 0.90 0.94 0.50 0.48 0.20 0.07 0.02 UNITS °C/W nH Lead Inductance, Mutual L13 Lead Capacitance, Bulk C11 C12 Lead Capacitance, Mutual C13 nH pF pF ISO9001 9.18.00 12 FS6232-01 AMERICAN MICROSYSTEMS, INC. Two-Way MP Motherboard Clock Generator IC September 2000 Table 20: 56-pin TSSOP (6.1mm) Package Dimensions DIMENSIONS INCHES MIN. A A1 b c D E E1 e L S 0.002 0.0067 0.0035 0.547 0.236 0.018 0.008 0° 12° REF 12° REF MILLIMETERS MIN. 0.05 0.17 0.09 13.9 6.00 0.45 0.20 0° 12° REF 12° REF 56 MAX. 0.047 0.006 0.011 0.008 0.555 0.244 0.030 8° MAX. 1.20 0.15 0.27 0.20 14.1 6.20 0.75 8° 1 E1 E AMERICAN MICROSYSTEMS, INC. 0.318 BSC 0.019 BSC 8.10 BSC 0.50 BSC b e SEATING PLANE A D A1 c L S θ2 θ3 θ1 θ1 θ2 θ3 Table 21: 56-pin TSSOP (6.1mm) Package Characteristics PARAMETER Thermal Impedance, Junction to Free-Air Lead Inductance, Self SYMBOL ΘJA L11 L12 CONDITIONS/DESCRIPTION Air flow = 0 m/s Longest trace + wire Shortest trace + wire Longest trace + wire to first adjacent trace Shortest trace + wire to first adjacent trace Longest trace + wire to next adjacent trace Shortest trace + wire to next adjacent trace Longest trace + wire to VSS Shortest trace + wire to VSS Longest trace + wire to first adjacent trace Shortest trace + wire to first adjacent trace Longest trace + wire to next adjacent trace Shortest trace + wire to next adjacent trace TYP. 81 4.04 1.38 2.20 0.72 1.43 0.48 0.63 0.21 0.31 0.07 0.04 0.01 UNITS °C/W nH Lead Inductance, Mutual L13 Lead Capacitance, Bulk C11 C12 Lead Capacitance, Mutual C13 nH pF pF ISO9001 9.18.00 13 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 8.0 Ordering Information Table 22: Device Ordering Codes DEVICE NUMBER ORDERING CODE 11995-801 FS6232-01 PACKAGE TYPE 56-pin (0.300”) SSOP OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION Tape and Reel 11995-811 11995-201 11995-211 56-pin (6.1mm) TSSOP 0° C to 70° C (Commercial) Tubes Tape and Reel Tubes Copyright © 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ISO9001 9.18.00 14