MTD655

MYSON TECHNOLOGY FEATURES • IEEE802.3 Clause 9 and IEEE802.3u Cluse 27 compliant. • Provide 4 RMII (Reduced Media Independent Interface) ports and 1 MII port. • Provide 2 inter_repeater stacking bus for 10M and 100M port expansion each. • Support stacking to 4 units without any external arbitration logic ( if use external arbitration logic, theoretically can stack to 6 units and up) . • Build_in 2 port switch controller, support up to 2048 MAC addresses filtering database. • Optional back_pressure flow control • Optional up_link_switch port function (in slave hub), support 100FX 2km distance extension in 100FD mode. • Meet Class_2 repeater specification for 100M_hub. • Use simple and low cost asynchronous SRAM (high speed ASRAM 128k*8 : one pcs only) • 128 pin PQFP package, 5V operation voltage. MTD655 5 Port 10M/100M Hub With 2 port Switch GENERAL DESCRIPTION The MTD655 is a highly integrated, 10M/ 100M dual speed hub with build_in 2 port switch. Support 4 RMII ports and 1 MII port for 10M/ 100M operation, and meet 100M_hub class_2 spec when connect with external PHYceivers. The MTD655 provides two Inter-repeater stacking bus for 10M and 100M expansion each, easily stack to 4 units without any external arbitration logic. If using external arbitration logic and proper bus driver, can stack to 6 units and up. The build_in 2 port switch, support 2k MAC addresses filtering, and use low cost asynchronous high speed SRAM (128k*8) one pcs only for packet buffering. This 2 port switch can also be configured to be up_link switch when hub is under slave mode. The MTD655 also support an simple and effective LED display function, provide 10M_col, 100M_col, memory_test_fail, and per port’ partis tion status. BLOCK DIAGRAM ASRAM Interface Two Port Switch Uplink Switch Enable(10/100,FD/HD) RMII4 10M_HD 10M Inter Hub Bus RMII3 RMII2 RMII1 10M Hub Port Switch Logic 100M_HD 100M Inter Hub Bus MII0 100M Hub This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. 1/18 MTD655 Revision 2.0 17/03/2000 MYSON TECHNOLOGY SYSTEM DIAGRAM DB25 Connector 10M Inter Hub Bus MTD655 MTD655 100M Inter Hub Bus 10M Inter Hub Bus MTD655 100M Inter Hub Bus 10M Inter Hub Bus MTD655 100M Inter Hub Bus 10M Inter Hub Bus ASRAM (128kx8) MTD655 100M Inter Hub Bus MII0 RMII1-4 PHYsceiver QUAD PHYsceiver Transformer QUAD Transformer RJ45 RJ45 This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. 2/18 MTD655 Revision 2.0 17/03/2000 1.0 PIN CONNECTION MYSON TECHNOLOGY VCC A4 GND OEB A3 A10 A2 A1 D7 A0 D6 D0 D5 D1 GND D4 D2 D3 VCC SYSCLK GND LEDDAT LEDCLK MDC MDIO RSTB 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 MTD655 3/18 GND NC VCC NC NC GND GND SPD0 TXD0_3 TXD0_2 NC TXCLK0 GND GND RXCLK0 TXD0_1 TXD0_0 TXEN0 RXD0_0 RXD0_1 GND NC NC NC GND GND RXD0_2 RXD0_3 RXDV0 CRS0 VCC GND CRSDV1 TXD1_1 TXD1_0 TXEN1 RXD1_0 RXD1_1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 A11 A5 A9 A6 A8 A7 A13 A12 WEB A14 GND A15 A16 IREQ10_OUT IREQ10_IN0 IREQ10_IN1 IREQ10_IN2 ICOLB10 IACKB10 ICLK10 GND IDAT10 IREQ100_OUT IREQ100_IN0 IREQ100_IN1 IREQ100_IN2 ICOLB100 IACKB100 GND ICLK100 VCC IDAT100_0 IDAT100_1 IDAT100_2 IDAT100_3 IMASTER FD4 UPSWEN 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 SPD1 SPD2 SPD3 SPD4 GND VCC RXD4_1 RXD4_0 TXEN4 TXD4_0 TXD4_1 CRSDV4 RXD3_1 RXD3_0 TXEN3 TXD3_0 TXD3_1 CRSDV3 GND VCC RXD2_1 RXD2_0 TXEN2 TXD2_0 TXD2_1 CRSDV2 MTD655 MTD655 Revision 2.0 17/03/2000 MYSON TECHNOLOGY 1.0 PIN DESCRIPTIONS MII Port Interface Pins (port0) Name RXD0_0 RXD0_1 RXD0_2 RXD0_3 CRS0 RXDV0 RXCLK0 TXEN0 TXD0_0 TXD0_1 TXD0_2 TXD0_3 TXCLK0 Pin Number 19 20 27 28 30 29 15 18 17 16 10 9 12 I/O Descriptions I Port0 MII receive data bit_0. I I I I I I O O O O O I Port0 MII receive data bit_1. Port0 MII receive data bit_2. MTD655 Port0 MII receive data bit_3. Port0 MII asynchronous carrier indicator from PHY device. Port0 MII synchronous receive data valid signal from PHY device. Port0 MII receive clock. Port0 MII transmit enable signal. Port0 MII transmit data bit_0. Port0 MII transmit data bit_1. Port0 MII transmit data bit_2. Port0 MII transmit data bit_3. Port0 MII transmit clock. RMII Port Interface Pins (port1 ~port4) Name CRSDV1 RXD1_0 RXD1_1 TXEN1 TXD1_0 TXD1_1 CRSDV2 RXD2_0 RXD2_1 TXEN2 TXD2_0 TXD2_1 CRSDV3 RXD3_0 RXD3_1 TXEN3 TXD3_0 TXD3_1 CRSDV4 Pin Number 33 37 38 36 35 34 39 43 44 42 41 40 47 51 52 50 49 48 53 I/O Descriptions I Port1 RMII receive interface signal, CRSDV1 is asserted high when I I O O O I I I O O O I I I O O O I port1 media is non_idle. Port1 RMII receive data bit_0. Port1 RMII receive data bit_1. Port1 RMII transmit enable signal. Port1 RMII transmit data bit_0. Port1 RMII transmit data bit_1. Port2 RMII receive interface signal, CRSDV2 is asserted high when port2 media is non_idle. Port2 RMII receive data bit_0. Port2 RMII receive data bit_1. Port2 RMII transmit enable signal. Port2 RMII transmit data bit_0. Port2 RMII transmit data bit_1. Port3 RMII receive interface signal, CRSDV3 is asserted high when port3 media is non_idle. Port3 RMII receive data bit_0. Port3 RMII receive data bit_1. Port3 RMII transmit enable signal. Port3 RMII transmit data bit_0. Port3 RMII transmit data bit_1. Port4 RMII receive interface signal, CRSDV4 is asserted high when port4 media is non_idle. 4/18 MTD655 Revision 2.0 17/03/2000 MYSON TECHNOLOGY RMII Port Interface Pins (port1 ~port4) Name RXD4_0 RXD4_1 TXEN4 TXD4_0 TXD4_1 Pin Number 57 58 56 55 54 I/O Descriptions I Port4 RMII receive data bit_0. I O O O Port4 RMII receive data bit_1. Port4 RMII transmit enable signal. Port4 RMII transmit data bit_0. Port4 RMII transmit data bit_1. MTD655 High Speed Asynchronous SRAM Interface Pins Name WEB OEB D[7:0] Pin Number 94 106 111,113,115, 118,120,119, 116,114 90,91,93,96, 95,102,108, I/O Descriptions O ASRAM control pin for write (low active). O ASRAM control pin for read (low active). I/O ASRAM data bus A[16:0] O ASRAM address bus 100,98,97,99 ,101,104,107 ,109,110,112 Note: Asynchronous SRAM acess time: 10/12 ns (max) 10M Inter-Bus Interface pins Name IMASTER Pin Number I/O I Descriptions Master hub selection: when high: means hub internal inter_bus arbiter is enabled and hub internal two_port switch is well conneted to 10M_hub core and 100M_hub core . when low: means hub internal inter_bus arbiter is disabled and hub internal two_port switch is not connected to 10M_hub core and 100M_hub core. I/O 10M Inter-Bus port access acknowledge signal (low active). For master hub, this pin is output; for slave hub is input, or while EXT_ARB jumper was set to “1”, this pin is input from an external arbitration device. I/O 10M Inter-Bus collision signal (low active). For master hub, this pin can output multi hub collision event to inform all slave hub ; for slave hub, this pin is an input, or while EXT_ARB jumper was set to “1”, this pin is input from an external arbitration device. I 10M Inter-Bus port access request input. I 10M Inter-Bus port access request input. I 10M Inter-Bus port access request input. O 10M Inter-Bus port access request output. 5/18 MTD655 Revision 2.0 17/03/2000 67 IACKB10 84 ICOLB10 85 IREQ10_IN0 IREQ10_IN1 IREQ10_IN2 IREQ10_OUT 88 87 86 89 MYSON TECHNOLOGY 10M Inter-Bus Interface pins Name ICLK10 IDAT10 Pin Number 83 81 I/O Descriptions I/O 10M Inter-Bus port clock. I/O 10M Inter-Bus port data bit 100M Inter-Bus Interface pins Name IACKB100 Pin Number 75 ICOLB100 76 IREQ100_IN0 IREQ100_IN1 IREQ100_IN2 IREQ100_OUT ICLK100 IDAT100_0 IDAT100_1 IDAT100_2 IDAT100_3 79 78 77 80 73 71 70 69 68 MTD655 I/O Descriptions I/O 100M Inter-Bus port access acknowledge signal (low active). For master hub, this pin is output; for slave hub is input, or while EXT_ARB jumper was set to “1”, this pin is input from an external arbitration device. I/O 100M Inter-Bus collision signal (low active). For master hub, this pin can output multi hub collision event to inform all slave hub ; for slave hub, this pin is an input, or while EXT_ARB jumper was set to “1”, this pin is input from an external arbitration device. I 100M Inter-Bus port access request input. I 100M Inter-Bus port access request input. I 100M Inter-Bus port access request input. O 100M Inter-Bus port access request output. I/O 100M Inter-Bus port clock. I/O 100M Inter-Bus port data bit 0. I/O 100M Inter-Bus port data bit 1. I/O 100M Inter-Bus port data bit 2. I/O 100M Inter-Bus port data bit 3. LED Interface Pins Name LEDDAT Pin Number I/O I/O Descriptions LED display serial data out; mapping for LEDCLK signal’ burst clock s , its serial out data sequence is : ( first bit be shifted out is from b00, and end of burst bit is b23) b00: *********** b01: ********** b02: ********** b08: 10hub_col b09: 100hub_col b10: asram_test_fail b11: port0 partition b12: port1 partition b13: port2 partition b14: port3 partition b15: port4 partition b16: ************ b17: ************ b18: ************ b19: port0 rx_activity b20: port1 rx_activity b21: port2 rx_activity b22: port3 rx_activity b23: port4 rx_activity 124 b03: port0 partition b04: port1 partition b05: port2 partition b06: port3 partition b07: port4 partition LEDCLK 125 I/O LED display clock signal, the signal is a discontinued clock for LED data serial shift out. Every clock burst have 24 cycles ( period : 160 ns), and the clock burst will be repeated with every 42ms. 6/18 MTD655 Revision 2.0 17/03/2000 MYSON TECHNOLOGY Miscellaneous Pins Name RSTB SYSCLK MDC MDIO UPSWEN Pin Number 128 122 126 127 65 FD4 66 SPD0 SPD1 SPD2 SPD3 SPD4 NC_pin VCC GND 8 64 63 62 61 2,4,5,11,22, I I I I I I I/O I I I/O I/O I MTD655 Descriptions System reset input, low active. 50MHz system clock input MII management clock inout MII management data inout Up_link switch port enabling : one of internal two_port switch port will connect to 100M_hub domain, and another port will redirect to RMII port4. When up_link switch port enabling, this pin is port4’ full_deplex indis cator, input from PHY. When hign , indicate port4 in running on full_duplex mode. When low, indicate on half_duplex mode. Port0 speed indicator, input from PHY. SPD0 input low: 100M , input high: 10M. Port1 speed indicator, input from PHY. SPD1 input low: 100M , input high: 10M. Port2 speed indicator, input from PHY. SPD2 input low: 100M , input high: 10M. Port3 speed indicator, input from PHY. SPD3 input low: 100M , input high: 10M. Port4 speed indicator, input from PHY. SPD4 input low: 100M , input high: 10M. NC No connection pins 23,24 3,31,45,59, PWR Power pins 72,103,121 1,6,7,13,14, GND Ground pins 21,25,26,32, 46,60,74,82, 92,105,117, 123 7/18 MTD655 Revision 2.0 17/03/2000 MYSON TECHNOLOGY Power On Configuration Set Up Table Name NC_11 Pin Number MTD655 I/O Descriptions I/O Port0 MII interface enable : ( power on external jumper configuration ) - pin floating : Port0 MII interface disable (change to be RMII interface) , not suit for 5 ports daul speed hub application. - external pull_high: Port0 MII interface enable. I/O Back_pressure disable : ( power on external jumper configuration ) 11 TXEN0 18 TXEN2 42 - external pull_low (default ) : normal mode (back_pressure enbale) - external pull_high: back_pressure disable I/O Auto MII_setting bypass : ( power on external jumper configuration ) - external pull_low (default ) : normal mode ( auto MII_setting); after power_on, MTD655 will auto setup PHY devices be forced in half_ duplex mode for repeater apllication. - external pull_high: auto MII_setting bypass I/O 1522 bytes packet accept enable : ( power on external jumper configuration ) MDC 126 - external pull_low (default ) : normal mode (