NT3882H

NT3882 Dot Matrix LCD 40-Channel Driver Features T T T Provides a 40 channel LCD driver Internal serial to parallel conversion circuits: 20-bit shift register X 2 40-bit latch X 1 40-bit 4 level driver X 1 Logic circuit supply voltage range: 4.5V - 5.5V T T T T T LCD driving voltage range (VDD - VEE): 3.5V to 11V Applicable LCD duty cycle: 1/2 to 1/16 Interfaces with a NT3881C/D LCD controller LCD bias voltage can be supplied externally Available in 64-pin QFP and in CHIP FORM General Description The NT3882 is a dot matrix LCD 40 channel driver fabricated by low power CMOS technology. This IC consists of two 20-bit shift registers, a 40-bit latch, and a 40-bit 4 level LCD driver. The NT3882 converts serial data which is received from the LCD controller (NT3881C/D) to parallel data and then outputs LCD driving waveforms to drive LCD. Expansion of charactertype liquid crystal display can be easily obtained according to the number and structure of characters. Pin Configuration S 3 4 S 3 3 S 3 2 S 3 1 S 3 0 S 3 5 S 3 6 S 3 7 S 3 8 S 3 9 S 4 0 Pad Configuration S 2 9 2 S 3 4 63 S 3 3 62 S 3 2 61 S 3 1 60 S 3 0 59 S 3 5 57 S 3 6 56 S 3 7 55 S 3 8 54 S 3 9 53 S 4 0 52 N C N C S28 3 4 5 64 NC S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S 9 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 V2 NC NC V3 S24 7 8 9 10 11 12 13 14 35 S16 15 16 17 18 25 19 S 1 2 20 S 9 21 S 1 0 22 S 1 1 23 S 8 24 S 7 V D D S27 S26 S25 51 V2 48 6 46 42 40 39 V3 V EE M DR2 DL2 NC V EE NC NC NC S20 S23 S22 S21 NT3882H NT3882F 38 37 DR1 DL1 42 41 40 39 38 37 36 35 34 33 M NC DR2 DL2 DR1 DL1 GND CL2 CL1 NC S15 S14 S13 34 CL1 S19 S18 S17 36 GND CL2 32 S1 27 S 6 28 S 5 29 S 4 30 S 3 31 S 2 21 S 1 0 22 S 1 1 23 S 8 24 S 7 25 V D D 26 N C 27 S 6 28 S 5 29 S 4 30 S 3 31 S 2 32 S 1 1 V2.0 November, 1999 NT3882 Block Diagram S1 V DD S2 S19 S20 S21 S22 S39 S40 V2 V3 V EE 40-Bit 4-Level LDC Drivers M CL1 40-Bit Latch DL2 CL2 20-Bit Shift Re g ister 20-Bit Shift Register DR2 DR1 DL2 GND 2 NT3882 Pin and Pad Descriptions Pin No. 2- 24, 27 - 32, 52 - 57, 59 - 63 25 34 35 36 37 38 39 40 42 46, 48, 51 1, 26, 33, 41, 43 - 45, 47, 49, 50, 58, 64 Pad No. 27 - 32, 2 - 24, 52 - 57, 59 - 63 25 34 35 36 37 38 39 40 42 46, 48, 51 Designation S29 - S7, S6 - S1, S40 - S35, S30 - S34 VDD CL1 CL2 GND DL1 DR1 DL2 DR2 M VEE, V3, V2 NC I/O O External Connection LCD panel Description Segment signal output pins P I I P I O I O I P - Power supply Controller Controller Power Supply Controlleror NT3882 NT3882 Controlleror NT3882 NT3882 Controller Power Supply - Power for logic circuits Clock to latch serial data Clock to shift serial data 0V Data input of 1 - 20 bits from controller Data output of 20 bit shift register Data input of 21 - 40 bits from controller Data output of 40 bit shift register Alternate signal for LCD drivers Power for LCD drivers No connection Functional Description NT3882 is a dot matrix LCD segment driver LSI. It operates with the controller, such as NT3881C/D, and/or another segment driver LSI NT3882. NT3882 receives serial data from the controller or another NT3882, converts it to parallel data and then supplies the LCD driving waveforms to the LCD panel. 1. CL1 This signal is used for latching the shift register contents. When CL1 is set at high, the shift register contents are transferred to the 40-bit 4level LCD driver. When CL1 is set at low, the last display output data (S1 to S40) is held. 2. CL2 Clock pulse inputs for the two 20-bit shift registers. The data is shifted to a 40-bit latch at the falling edge of CL2. The clock singal CL2 must be active when operating to refresh shift registers' contents. 3. DL1 The 1 - 20 bit data from LCD controller is fed into the first 20-bit shift register through DL1. 4. DR1 The 20th bit data of first 20-bit shift register output from DR1. The data shifted out from DR1 after 20 bit delay are synchronized with the clock pulse (CL2). By connecting DR1 to DL2, two 20-bit shift registers can be cascaded to one 40-bit shift register. 5. DL2 The 21 - 40 bit data from the LCD controller is fed into the second 20-bit shift register through DL2. 6. DR2 The 40th bit data of the second 20-bit shift register output is from DR2. The data shifted out from DR2 after a 20-bit delay is synchronized with the clock pulse (CL2). By connecting DR2 to the next NT3882 DL1, the cascade construction is obtained to drive a wider LCD panel. 7. S1 to S40 These 40 bits represent the 40 data bits in the 40-bit latch. One of VDD, V2, V3 and VEE is selected as a LCD driving voltage source according to the combination of latched data level and the alternate signal (M). 3 NT3882 The truth table is listed as follows: Latched Data 1(High) (Selected) 0(Low) (Nonselected) M 1(High) 0(Low) 1(High) 0(Low) Output level of S1 to S40 VEE VDD V3 V2 Absolute Maximum Ratings* Power Supply Voltage (VDD-GND) . . . . . . . -0.3V to 7.0V Power Supply Voltage (VDD-VEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - 13.5V to VDD + 0.3V Input Voltage . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V Operating Temperature . . . . . . . . . . . . . -20qC to + 75qC Storage Temperature . . . . . . . . . . . . . .-55qC to + 125qC *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposed to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25GC) Symbol VIH VIL VOH VOL VD1 VD2 IIL IVL IDD Vi-Sj Voltage Descending Input Leakage Current Vi Leakage Current Power Supply Current CL1, CL2 DL1, DL2 V2, V3, VEE Note 2 -5 -10 Note 1 Output Voltage Parameter Input Voltage Terminal CL1, CL2 DL1, DL2 DR1, DR2 Min. 0.7 X VDD 0 VDD - 0.4 Typ. Max. VDD 0.3 X VDD 0.4 1.1 105 5 10 200 Unit V V V V V V IOH = -0.4mA IOL = 0.4mA ION = 0.1mA for one of Sj ION = 0.05mA for each of Sj VIN = 0 or VDD S1 to S40 open fCL1 = 1KH fCL2 = 400KHz Conditions PA PA PA Note 1: Vi - Sj (Vi = VDD, V2, V3, VEE; j = 1 to 40) equivalent circuit. 1Kmax. Vi Power Switch 1Kmax. Data Swtich Sj Note 2: Input/output current is excluded. When the input is at the intermediate level with CMOS, some excessive current will flow through the input circuit to the power supply. To avoid this, the input level must be fixed at a high or low state. 4 NT3882 AC Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25GC) Symbol fCL2 tCWH tCWL tDH tSUD tSUC1 tSUC2 tCL tPD Data Hold Time Data Set-up Time Clock Set-up Time (CL2 o CL1) Clock Set-up Time (CL1 o CL2) Clock Rise/Fall Time Data Delay Time Parameter Data Shift Frequency Clock Width High Low Terminal CL2 CL1, CL2 CL2 DL1, DL2 DL1, DL2 CL1, CL2 CL1, CL2 CL1, CL2 Min. 800 800 300 300 500 500 75 Typ. Max. 400 200 500 Unit KHz ns ns ns ns ns ns ns ns Timing Waveforms V IH t CWL CL2 V IL t CL t CWH t CL t DH DL1,DL2 t SUD t SUC1 t PD V OH DR1,DR2 V OL t SUC2 t SUC2 CL1 t CL t CWH t CL 5 NT3882 Application Circuit (for reference only) LCD PANEL C1 - C16 S1 - S40 D DL1 S1 - S40 DR2 DL1 CL2 S1 - S40 DR2 DL2 CL2 DL2 CL1 M V DD GND NT3882 DR1 CL1 NT3882 DR1 M V2 V3 V EE V DD GND V2 V3 V EE CL2 CL1 NT3881D M V DD GND V1 V2 V3 V4 V5 VR R R R R R C C C C C GND or other negative voltage 6 NT3882 Bonding Diagram S 2 9 2 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 3 4 51 5 6 7 42 8 9 10 11 12 13 36 14 35 15 34 16 17 18 19 S 1 2 20 S 9 21 S 1 0 22 S 1 1 23 S 8 24 S 7 V D D S 3 4 63 S 3 3 62 S 3 2 61 S 3 1 60 S 3 0 59 S 3 5 57 S 3 6 56 S 3 7 55 S 3 8 54 S 3 9 53 S 4 0 52 V2 NT3882H 48 V3 46 V EE M Y 40 39 DR2 DL2 2514 2m (0,0) X 38 DR1 37 DL1 GND CL2 CL1 32 S1 25 27 S 6 28 S 5 29 S 4 30 S 3 31 S 2 2235 2m * Connecting IC substrate to VDD or keeping floating is recommended. * Pad window area120Pm X 100Pm. 7 NT3882 Bonding Dimensions unit: 2m Pad No. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 Designation S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S9 S10 S11 S8 S7 VDD S6 S5 X -729 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -985 -729 -579 -429 -279 -129 21 171 321 471 Y 1148 1125 975 825 675 525 375 225 75 -75 -225 -375 -525 -675 -825 -975 -1125 -1148 -1148 -1148 -1148 -1148 -1148 -1090 -1148 -1148 Pad No. 29 30 31 32 34 35 36 37 38 39 40 42 46 48 51 52 53 54 55 56 57 59 60 61 62 63 Designation S4 S3 S2 S1 CL1 CL2 GND DL1 DR1 DL2 DR2 M VEE V3 V2 S40 S39 S38 S37 S36 S35 S30 S31 S32 S33 S34 X 621 771 921 985 985 985 985 985 985 985 985 985 985 985 985 921 771 621 471 321 171 21 -129 -279 -429 -579 Y -1148 -1148 -1148 -859 -705 -555 -373 -204 -54 96 246 396 562 722 882 1148 1148 1148 1148 1148 1148 1148 1148 1148 1148 1148 Ordering Information Part No. NT3882H NT3882F Package CHIP FORM 64L QFP 8 NT3882 Package Information QFP 64L Outline Dimensions ÉÅ Å ·µ ¶³ unit: inches/mm ² ¶² ²º ´´ ³± æ ÈÅ ã ´³ ÉÆ ÈÆ Æ ÈÅ ÿ ÿ ³ Ôææ Åæõâêí Ç Ôæâõêïè Ñíâïæ  ä y D ² Í Í² Åæõâêí Ç Symbol A A1 A2 b Dimensions in inches 0.130 Max. 0.004 Min. 0.112 ± 0.005 0.016 +0.004 -0.002 0.006 +0.004 -0.002 0.551 ± 0.005 0.787 ± 0.005 0.039 ± 0.006 0.693 NOM. 0.929 NOM. 0.740 ± 0.012 0.976 ± 0.012 0.047 ± 0.008 0.095 ± 0.008 0.006 Max. 0G ~ 12G Dimensions in mm 3.30 Max. 0.10 Min. 2.85 ± 0.13 0.40 +0.10 -0.05 0.15 +0.10 -0.05 14.00 ± 0.13 20.00 ± 0.13 1.00 ± 0.15 17.60 NOM. 23.60 NOM. 18.80 ± 0.31 24.79 ± 0.31 1.19 ± 0.20 2.41 ± 0.20 0.15 Max. 0G ~ 12G c D E e GD GE HD HE L L1 y 6 Notes: 1. Dimensions D & E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only. 9