NT68275

NT68275 IIC Bus Controlled On-Screen Display Features n IIC Bus Interface with Slave Address $7A (Transmitter) & $7B (Receiver) n Horizontal Frequency Range: 30KHz ~ 150KHz* n Flexible Display Resolution Up to 1524 Dots/Row n Internal PLL Generates a Stable and Wide-Ranged System Clock (120 MHz)* n OSD Screen Consist Character Array of 15 Rows by 30 Columns n Programmable Vertical and Horizontal Position for OSD Displaying Center n Total of 528* ROM Fonts including 512* Standard & 16 Multi-color ROM Fonts. n 12 X 18 Dot Matrix Per Character n 8-Color Selection for Each Character n 7-Color Selection for Each Character Background n Character/Symbol Blinking, Shadowing & Bordering Display Effect n Double Character Height and Width for Each Row n Programmable Height of Character/Symbol Display n Row To Row Spacing Control to Avoid Expansion Distortion n Four Programmable Windows with Overlapping Capability and Shadowing Effect n Color Setting for Windows’ Background and Character Shadowing & Bordering n Fade-In/Out Effect of OSD Screen Display n Hsync & Vsync Input Polarity Selectable General Description NT68275 is designed for displaying symbols and characters onto a CRT monitor. Its operation is controlled by a microcontroller with an IIC bus interface. By sending proper data and commands to NT68275, it can carry out the full screen display automatically with the time base generated by an on-chip PLL circuit. There are many functions provided by this chip to fully support user applications, such as: adjustment of the position of OSD The “ * “ sign denote s that feature different from NT6827. windows , built-in 512* ROM & 16 multi-color fonts, variable character height with row-to-row spacing adjustment, 8 color selections & 7 background color controls for each character, double height/width controls for each row, 4 overlapping window available with color & size controls, size controls for each window shadowing, color selection for windows’ shadowing & character shadowing/ bordering, fade-in/out display effect, etc. 1 V1.0 NT68275 Block Diagram SCL SDA I2C BUS RECEIVER BUS CONTROL BUFFER ROM FONT 12 * 18 DISPLAY EFFECT VPOL R/G/B VERTICAL CONTROL VFLB HFLB VSYNC DISPLAY MEMORY OUTPUT CONTROL FBKG *PWM/INT HSYNC HPOL CONTOL REG. TIMING GENERATOR POWER ON LOW VOLTAGE RESET COLOR CONTROL RP VCO PLL CIRCUIT TEST CIRCUIT HORIZONTAL CONTROL POWER SYSTEM AGND 2 DGND AVCC DVCC NT68275 Pin Assignment AGND VCO RP AVCC HFLB N.C. SDA SCL 1 2 3 4 5 6 7 8 16 15 14 13 DGND R G B FBKG *PWMCK/INT VFLB DVCC NT68275 12 11 10 9 3 NT68275 Pin Description NT68275 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME AGND VCO RP AVCC HFLB N.C. SDA SCL DVCC VFLB *PWMC K/INT FBKG B G R DGND I/O/P/R P P I I I P I O O O O O P Analog Ground Voltage I/P to Control Oscillator Bias Resistor. Used to bias internal VCO to resonate at specific dot frequency Analog Power Supply (5 V Typ.) Horizontal Fly-back Input (Schmitt Trigger Buffer) SDA Pin Of IIC Bus (Schmitt Trigger Buffer) with internal 100K ohm pulled-high resistance SCL Pin Of IIC Bus (Schmitt Trigger Buffer) with internal 100K ohm pulled-high resistance Digital Power Supply (5 V Typ.) Vertical Fly-back Input (Schmitt Trigger Buffer) PWM output or Intensity output Fast Blanking Output. Used to cut off external R, G, B signals. Blue Color Output with Push-Pull Output Structure Green Color Output with Push-Pull Output Structure Red Color Output with Push-Pull Output Structure Digital Ground Function 4 NT68275 DC/AC Absolute Maximum Ratings* Recommended Operating Conditions VCC (measured to GND) . . . . . . . . . .. . 4.75V to 5.25V Operating Temperature . . . . . . . . . . . . . 0 to +70 0C *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposed to the absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics (VDD = 5V, Tamb = 25° C) Symbol VCC Supply Voltage Parameter Min. 4.75 Typ. 5 Max. 5.25 Unit V Notes DC Characteristic Symbol IDD VIH1 VIL1 VIH2 VIL2 Idrive1 Isink1 Ileak Iiicl V th VSTIH VSTIL Parameter Operating Current Input High Voltage Input Low Voltage IIC Bus Input High Voltage IIC Bus Input Low Voltage Driving current of R, G, B, FBKG, HFTON output pins at 2.4V output voltage Sinking current of R, G, B, FBKG, HFTON output pins at 0.4V output voltage Leakage current of R, G, B, FBKG pins at Hi-Z state IIC Bus Output Sink Current Input Threshold Voltage at HFLB & VFLB Schmitt Trigger Input High Voltage Schmitt Trigger Input Low Voltage Min. Typ. 22 Max. 25 Unit mA V Notes No loading VFLB, HFLB with Schmitt Trigger Buffer VFLB, HFLB Schmitt Trigger Buffer SCL, SDA 2 0.8 3 1.5 80 20 10 5 1.8 2.0 1.7 0.8 1.1 V V V mA mA uA mA Measured at 2.5V state Viicoutl = 0.4V 2.2 2 V V V Refer Figure 1 Iin Input Current of Hsync, Vsync, SDA, SCL pins -10 +10 uA Schmitt Trigger Buffer 5 NT68275 Output state VH VL 1.1V 1.7V Input voltage Figure 1. Schmitt Trigger Diagram AC Characteristic Symbol Fhfy Vhfly Thflymin Thflymax Fvfy Vvfly Tvflymin Tvflymax Parameter Horizontal Fly-back Frequency Horizontal Fly-back Input Minimum Pulse Width of Horizontal Fly-back Maximum Pulse Width of Horizontal Fly-back Vertical Fly-back Frequency Vertical Fly-back Input Minimum Pulse Width of Vertical Fly-back Maximum Pulse Width of Vertical Fly-back 50 Min. 30 Typ. Max. *150 5 0 0.7 5.5 *200 5 0 20 1 5V Unit KHz V V us us Hz V V us ms Notes HFLB Thwidth 2.0 V 0V 5V VFLB Tvwidth 2.0 V 0V Figure 2. H/V Fly-Back Signal 6 NT68275 7 NT68275 IIC Bus - Slave Transmitter & Receiver (Slave address: $7A & $7B) Table 1. IIC Bus Symbol Parameter Min. Typ. Max. Unit Notes Fmaxcl VIL VIH Tlow Thigh Tsudat Thddat Tiicr Tiicf Tsusta Thdsta Tsusta Tsusto Tiicbuf Iiicl Tfilter Maximum SCL Clock Frequency Input Low Voltage Input High Voltage Low Period of SCL Clock High Period of SCL Clock Data Setup Time Data Hold Time Rise Time of IIC Bus Fall Time of IIC Bus Setup Time Condition for Repeated START 1.3 4.0 4.7 4.0 4.7 4 5 -0.5 3.0 4.7 4.0 250 300 100 1.5 5.5 KHz V V us us ns ns 1000 300 ns ns us us us us us mA Viicoutl = 0.4 V SCL, SDA SCL, SDA Hold Time for START Condition Setup Time for START Condition Setup Time for STOP Condition Time IIC bus must be free before next new transmission can start IIC Bus Sink Current Input Filter Spike Suppression 100 ns See also IIC Table Control and IIC Sub Address Control SDA Tiicbuf Tlow Tiicr Tiicf Thdsta SCL Thdsta Thddat Thigh Tsudat Tsusta Tsusto STOP START START STOP Figure 3. IIC Bus Timing 8 NT68275 Memory Map 7 Fonts Address $00-$FF 0 7 Row Attribute Register 0 7 7 0 0 0 COLUMN 29 0 30 DISPLAY REGISTER 14 Figure 4-1. Memory Map of Display Register (Row 0 – 14) 7 Character Attribute Register 0 7 0 0 0 COLUMN 29 ROW CHARACTER ATTRIBUTE REGISTER 14 Figure 4-2. Memory Map of Attribute Register (Row 0 – 14) 9 ROW ATTRIBUTE REGISTER ROW NT68275 7 Window 1-4 Control Register 0 7 Reset Flag Control Register 0 7 7 ROW 15 0 0 WINDOW1 - WINDOW4 0 OSD SCREEN CONTROL 11 12 22 23 COLUMN 7 OSD Screen Control Register 0 Figure 4-3. Memory Map of Control Register (Row 15) 10 NT68275 List of Control Registers: (1) Display Register: Row 0 – 14 , Column 0 – 29 8 Row 0-14 Column 0-29 *Page 7 MSB 6 5 4 3 2 1 0 LSB Font’s Address $00 - $1FF Bit 8: * Page - This bit will address the page 1 ROM font area by bit 7-0 of this control register. Otherwise, it will address page 0. This can be set by the bit5 column data at IIC bus transmission. Refer to Figure 8-1 & 8-3 for ROM font area. Bit 7-0: These eight bits will address one of the 256 characters/ symbols residing in the character ROM fonts. Note that if user sets MCFONT bit (row 15, column 22) to ‘1’, the 0 ~ 256 will address standard ROM fonts, and if cleared to ‘0’, the 0 ~ 239 will address standard ROM fonts & 240 ~ 255, multi -color ROM fonts. (2) Character Attribute Register: Row 0 – 14, Column 0 – 29 7 Row 0-14 Column 0-29 6 BKR 5 BKG 4 BKB 3 BLINK 2 R 1 G 0 B Character Attribute Control Bit 6-4: BKR/G/B -These three bits define the color attribute of the background for the corresponding character/symbol. If all three bits are cleared, no background will be displayed. Refer to the TAB 3 for the color selections. Bit 3: BLINK - This bit enables the blinking effect of the corresponding character/symbol with this bit set to ‘1’. The blinking frequency is approximately 1Hz with a fifty-fifty duty cycle at 80Hz vertical sync frequency. Bit 2-0: R/G/B -These three bits define the color attribute of the corresponding character/symbol. Refer to the TAB 2 for the color selections. TAB 2. Character/Window Color Selection COLOR Black Blue Green Cyan Red Magenta Yellow White R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 TAB 3. Character/Window Background Color Selection COLOR No Background Blue Green Cyan Red Magenta Yellow White R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 11 NT68275 IIC Bus Controlled On-Screen Display 12 V1.0 NT68275 (3) Row Attribute Register: Row 0 – 14, Column 30 7 Row 0-14 Column 30 6 5 4 3 2 *RINT 1 DBH 0 DBW Row’s Attribute Control Bit 1: DBH – This bit controls the height of the displayed character/symbol. When this bit is set, the character/symbol is displayed in double height. Bit 0: DBW – This bit controls the width of the displayed character/symbol. When this bit is set, the character/symbol is displayed in double width. Bit 2: * RINT – Row intensity, This bit controls the intensity of the corresponding row .By setting this bit to 1, the INT pin will go high when the characters of this row are displayed. See Figure 5. 13 NT68275 (4) Window 1 Registers: Row 15, Column 0 7 Row 15 Column 0 MSB 6 5 Row Start Address 4 LSB 3 MSB 2 1 Row End Address 0 LSB Window 1 Row Size Control Bit 7-4: These bits determine the row start position of Window 1on the 15*30 OSD screen. Bit 3-0: These bits determine the row end position of Window 1on the 15*30 OSD screen. 7 Row 15 Column 1 MSB 6 5 4 Column Start Address 3 LSB 2 1 0 SHAD WINEN *WINT Window1 Column Size Control & Attribute Control Bit 7-3: These bits determine the column start position of Window 1 on the 15*30 OSD screen. Bit 2: WINEN - This bit enables window 1 when it is set. The default value is 0 after power on. Bit 1: * WINT - Window intensity. This bit controls the intensity of Window 1 .By setting this bit to 1, the INT pin will go high while displaying Window 1 and characters inside the window. See Figure 5. Bit 0: SHAD - This bit enables the shadowing on the window when it is set to ‘1’. The default value is 0 after power on. 7 Row 15 Column 2 MSB 6 5 4 Column End Address 3 LSB 2 1 0 R G B Window 1 Column Size Control & Attribute Control Bit 7-3: These bits determine the column end position of Window 1on the 15*30 OSD screen. Bit 2-0: R/G/B – These bits control the background color of Window 1. Refer to Table for color selection. Note: Window 1 control registers occupy column 0-2 of row 15, Window 2 from column 3-5, Window 3 from 6-8 and Window 4 from 9-11. The function of Window 2- 4 control registers is the same as Window 1. Window 1 has the highest priority, and the Window 4, the least. The higher priority color will take over on the overlap window area. If the start address of the row/column is greater than the end address, the window will not be displayed. Out of range setting (over 15 rows or 30 columns range) will cause abnormal operation. 14 NT68275 OSD Screen Position Control Registers: Row 15, Column 12 - 13 7 Row 15 Column 12 MSB 6 5 4 VPOS 3 2 1 0 LSB Vertical Position Adjustment Bit 7-0: VPOS - These bits determine the vertical starting position for the character display. It is the vertical delay starting from the leading edge of VFLB. The unit of this setting is 4 horizontal lines and the equation is defined as below: Vertical delay = (Vpos * 4 +1) * Horizontal line . The default value of it is 4 ($04) after power on. 7 Row 15 Column 13 MSB 6 5 4 HPOS LSB 3 2 1 0 Horizontal Position Adjustment Bit 7-0: HPOS – These bits determine the horizontal starting position for the character display. It is the horizontal delay starting from the leading edge of HFLB. The unit of this setting is 6 dots movement shift to right on the monitor screen and the equation is defined as below: Horizontal delay = (Hpos * 6 + 49) / P.R. where the P.R. (pixel rate) is defined by the HDR & Horizontal Frequency. P.R. (Pixel Rate) = HDR * 12 * FreqHFLB Refer the HDR control register at row 15 / column 15 for the P.R. setting. The default value of these bit is 15 ($ 0F) after power on. 15 NT68275 (5) Character Height Control: Row 15, Column 14 7 Row 15 Column 14 6 CRH6 5 CRH5 4 CRH4 3 CRH3 2 CRH2 1 CRH1 0 CRH0 Character’s Height Control Bit 6-0: CRH6-CRH0 - These bits determine the displayed character height. Character, original 12 by 18 font matrix, can be expanded from 18 to 71 lines. Refer to the table below. All of these bits will be cleared to ‘0’ after power on. If the setting value of CH0 – CH6 is great than 17, the algorithm will repeat at most 17 lines. TAB 4. Lines Expanded Control CRH6 ~ CRH0 CRH6 = ‘ 1 ‘ , CRH5 = ‘ 1 ‘ CRH6 = ‘ 1 ‘ , CRH5 = ‘ 0 ‘ CRH6 = ‘ 0 ‘ , CRH5 = ‘ X ‘ CRH4 = ‘ 1 ‘ CRH3 = ‘ 1 ‘ CRH2 = ‘ 1 ‘ CRH1 = ‘ 1 ‘ CRH0 = ‘ 1 ‘ Lines Inserted All 18 lines repeat twice All 18 lines repeat once Repeat at most 17 lines Insert 16 lines Insert 8 lines Insert 4 lines Insert 2 lines Insert 1 lines TAB 5. Lines Expanded Position No. of Lines Inserted Insert 1 lines Insert 2 lines Insert 4 lines Insert 8 lines Insert 16 lines Insert 17 lines Repeat Position 1 2 3 4 5 6 7 8 9 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 10 11 12 13 14 15 16 17 18 16 NT68275 (6) Flexible Display Control Register : Row 15 , Column 15 7 Row 15 Column 15 6 MSB 5 4 3 HDR 2 1 0 LSB Horizontal Display Resolution Control Bit 6-0: HDR -These bits determine the resolution of the horizontal display line. The unit of this setting is twelve dots (one character). With total 92 steps ($24 ~ $7F: 36 ~ 127 steps; value cannot be smaller than 36 anytime.), user can adjust the resolution from 36 to 127 characters on each horizontal line. Note that the resolution adjustment must cooperate with the VCO setting at row 15 / column 18 control register. Refer to the table of the control register at row 15 / column 18. The default value of it is 40 after power on. (7) OSD Row to Row Space Control Register : Row 15 , Column 16 7 Row 15 Column 16 6 5 4 MSB 3 2 R2RSPACE 1 0 LSB Row To Row Space Adjustment Bit 4-0: R2RSPACE - These bits define the row-to-row spacing in units of horizontal lines. Extra lines defined by this 5-bit value will be appended for each display row. The default value is 0 after power on and there is no extra line inserted between rows. All of these bits will be cleared to ‘0’ after power on. (8) Input/Output Control Register : Row 15 , Column 17 7 Row 15 Column 17 6 5 SHADOW 4 FADE 3 2 1 0 OSDEN BSEN BLANK CLRWIN CLRDSPR FBKGC OSD Screen Control 1 Bit 7: OSDEN – This bit will enable the OSD circuit when it is set to ‘1’. The default value is ‘0’ after power on. Bit 6: BSEN – This bit will enable the bordering and shadowing effect when it is set to ‘1’. The default value is ‘0’ after power on. Bit 5: SHADOW – When the BSEN set to ‘1’, it will enable the shadowing effect when this bit set to ‘1’, too. Otherwise, it will enable the bordering effect as this bit is cleared to ‘0’. The default value is ‘0’ after power on. Bit 4: FADE - This bit enables the fade-in/out effect when the OSD screen is turned on by setting from OSDEN = ’0’ to ‘1’ or turned off by setting from OSDEN = ’1’ to ‘0’. The fade-in/out effect will be completed about 0.5 seconds when the input Vsync is 60 Hz. The default value of this bit is ‘0’ after power on. Bit 3: BLANK – This bit will force the FBKG pin to output high when this bit & the FBKGOP are bit set to ‘1’. Otherwise, the FBKG pin will output low when this bit is set to ‘1’ & FBKGOP bit set to ‘0’. The default value of this bit is ‘0’ after power on. Bit 2: CLRWIN – This bit will clear all windows’ WINEN control bit as it is set to ‘1’. The default value of this bit is ‘0’ after power on. Bit 1: CLRDSPR – This bit will clear all of the content in the display registers and R, G, G, BLNK bit in the character attribute registers when it is set to ‘1’. The default value of this bit is ‘0’ after power on. 17 NT68275 Bit 0: FBKGC - It determines the configuration of FBKG output pin. When it is cleared, the FBKG pin will output high during displaying characters or windows. Otherwise, it will output high only during displaying characters. The default value of this bit is ‘0’ after power on. 18 NT68275 7 6 5 *PWM/INT 4 DBOUNCE 3 HPOL 2 1 0 VCO0 Row 15 RGBF FBKGOP Column 18 VPOL VCO1 OSD Screen Control 2 Bit 7: RGBF - This bit controls the driving state of output pins, R, G, B and FBKG when the OSD is disabled. After power on, this bit is cleared to ‘0’ and all of the R, G, B and FBKG pins output a high impedance state while the OSD is being disabled. If this bit is set to ‘1’, the R, G, B output pins will drive low, FBKG pin drive high or low depend on FBKGOP (If FBKGOP=0, drive high. If FBKGOP=1, drive low) while OSD being disabled. Bit 6: FBKGOP - This bit selects the polarity of the output signal of FBKG pin. This signal is active low when the user clears this bit. Otherwise, active high set this bit. Refer the figure 5 below for the FBKG output timing. The default value is ‘1’ after power on. Bit 5: * PWM/INT - This bit selects the output option to PWM/INT pin. This bit will enable the PWM clock output as it is set to ‘1’. Otherwise, it will select the INT option. Refer the figure 5 bellow for the INT output timing. The default value is ‘0’ after power on. Bit 4: DBOUNCE - This bit is to activate the debounce circuit of horizontal and vertical scan. It is to prevent from the OSD screen shaking when user adjusts the horizontal phase or vertical position. This bit will be cleared after power on. Bit 3: HPOL - This bit selects the polarity of the input signal of horizontal sync (HFLB pin). If the input sync signal is negative polarity, user must clear this bit. Otherwise, set this bit to ‘1’ to accept the positive polarity signal. After power on, this bit is cleared to ‘0’ and it will accept negative polarity sync signal. Bit 2: VPOL - This bit selects the polarity of the input signal of vertical sync ( VFLB pin). If the input sync signal is negative polarity, user must clear this bit. Otherwise, set this bit to ‘1’ to accept the positive polarity signal. After power on, this bit is cleared to ‘0’ and it will accept negative polarity sync signal. Bit 1-0: VCO1/0 – These bits select the VCO frequency range when user set the horizontal display resolution flexibly. It is related to the horizontal display resolution and user must set the control register at row15 / column15 properly. The default value is VCO1=0 & VCO0=0 after power on state. The relationship between VCO1/0 and display resolution is list below: TAB 6. P.R. (Pixel Rate) = HDR * 12 * FreqHFLB Section Freq1 Freq2 Freq3 Freq4 VCO1 0 0 1 1 VCO0 VCO Freq. Min 0 1 0 1 *6 *14 *29 *61 VCO Freq. Max *13 (Min / HDR*12) < *28 *60 *120 MHz Min < P.R. < Max FreqHFLB < Max / (HDR*12) Unit P.R. Limit HFLB Freq. Limit If there are no signals at HFLB input, the PLL will generate an approximate 2.5 MHz clock to ensure the proper operation of the IIC bus and other control registers. 19 NT68275 FBK INT1 INT2 RINT=1 RINT=0 INT1 INT2 Window Backgroun Character Shadowin Character Backgroun Window Backgroun Character Backgroun FBKGC bit = ‘0’ WINT = 0 FBKGC bit = ‘1’ WINT = 1 Figure 5. * FGBK & INT Output Timing 20 NT68275 (10) Color Selection for Shadowing/Bordering Effect: Row 15, Column 19 7 Row 15 Column 19 6 WINR 5 WING 4 WINB 3 2 CHR 1 CHG 0 CHB Shadowing/Bordering Color Control Bit 6-4: WINR/G/B – These bits control the shadowing color of window 1 -4. Refer to Table 7 for color selection. All of these bits will be cleared to ‘0’ after power on. Bit 2-0: CHR/G/B – These bits control the shadowing/bordering color of each character. Refer to Table 7 for color selection. All of these bits will be cleared to ‘0’ after power on. TAB 7 Character/Windows’ Shadowing Color Selection COLOR Black Blue G reen Cyan R ed Magenta Yellow White R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 (11) Multi-Color Font Control: Row 15, Column 20 7 Row 15 Column 20 6 5 4 3 2 1 0 MCFONT Multi-Color Font Control Bit 0: MCFONT – This bit will enable multi-color fonts addressed from 240 to 255 when it is set to ‘1’. The default value is ‘0’ after power on and enable standard ROM fonts. 21 NT68275 (12) Adjustments of Width & Height for Windows’ Shadowing: Row 15, Column 21, 22 7 6 5 4 3 2 1 Row 15 W4WD1 W4WD0 W3WD1 W3WD0 W2WD1 W2WD0 W1WD1 Column 21 0 W1WD0 Setting of Windows’ Shadowing Width WxWD1/0 – This will determine the size of window’s width when the SHAD bit of windows control register (row 15 column 1,4,7,10) be set to ‘1’. The default values are ‘0 0 ‘ after power on. Refer to the TAB below for the size adjustments. W xWD1/0 Window Shadowing Width (0,0) 2 (0,1) 4 (1,0) 6 (1,1) 8 Units Pixels 7 Row 15 W4HT1 Column 22 6 W4HT0 5 W3HT1 4 W3HT0 3 W2HT1 2 W2HT0 1 W1HT1 0 W1HT0 Setting of Window Shadowing Height WxHT1/0 – These bit will determine the window height when the SHAD bit of the window control register (row 15 column 1,4,7,10) is set to ‘1’. The default values are ‘0 0 ‘ after power on. Refer to the TAB below for the size adjustments. WxHT1/0 Window Shadowing Height (0,0) 2 (0,1) 4 (1,0) 6 (1,1) 8 Units Pixels 22 NT68275 (13) Reset Flag Control Registers 7 Row 15 Column 23 6 5 4 3 2 1 RESETFLG 0 B it 1 RESTFLG – A system resetwill clear this bit. User can set this bit first and detect if : internal reset circuit has reset the system. This bit can be read back through IIC bus by external master device, for example MCU. The other bits are reserved. (14) Reserved Control Register: Row 15, Column 24 & 31 7 Row 15 Column 24 6 5 4 3 Reserved 2 1 0 This control register is reserved and any data can not be written into this register. 7 Row 15 Column 31 6 5 4 3 Reserved 2 1 0 This control register is reserved and any data can not be written into this register. IIC Bus Read Mode Operation: 3 ---- 1 bytes data ----4 (3) Row15 Column 23 Data 8 bits Type (a) (1) START Condition (2) OSD Slave Address ‘$7B’ 8 bits (4) STOP Condition User must read these bytes of data sequentially and can abort transmission by sending NAK (no acknowledge), Repeat START condition or STOP condition. Every time user sends the START condition (including Repeat START) and slave address $7B, the NT68275 will respond ACK and then transmit the first byte (content of row5 column3 register). It is prohibited to read more than 1 byte of data. 23 NT68275 IIC Bus Communication: Figure 6 shows the IIC Bus transmission format. The master initiates a transmission routine by generating a START condition, followed by a slave address byte. Once the address is properly identified, the slave will respond with an ACKNOWLEDGE signal by pulling the SDA line LOW during the ninth SCL clock. Each data byte which then follows must be eight bits long, plus the ACKNOWLEDGE bit, to make up nine bits together. This ACKNOLEDGE bit is sent by NT68275 at WRITE mode operation and by master, at READ mode. In the WRITE mode, appropriate row and column address information and display data can be downloaded sequentially from the master in one of the three transmission formats described in Figure 6 Access Register Operation. In the READ mode, the content in some control registers can be transferred to the master. In the cases of no ACKNOWLEDGE or completion of data transfer, the master will generate a STOP condition to terminate the transmission routine. Note that the OSD_EN bit must be set after all the display information has been sent in order to activate the displaying circuitry of NT68275, so that the received in-formation can then be displayed. Write Operation of the Control Registers: After the proper identification by the receiving device, a data train of arbitrary length is transmitted from the master. There are three transmission formats from (a) to (c) as stated below the Timing section. The data train in each sequence consists of row address, column address and data. In format (a), data must be preceded with the corresponding row address and column address. This format is particularly suitable for updating small amounts of data between different rows. However, if the current information byte has the same row address as the one before, format (b) is recommended. For a full screen pattern change which requires a massive information update, or during power up situation, most of the row and column addresses on either (a) or (b) format will appear to be redundant. A more efficient data transmission format (c) should be applied. This sends the starting row and column addresses once only, and then treats all subsequent data as display information. The row and column addresses will be automatically incremented internally for each display information data from the starting location. To differentiate the row and column addresses when transferring data from master, the MSB (Most Significant Bit) is set as in TAB 8 Transmission: ‘1’ represent row, while ‘0’ for column address. Furthermore, to distinguish the column address between format (a), (b) and (c), the sixth bit of the column address is set to ‘1’, which represents format (c), and a ‘0’ for format (a) or (b). There is some limitation on using mix-formats during a single transmission. It is permissible to change the format from (a) to (b), or from (a) to (c), or from (b) to (a), but not from (c) back to (a) or (b). 24 NT68275 IIC Bus Write Operation Timing: Figure. 6 Access Register Write Operation Type (a) (1) START Condition (2) OSD Slave Address ‘$7A’ 8 bits (3) (4) (5) 3 --------------- Repeat --------------4 (3) (4) (5) (6) Row Address Column Address Information Row Address Column Address Information Data Data Data Data Data Data 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits … STOP Condition Type (b) (1) START Condition (2) OSD Slave Address ‘$7A’ 8 bits (3) (4) (5) 3 ------ Repeat -----4 (4) (5) (6) Row Address Column Address Information Column Address Information Data Data Data Data Data 8 bits 8 bits 8 bits 8 bits 8 bits … STOP Condition Type (c) (1) START Condition (2) OSD Slave Address ‘$7A’ 8 bits (3) (4) (5) (5) 3Repeat 4 (5) (6) Row Address Column Address Information Information Information Data Data Data Data Data 8 bits 8 bits 8 bits 8 bits 8 bits … STOP Condition TAB 8. Address Data Transmission for Registers ITEM No 1 2 Display Register 3 4 5 6 Attribute / Control Register 7 8 ADDRESS Row Column Column Information Data Row Column Column Information Data B7 1 0 0 D7 1 0 0 D7 B6 0 0 1 D6 0 0 1 D6 B5 0 B4 X B3 R3 C3 C3 D3 R3 C3 C3 D3 B2 R2 C2 C2 D2 R2 C2 C2 D2 B1 R1 C1 C1 D1 R1 C1 C1 D1 B0 R0 C0 C0 D0 R0 C0 C0 D0 (a),(b),(c) (a),(b) (c) Type (a),(b),(c) (a),(b) (c) *Page C4 *Page C4 D5 1 X X D5 D4 X C4 C4 D4 *The page bit will identify the page number of ROM font area. If this bit is set ‘0’, the following information data will address the page 0 ROM font area. Otherwise, it will address the page 1. 25 NT68275 Read Operation of the Control Registers: Not all control registers can be read out by the master via IIC bus of READ mode. Bellow listed, after the proper identification of slave address ($7B) by the NT68275, 1 byte data train is transmitted to the master. Item 1 Register Row 15 Column 23 Control Register Bytes 1 IIC Bus Read Operation Timing: Figure 7. Access Register Read Operation (1) START Condition Type (a) (2) OSD Slave Address ‘$7B’ 8 bits 3 ---- 1 bytes data ----4 (3) Row15 Column 23 Data 8 bits (4) STOP Condition U ser must read these bytes of data sequentially and can abort transmission by sending NAK (no acknowledge), Repeat START condition or STOP condition. Every time user sends the START condition (including Repeat START) and slave address $7B, the NT68275 will respond ACK and then transmit first byte (content of row 15 column 23 register). It is prohibited to read more than 1 byte of data. 26 NT68275 Font Access: ( 00 ) ( 01 ) ( 02 ) ( 03 ) ( 04 ) ( 05 ) ( 06 ) ( 07 ) ( 08 ) ( 09 ) ( 0A ) ( 0B ) ( 0C ) ( 0D ) ( 0E ) ( 0F ) (10 ) ( 11 ) ( 12 ) ( 13 ) ( 14 ) ( 15 ) ( 16 ) ( 17 ) ( 18 ) ( 19 ) ( 1A ) ( 1B ) ( 1C ) ( 1D ) ( 1E ) ( 1F ) ( 20 ) ( 21 ) ( 22 ) ( 23 ) ( 24 ) ( 25 ) ( 26 ) ( 27 ) ( 28 ) ROM Fonts . . . ( 29 ) ( 2A ) ( 2B ) ( 2C ) ( 2D ) ( 2E ) ( 2F ) ( D0 ) ( D1 ) ( D2 ) ( D3 ) ( D4 ) ( D5 ) ( D6 ) ( D7 ) ( D8 ) ( D9 ) ( DA ) ( DB ) ( DC ) ( DD ) ( DE ) ( DF ) ( E0 ) ( E1 ) ( E2 ) ( E3 ) ( E4 ) ( E5 ) ( E6 ) ( E7 ) ( E8 ) ( E9 ) ( EA ) ( EB ) ( EC ) ( ED ) ( EE ) ( EF ) ( F0 ) ( F1 ) ( F2 ) ( F3 ) ( F4 ) ( F5 ) ( F6 ) ( F7 ) ( F8 ) ( F9 ) ( FA ) ( FB ) ( FC ) ( FD ) ( FE ) ( FF ) Figure 8-1. Page 0 including 256 Standard ROM FONT Configuration ( 00 ) ( 01 ) ( 02 ) ( 03 ) ( 04 ) ( 05 ) ( 06 ) ( 07 ) ( 08 ) ( 09 ) ( 0A ) ( 0B ) ( 0C ) ( 0D ) ( 0E ) ( 0F ) (10 ) ( 11 ) ( 12 ) ( 13 ) ( 14 ) ( 15 ) ( 16 ) ( 17 ) ( 18 ) ( 19 ) ( 1A ) ( 1B ) ( 1C ) ( 1D ) ( 1E ) ( 1F ) ( 20 ) ( 21 ) ( 22 ) ( 23 ) ( 24 ) ( 25 ) ( 26 ) ( 27 ) ( 28 ) ROM Fonts . . . ( 29 ) ( 2A ) ( 2B ) ( 2C ) ( 2D ) ( 2E ) ( 2F ) ( D0 ) ( D1 ) ( D2 ) ( D3 ) ( D4 ) ( D5 ) ( D6 ) ( D7 ) ( D8 ) ( D9 ) ( DA ) ( DB ) ( DC ) ( DD ) ( DE ) ( DF ) ( E0 ) ( E1 ) ( E2 ) ( E3 ) ( E4 ) ( E5 ) ( E6 ) ( E7 ) ( E8 ) ( E9 ) ( EA ) ( EB ) ( EC ) ( ED ) ( EE ) ( EF ) Multi-color ROM Fonts ( F0 ) ( F1 ) ( F2 ) ( F3 ) ( F4 ) ( F5 ) ( F6 ) ( F7 ) ( F8 ) ( F9 ) ( FA ) ( FB ) ( FC ) ( FD ) ( FE ) ( FF ) Figure 8-2. Page 0 including 240 Standard & 16 Multi-color ROM FONT Configuration 27 NT68275 (100 ) ( 101 ) ( 102 ) ( 103 ) (104 ) ( 105 ) ( 106 ) ( 107 ) ( 108 ) ( 109 ) ( 10A ) ( 10B ) ( 10 C ) ( 10D ) ( 10 E ) ( 10F ) (110 ) (111 ) ( 112 ) ( 113 ) ( 114 ) ( 115 ) ( 116 ) ( 117 ) ( 118 ) ( 119 ) ( 11A ) ( 11B ) ( 11 C ) ( 11D ) ( 11 E ) ( 11F ) ( 120 ) ( 121 ) ( 122 ) ( 123 ) ( 124 ) ( 125 ) ( 126 ) ( 127 ) ( 128 ) ROM Fonts . . . ( 129 ) ( 12A ) ( 12B ) ( 12 C ) ( 12D ) ( 12 E ) ( 12F ) ( 1D0 ) ( 1D1 ) ( 1D2 ) ( 1 D3 ) ( 1D4 ) ( 1 D5 ) ( 1D6 ) ( 1D7 ) ( 1D8 ) ( 1D9 ) ( 1 DA ) ( 1DB ) ( 1 DC ) ( 1DD ) ( 1 DE ) ( 1DF ) ( 1E0 ) ( 1E1 ) ( 1E2 ) ( 1 E3 ) ( 1E4 ) ( 1 E5 ) ( 1E6 ) ( 1E7 ) ( 1E8 ) ( 1E9 ) ( 1 EA ) ( 1EB ) ( 1 EC ) ( 1ED ) ( 1 EE ) ( 1EF ) ( 1F0 ) ( 1F1 ) ( 1F2 ) ( 1 F3 ) ( 1F4 ) ( 1 F5 ) ( 1F6 ) ( 1F7 ) ( 1F8 ) ( 1F9 ) ( 1 FA ) ( 1FB ) ( 1 FC ) ( 1FD ) ( 1 FE ) ( 1FF ) Figure 8 –3. * Page 1 including 256 Standard ROM FONT Configuration 28 NT68275 1 2 3 4 5 6 7 8 9 10 1112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Figure 9-1. 12 * 18 Dots Font 1 2 3 4 5 6 7 8 9 10 1112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 1112 Figure 9-2. Bordering Effect Figure 9-3. Shadowing Effect 29 NT68275 OSD Screen Position: Figure 10 below illustrates the position of all display characters on the screen relative to the leading edge of horizontal and vertical fly-back signals. T HPOS *6 + 49 dots HFLB HFLB VFLB VPOS *4 + 1 lines Raster T 30 ( 30*12 =360 D o t s ) u 15 OSD Screen VFLB Figure 10. OSD Screen Position 30 NT68275 OSD Display Format: OSD Screen 0 0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Double Height Double Width 11 12 13 14 15 Line Expanded = 22 lines & Double Width Line Expanded = 22 lines & Double Height Figure 11. OSD Display Format 31 NT68275 OSD Window Setting: 30 Row Start Address Column Start Address Column End Address WINDOW1/2/3/4 15 Row End Address AREA Row Start/End Control Register: row15 /column 0/3/6/9 Column Start Control Register: row15 /column 1/4/7/10 Column End Control Register: row15 /column 2/5/8/11 Window Color Control Register: row15 /column 2/5/8/11 Figure 12. Window Size Setting WIDTH HEIGHT S h a d o w C o l o r S e l e c t i o n C o n t r o l R e g i s t e r: row15 /column 19 WINDOW AREA W i d t h A d j u s t m e n t C o n t r o l R e g i s t e r: row15 /column 21 H e i g h t A d j u s t m e n t C o n t r o l R e g i s t e r: row15 /column 22 HEIGHT Note : Width Adjustment Units : Pixels Height Adjustment Units : H Lines WIDTH OSD SCREEN AREA ( 15 row by 30 column ) Figure 13. Window Shadowing Setting 32 NT68275 Characters’ Programmable Height: TAB 9. Line Expanded Example 1: If user sets CRH0 = 1, CRH2= 1, CRH3= 1 Line Original Font CRH0 CRH2 CRH3 CH4 – CH 0 = 18 Result : 35 lines 18+17 1 ! 2 ! 3 ! 4 ! 5 ! 6 ! 7 ! 8 ! 9 ! ! 10 11 12 13 14 15 16 17 18 ! ! ! ! ! ! ! ! ! ! ! ! !! ! !! ! ! !! ! ! ! !! ! ! !! ! ! ! !! ! ! !! ! ! ! !! ! ! !! ! ! ! !! ! ! !! ! ! ! !! ! ! !! ! ! ! !! ! ! !! ! ! ! !! ! ! !! ! Example 3: If user sets CRH1 = 1, CRH3 = 1, CH5 = 0, CH6 = 1 Line Original Font CRH1 CRH3 CH4 – CH0 < 18 CRH6,5=(1,0) Result : 46 lines 18+( 8 * CRH3 ) + (2*CRH1)+ 18 * 1 1 ! 2 ! 3 ! 4 ! 5 ! ! 6 ! 7 ! 8 ! 9 ! 10 11 12 13 14 15 16 17 18 ! ! ! ! ! ! ! ! ! ! ! ! ! !! ! !!! ! !! ! ! ! ! ! ! ! ! ! !! ! ! ! !!! ! !! ! ! ! !!! ! !! ! ! ! ! ! ! ! ! ! !! ! ! ! !!! ! !! ! !! !!! !!! !!! !!! !!! !!! 33 NT68275 Multi-color Font Operation: Red Green Cyan R G B O/P Multi-color Font Figure 14. Multi-Color Font Example above, the NOVATEK logo is consisted of four fonts. The R, G, B output channels will send out their corresponding font data and it can then display multiple colors in the same font. When using the multi -color font, it can not be set as black and the bordering and shadowing are not available. 34 NT68275 Figure 15-1. Font Code Example 35 NT68275 Figure 15-2. Font Code Example (continued) 36 NT68275 Application Circuit Vcc . 220 uf . . .. 1M 0.01uf . 5.6K 5.6 K 12 K 0.01uf . 1 2 3 4 5 AGND VCO RP AVCC HFLB NC SDA SCL DGND 16 R G B FBKG PWM/ /INT VFLB DVCC 15 14 13 12 11 10 9 470 470 470 470 220 0.1 uf HFLB 100 p f . 6 7 8 .... . .. . . .. 100 p f Vcc 0.1u f R G B FBKG PWMCLK/INT VFLB 100 p f 220u f SCL SDA NT68275 Application Circuit 37 NT68275 Package Information P-DIP 16L Outline Dimensions D 16 9 unit: inches/mm E1 1 S 8 E C A2 A A1 Base Plane Seating Plane B B1 e1 eA L α Symbol A A1 A2 B B1 C D E E1 e1 L α eA S Dimension in inch Dimension in mm 0.175 Max. 4.45 Max. 0.010 Min. 0.25 Min. 0.130±0.010 3.30±0.25 0.018 +0.004 0.46 +0.10 -0.002 -0.05 0.060 +0.004 1.52 +0.10 -0.002 -0.05 0.010 +0.004 0.25 +0.10 -0.002 -0.05 0.750 Typ. (0.770 Max.) 19.05 Typ. (19.56 Max.) 0.300±0.010 7.62±0.25 0.250 Typ. (0.262 Max.) 6.35 Typ. (6.65 Max.) 0.100±0.010 2.54±0.25 0.130±0.010 3.30±0.25 0°~ 15° 0°~ 15° 0.345±0.035 0.040 Max. 8.76±0.89 1.02 Max. Note: 1 . The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end fl ash. 38