NT68P81-D01013

NT68P81 USB Keyboard Micro-Controller Features n Built-in 6502C 8 -bit CPU n 3 MHz CPU operation frequency when oscillator is running at 6 MHz n 6K bytes of OTP (one time programming) ROM n 256 bytes of SRAM n O ne 8-bit programmable base timer with pre-divider circuit n 2 9 programmable bi-directional I/O pins including two external interrupts n n n n n n n n n 3 LED direct sink pins with internal serial resistors On-chip oscillator (Crystal or Ceramic Resonator) Watch-dog timer reset Built-in power-on reset USB interface 3 supported endpoints Remote wakeup provided CMOS technology for low power consumption 40-pin DIP package, 42-pad Dice form and COB General Description The NT68P81 is a single chip micro-controller for USB keyboard applications. It incorporates a 6502C 8 -bit CPU core, 6K bytes of OTP ROM, and 256 bytes of RAM used as working RAM and stack area. It also includes 29 programmable bi-directional I/O pins with built-in resistors, and one 8-bit pre-loadable base timer. Additionally, it includes a built-in power-on reset, a builtin low voltage reset, an oscillator that requires crystal or ceramic resonator applied, and a watch-dog timer that prevents system standstill. Pin Configuration Pad Configuration P 1 5 P 1 4 24 P 1 3 23 P 1 2 22 P 1 1 21 P 1 0 20 P 0 7 19 P 0 6 18 P 0 5 17 GND VCP VDP VDM [OE] P30 [PGM] P31 INT0/P32 INT1/P33 P34 [VPP] RESET [A0] P00 [A1] P01 [A2] P02 [A3] P03 [A4] P04 [A5] P05 [A6] P06 [A7] P07 [A8] P10 [A9] P11 1 2 3 4 5 6 7 8 40 39 38 37 36 35 34 33 OSCI OSCO VD D LED2 [MODE2] LED1 [MODE1] LED0 [MODE0] P27 [DB7] P26 [DB6] P25 [DB5] P24 [DB4] P23 [DB3] P22 [DB2] P21 [DB1] P20 [DB0] P17 P16 P15 [CE] P14 [A12] P13 [A11] P12 [A10] L E D 2 V C C V C C O S C O O S C I G N D G N D V C P V D P V D M P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 LED0 LED1 26 28 27 28 28 29 12 30 31 32 33 34 35 36 37 38 39 40 41 42 1 2 3 4 5 7 6 9 8 14 13 16 15 25 P04 P03 P02 P01 P00 RESET P34 P33 P32 P31 P30 9 10 11 12 13 14 15 16 17 18 19 20 32 31 30 29 28 27 26 25 24 23 22 21 NT68P81 11 10 NT68P81 1 V2.0 NT68P81 Block Diagram OSCI Timing Generator OSCO Power Down/Up Transceiver VCP VDP VDM SIE 6502 CPU 6K Bytes OTP ROM Serial Bus Manager 256 Bytes SRAM FIFOs Watch Dog Timer V DD GND RESET Power-On Reset Base Timer I/O PORTs Interrupt Controller LED0 LED1 LED2 P00~P07 P10~P17 P20~P27 P30~P34 2 NT68P81 Pin and Pad Descriptions Pin No. 1 2 3 4 5 Pad No. 1,2 3 4 5 6 Designation GND VCP VDP VDM P30 I/O P O I/O I/O I/O OE [I] I/O 6 7 8 9 10 7 8 9 10 11 P31 PGM [I] P32/INT0 P33/INT1 P34 RESET Shared with OTP[I/O] Ground Description USB 3.3V driver USB data plus USB data minus Bi-directional I/O pin Program output enable Bi-directional I/O pin Program control Bi-directional I/O shared with INT0 Bi-directional I/O shared with INT1 Bi-directional I/O pin Internally pulled down resistor VPP [P] Program supply voltage Bi-directional I/O pin A0 ~ A7 [I] Program address buffer Bi-directional I/O pin A8 ~ A12 Program address buffer Bi-directional I/O pin CE [I] Program chip enable Bi-directional I/O pin VPIH[I] OTP Program Input Voltage High Bi-directional I/O pin Bi-directional I/O pin DB0 ~ DB7 [I/O] Program data buffer LED direct sink MODE0 [I] Mode selection LED direct sink MODE1 [I] Mode selection LED direct sink MODE2 [I] Mode selection Power supply (+5V) Crystal oscillator output CLK[I] Program Clock I/O I/O I/O I 11 ~ 18 12 ~ 19 P00 ~ P07 I/O 19 ~ 23 20 ~ 24 P10 ~ P14 I/O 24 25 P15 I/O 25 26 27 ~ 34 26 27 28 ~ 35 P16 I/O P17 P20 ~ P27 I/O I/O 35 36 LED0 O 36 37 LED1 O 37 38 39 38 39,40 41 LED2 O VDD OSCO P O 3 NT68P81 40 * [ ]: OTP Mode 42 OSCI I VPIL[I] Crystal oscillator input OTP Program Input Voltage Low 4 NT68P81 Functional Description 1. 6502C CPU The 6502C is an 8 -bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory range, and an interrupt input. Other features are also included. The CPU clock cycle is 3MHz (6MHz system clock divided by 2). Please refer to 6502 data sheet for more detailed information. 7 Accumulator A 7 Index Register Y 7 Index Register X 15 Program Counter PCH PCL 7 7 Stack Pointer SP 7 N V B D I Z 0 0 0 8 0 0 0 C Status Register P Carry Zero IRQ Disable Decimal Mode BRK Command Overflow Negative 1 = TRUE 1 = Result ZERO 1 = DISABLE 1 = TRUE 1 = BRK 1 = TRUE 1 = NEG Figure 1. 6502 CPU Registers and Status Flags 5 NT68P81 2.Instruction Set List Instruction Code ADC AND A SL BCC BCS BEQ BIT BMI BNE B PL BRK B VC BVS CLC CLD CLI CLV CMP CPX CPY DEC DEX DEY EOR INC INX INY JMP JSR Meaning Add with carry Logical AND Shift left one bit Branch if carry clear Branch if carry set Branch if equal to zero Bit test Branch if minus Branch if not equal to zero Branch if plus Break Branch if overflow clear Branch if overflow set Clear carry Clear decimal mode Clear interrupt disable bit Clear overflow Compare accumulator to memory Compare with index register X Compare with index register Y Decrement memory by one Decrement index X by one Decrement index Y by one Logical exclusive-OR Increment memory by one Increment index X by one Increment index Y by one Jump to new location Jump to subroutine Operation A + M + C → A， C A• M → A C ← M7••• M0 ← 0 Branch on C＝ 0 Branch on C＝ 1 Branch on Z＝ 1 A• M， M7 → N， M6 → V Branch on N＝ 1 Branch on Z＝ 0 Branch on N＝ 0 Forced interrupt PC + 2↓ P C↓ Branch on V＝ 0 Branch on V＝ 1 0→ C 0→ D 0→ I 0→ V A－M X－ M Y－M M－1→M X－ 1 → X Y－1→Y A ♁ M→ A M+1→ M X+1 → X Y+1→ Y (PC + 1) → PCL， (PC + 2) → PCH PC + 2↓， (PC + 1) → PCL， (PC + 2) → PCH 6 NT68P81 Instruction Set List (contiuned) Instruction Code LDA LDX LDY LSR NOP ORA PHA PHP PLA PLP ROL ROR RTI RTS S BC S EC S ED SEI STA STX STY TAX TAY TSX TXA TXS TYA Meaning Load accumulator with memory Load index register X with memory Load index register Y with memory Shift right one bit No operation Logical OR Push accumulator on stack Push status register on stack Pull accumulator from stack Pull status register from stack Rotate left through carry Rotate right through carry Return from interrupt Return from subroutine Subtract with borrow Set carry Set decimal mode Set interrupt disable status Store accumulator in memory Store index register X in memory Store index register Y in memory Transfer accumulator to index X Transfer accumulator to index Y Transfer stack pointer to index X Transfer index X to accumulator Transfer index X to stack pointer Transfer index Y to accumulator M→A M→X M→Y 0 → M7••• M0 → C No operation (2 cycles) A+M→A A↓ P↓ A↑ P↑ C ← M7••• M0 ← C C → M7••• M0 → C P ↑ ， PC ↑ PC ↑ ， PC+1 → P C A － M － C → A， C 1→ C 1→ D 1→ I A →M X→M Y →M A→X A→Y S→X X→ A X→ S Y→A Operation *For more detailed specifications, pleas e refer to 6502 programming data book. 7 NT68P81 3. OTP ROM: 6K X 8 bits The built-in OTP ROM program code, executed by the 6502 CPU, has a capacity of 6K x 8-bit and is addressed from E800H to FFFFH. It can be programmed by the universal EPROM writer through a conversion adapter and programming configuration such as INTEL - 27C64. In the OPERATING mode, the OTP ROM is integrated with the system and it cannot be directly accessed. When the user wants to work with the OTP ROM alone, the user must first enter the PROGRAMMING mode by setting: PIN < RESET = VPP>. At this time, through multiplex pins, we can use familiar procedures to program and verify the OTP ROM block with the universal programmer. OTP ROM Mega Cell D.C. Electrical Characteristics (READ Mode) (VDD = 5V, TA = 25℃, unless otherwise specified) Symbol VIH VIL IIL IOH IOL IDD ISTB1 Note: Operating Current Standby Current Input Current Output Voltage -400 1 1 100 Parameter Input Voltage Min. VDD - 0.3 -0.3 Typ. Max. VDD + 0.3 0.3 +/-10 Unit V V µA µA mA mA µA VDD = 5V, VOH = 4.5V VDD = 5V, VOL = 0.5V F = 3MHz 2 3 Test Conditions Note 1 1 1. All inputs and outputs are CMOS compatible 2. F = 3MHz, l out = 0mA, CE = VIH. VDD = 5V 3. CE = VIH, OE = VIL, VDD = 5V OTP ROM Mega Cell A.C. Electrical Characteristics (READ Mode) (VDD = 5V, TA = 25℃, unless otherwise specified) Symbol Tcyc T12 Tacc Tce Tst Toh Cycle Time Non-overlap Time to PH1 & PH2 Address Access Time OTPCE to Output Valid Output Data Setup Time Output Data Hold Time 20 0 Parameter Min. 250 5 65 145 145 Max. Unit ns ns ns ns ns ns 4.5V < VDD < 5.5V Conditions OTP ROM Mega Cell A.C. Test Conditions Output Load Input Pulse Rise and Fall Times Input Pulse Levels Timing Measurement Reference Level 1 CMOS Gate and CL = 10pF 10ns Max. 0V to 5V Inputs 0V and 5V Outputs 0.3V and 4.7V 8 NT68P81 OTP ROM Mega Cell Timing Waveforms (READ mode) T12 T cyc PH1 PH2 A0 - A14 OTPCE DB0 - DB7 Tacc & Tce Tst Toh OTP ROM Mega Cell D.C. Electrical Characteristics (PROGRAMMING Mode) (VDD = 5V, TA = 25℃, unless otherwise specified) Symbol VDD VPP VIH VIL IIL IOH IOL IDD IPP CLK VPIH VPIL Input Clock Input Voltage 2 -0.3 53.203424 VDD + 0.3 0.6 Operating Current Output Current Output Current -400 1 30 20 Input Voltage Parameter Supply Voltage 10.5 2 -0.3 Min. Typ. 6 Max. 6.5 12.75 VDD + 0.3 0.6 +/-10 Unit V V V V μA μA mA mA mA MHz V V VPP = 12.75V VDD = 5V, VOH = 4.5V VDD = 5V, VOL = 0.5V Test Conditions Note 4 9 NT68P81 Note: 4. For reliability concerns, we suggest V = 6V & VPP = 12.75V for testing OTP ROM AC characteristics in DD PROGRAMMING mode, and the same condition is suggested for universal programmer supply voltage. OTP ROM Mega Cell A.C. Electrical Characteristics (PROGRAMMING Mode) (TA = 25℃, unless otherwise specified) Symbol Tms Tmh Tas Tah Tces Tceh Tds Tdh Tvs Tpw Tdv Tdf Parameter Mode Decode Setup Time Mode Decode Hold Time Address Setup Time A ddress Hold Time CE Setup Time CE Hold Time Date Setup Time Data Hold Time VPP Setup Time Program Pulse Width OE to Output Valid OE to Output High-Z Min. 2 2 2 2 2 2 2 2 2 100 150 90 Typ. Max. Unit µs µs µs µs µs µs µs µs µs µs ns ns CE = VIL Test Conditions Note OTP ROM Mega Cell A.C. Test Conditions Output Load Input Pulse Rise and Fall Times Input Pulse Levels Timing Measurement Reference Level 1 TTL Gate and C L = 100pF 10ns max. 0.45V to 2.4V Inputs 0.8V and 2.2V Outputs 0.8V and 2.4V 10 NT68P81 OTP ROM Mega Cell Timing Waveform (Program) Tms Tmh MODE DEC. TEST = VPP, MODE [0..2] = 000; Tvs VPP Tas A0 - A14 Tah CE Tces OE Tceh Tdf DB0 - DB7 D IN Tdv DOUT PGM Tds Tpw Tdh Note: 5. VDD must be applied simultaneously or before VPP and cut off simultaneously or after VPP. 6. Removing the device from the socket or setting the device in socket with VPP = 12.75V may cause permanent damage. 11 NT68P81 OTP ROM Mega Cell Mode Selection RESET = 12.75V, VPIL = VIL, VPIH = VIH not VPP VPP VPP VPP VPP VPP VPP VPP VPP VPP Mode [0..2] Mode CE OE VPP DB0-DB7 － 000 000 000 000 001 010 011 100 101 Normal Operating Output Disable Program Program Verify Program Inhibit (Standby) Security (Program) Word-line Stress Bit-line Stress OTP Row (after pkg) OTP Column (after pkg) － － VIH VIH VIL VIH － － VIH VIH － VIH VIH VIL － － － － VIH VIH － － VPP － VPP VPP VPP VPP VPP VPP － high-Z data in data out high-Z data in － “0” data in data in *The security byte is at $0000 address. READ MODE The NT68P81's OTP ROM mega cell has 2 control pins. The CE (chip enable) controls the operation power and is used for device selection. The OE (output enable) controls the output buffers. OUTPUT DISABLE MODE If OE = VIH, the outputs will be in a high impedance state. So two or more ROMs can be connected together on a common bus. STANDBY MODE By applying a low level to the chip is in standby mode, it will reduce the operating current to 100µA. PROGRAM MODE Initially, all bits are in "1" state which is an erased state. Thus the program operation is to introduce "0" data into the desired bit locations by electronic programming. When the VPP input is at 12.75V and CE is at VIH, the chip is in the PROGRAMMING mode. PROGRAM VERLFY MODE The VERIFY mode will check to see that the desired data is correctly programmed on the programmed bit. The VERIFY is accomplished with CE at V , VPP input is at IH 12.75V, and OE = VIL. PROGRAM INHIBIT Using this mode, programming of two or more OTP ROMs in parallel with different data is accomplished. All inputs except for CE and OE may be commonly connected. The TTL high level program pulse is only applied to the CE of the desired device and TTL high level signal is applied to the other devices. 12 NT68P81 4. SRAM: 256 X 8 bits The built-in SRAM is used for general purpose data memory and for stack area. SRAM is addressed from 0080H to 017FH. Because the 6502C default stack pointer is 01FFH, the stack area will map $01FF-$0180 to $00FF-$0080, thus the programmer can set the “S” register to 7FH when starting program, allowing stack point to be 017FH. as; LDX TXS #$7F $0000 $001F System Registers Unused $0080 $00FF $0100 $017F RAM RAM stack pointer Unused $E800 ROM $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF NMI-L NMI-H RST-L RST-H IRQ-L IRQ-H IRQ Vector RESET Vector NMI Vector 13 NT68P81 5. System Reserved Registers Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $ 000F Register IRQFUNC IRQCLRF IE_FUNC IRQUSB IRQCLRU IE_USB BT TCON TMOD PORT0 PORT1 PORT2 PORT3 LED CLRWDT MODE_FG Reset 00H 00H 00H 00H 00H 00H 00H 01H 00H FFH FFH FFH 1FH 07H 00H 02H Bit 7 － － － SUSP CSUSP ESUSP BT7 － － P07 P17 P27 － － 0 － Bit 6 － － － STUP CSTUP ESTUP BT6 － － P06 P16 P26 － － 1 － Bit 5 － － － － － － BT5 － － P05 P15 P25 － － 0 － Bit 4 － － － － － － BT4 － － P04 P14 P24 P34 － 1 － Bit 3 KBD CKBD EKBD IN2 CIN2 EIN2 BT3 － － P03 P13 P23 P33 － 0 － Bit 2 INT1 CINT1 EINT1 IN1 CIN1 EIN1 BT2 － TM2 P02 P12 P22 P32 LED2 1 － Bit 1 INT0 CINT0 EINT0 OT0 COT0 EOT0 BT1 － TM1 P01 P11 P21 P31 LED1 0 POF Bit 0 TMR CTMR ETMR IN0 CIN0 EIN0 BT0 R/W R W R/W R W R/W W W R/W R/W R/W R/W R/W W W R/W ENBT TM0 P00 P10 P20 P30 LED0 1 SUSF － : no effect 6. Power-on Reset Built-in power-on reset circuit can generate a minimum of 5ms pulse to reset the entire chip. The user also can use an external RESET pin to reset the entire chip. 7. Timing Generator This block generates the system timing and control signals supplied to the CPU and on-chip peripherals. The crystal oscillator generates a 6MHz system clock. It only generates 3MHz clock for CPU. 14 NT68P81 8. Base Timer (BT) The Base Timer is an 8 -bit counter with a programmable clock source selection. The BT can be enabled/disabled by the CPU. After reset, the BT is disabled and cleared. The BT can be preset by writing a preset value to BT7 ~ BT0 of the BT register at any time. When the BT is enabled, the BT starts counting from the preset value. When the value reaches FFH, it generates a timer interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the BT will wrap around and begin counting at 00H. The BT can be enabled by writing a "0" to " ENBT " bit in the TCON (Timer Control) register. The ENBT signal is level trigger. The input clock source of BT is controlled by the TMOD register. The following table shows 8 ranges of the BT. TM2 0 0 0 0 1 1 1 1 TM1 0 0 1 1 0 0 1 1 TM0 0 1 0 1 0 1 0 1 Pre-scalar Ratio System Clock/2 3 System Clock/2 4 System Clock/2 5 System Clock/2 6 System Clock/2 7 System Clock/2 8 System Clock/2 9 System Clock/2 10 Min. Count 1 .33 µs 2 .66 µs 5 .32 µs 1 0.64 µs 2 1.28 µs 4 2.56 µs 8 5.12 µs 1 70.24 µs Max. Count 341.33 µs 682.66 µs 1.36 ms 2.72 ms 5.44 ms 10.89 ms 21.79 ms 43.58 ms For counting accuracy, please set the TMOD register first, then preset the BT register, and enable the base timer finally. (TM2, TM1, TM0) = (1, 1, 1) is reserved for USB driver use. 15 NT68P81 9. Interrupt Controller There are 10 interrupt sources: Timer, INT0, INT1, KBD, SUSP, IN0, IN1, IN2, OT0 and STUP. 9.1. Timer Interrupt When the BASE TIMER overflows, it will set the TMR flag, If the interrupt is enabled by writing "1" to the bit 0 in IE_FUNC ($0002H), then it will interrupt 6502 CPU. The TMR flag can be read by the software. Once set by an interrupt source, it can read from bit0 in IRQFUNC ($0000H) and remains high unless cleared by writing "1" to the bit 0 in IRQCLRF ($0001H). All of register's data is cleared to "0" at initialization by the system reset. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, thus the TMR flag must be cleared by the software. 9.2. INT0 Interrupt As soon as INT0 pin detects a falling edge trigger, NT68P81 sets the INT0 flag ($0000H, bit1). After that, the 6502 CPU is interrupted if this interrupt has been already been enabled by writing “1” to EINT0 ($0002H, bit1). If the EINT0 flag is cleared, the 6502 CPU can’t be INT0 interrupted even if the INT0 flag is set. INT0 flag can be only be set by hardware and cannot be set or cleared directly by the software except for writing “1” to CINT0 ($0001H, bit1) flag to clear INT0 flag. When an interrupt occurs, the CPU will jump to $FFFEH & $FFFFH to execute the interrupt service routine so the INT0 flag must be cleared by software. 9.3. INT1 Interrupt As soon as the INT1 pin detects a falling edge trigger, NT68P81 sets the INT1 flag ($0000H, bit2). Then the 6502 CPU is interrupted if the interrupt has already been enabled by writing “1” to EINT1 ($0002H, bit2). If EINT0 flag is cleared, the 6502 CPU can’t be INT1 interrupted even if INT1 flag is set. INT1 flag can only be set by the hardware and can not be set or cleared directly by the software except for writing “1” to CINT1 ($0001H, bit2) flag to clear INT1 flag. When an interrupt occurs, CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the INT1 flag must be cleared by the software. 9.4. KBD Interrupt This interrupt will set the KBD flag ($0000H, bit3) every 4ms(HID 1.00 version) to indicate that keyboard scan data is ready to send for endpoint1. Then the 6502 CPU is interrupted if this interrupt has been enabled already by writing “1” to EKBD ($0002H, bit3). If the EKBD flag is cleared, the 6502 CPU can’t be KBD interrupted even if the KBD flag is set. The KBD flag can only be set by the hardware and can not be set or cleared directly by the software except for writing “1 ” to CKBD ($0001H, bit 3) flag to clear KBD flag. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the KBD flag must be cleared by the software. 9.5. IN0 Token Interrupt When an IN TOKEN for endpoint 0 is done, it will set the IN0 flag. If this interrupt is enabled by writing "1" to EIN0 ($0005H, bit0), it will interrupt 6502 CPU. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN0 flag must be cleared by the software. 9.6. OT0 (OUT 0) Token Interrupt When an OUT TOKEN for endpoint 0 is done, it will set the OT0 flag. If this interrupt is enabled by writing "1" to EOT0 ($0005H, bit1), it will interrupt 6502 CPU. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the OT0 flag must be cleared by the software. 16 NT68P81 9.7. IN1 Token Interrupt When an IN TOKEN for endpoint 1 is done, it will set the IN1 flag. If this interrupt is enabled by writing "1" to EIN1 ($0005H, bit2), it will interrupt the 6502 CPU. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN1 flag must be cleared by the software. 9.8. IN2 Token Interrupt When an IN TOKEN for endpoint 2 is done, it will set the IN2 flag. If this interrupt is enabled by writing "1" to EIN2 ($0005H, bit3), it will interrupt 6502 CPU. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN2 flag must be cleared by the software. 9.9. STUP (SETUP) Token Interrupt When a SETUP TOKEN for endpoint 0 is done, it will set the STUP flag. If this interrupt is enabled by writing "1" to ESTUP ($0005H, bit6), it will interrupt 6502 CPU. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the STUP flag must be cleared by the software. 9.10. SUSP Interrupt When USB SIE detects a suspend signal, it sets the SUSP flag. Then the 6502 CPU is interrupted if the interrupt has already been enabled by writing “1” to ESUSP ($0005H, bit7). If ESUSP flag is cleared, 6502 CPU can’t be SUSP interrupted even if SUSP flag is set. SUSP flag can be set by H/W only and can’t be set/cleared directly by the software except for writing “1” to CSUSP ($0004H, bit 7) flag to clear SUSP flag. When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the SUSP flag must be cleared by the software. 10. I/O PORTs The NT68P81 has 32 pins dedicated to input and output. These pins are grouped into 5 ports, as follows: PORT0 (P00~P07) PORT0 is an 8-bit bi-directional CMOS I/O port that is internally pulled high by PMOS. Each pin of PORT0 can be bit programmed as an input or output port under software control. When programmed as output, data is latched to the port data register and output to the pin. PORT0 pins with “1” written to them are pulled high by the internal PMOS pull-ups, and can be used as inputs in that state, then these input signals can be read. The port will output high after the reset. PORT1 (P10~P17): Functions the same as PORT0. PORT2 (P20~P27): Functions the same as PORT0. PORT3 (P30~P34): Functions the same as PORT0. Except for P33/P32 is shared with INT1/INT0 pin. It is also a Schmitt Trigger input with an interrupt source of falling edge sensitive. LED: There are three LED direct sink pins which require no external serial resistors. The address is mapped to $000DH. 17 NT68P81 11. Watch-Dog Timer (WDT) The NT68P81 has a watch-dog timer reset function that protects programs against system standstill. The clock of the WDT is derived from the crystal oscillator. The WDT interval is about 0.15 seconds when the operation frequency is 6MHz. The timer must be cleared every 0.15 second during normal operation; otherwise, it will overflow and cause a system reset (This cannot be disabled by the software). Before watch-dog reset occurs, the software will clear the watch-dog register by writing #55H to CLRWDT ($000EH) register. For example: LDA STA #$55H $000E 12. Power Control The power-off flag (POF) in the MODE_FG register indicates whether a reset is a warm start or a cold start reset. POF is set by hardware when an external power VCC arises to its normal operating level, and must be cleared by the software in the cold reset initialization procedure. A warm start reset (POF = 0) occurs at a watch-dog reset or resume reset. Address $000FH Register MODE_FG Reset 02H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 POF Bit 0 SUSF R/W R/W 13. Universal Serial Bus Interface Please refer to the UNIVERSAL SERIAL BUS specification Version 1.0 Chapter 7, 8, and 9. 14. Suspend and Resume Suspend: When SIE receives the suspend signal, NT68P81 generates a SUSP interrupt request. In the SUSP interrupt service routine, the software will carry out the following steps: 1) 2) 3) 4) 5) 6) Clear SUSP IRQ flag, Store all the port status, Force return lines (PORT2) pull-high, Force scan lines (PORT0, PORT1 and P30, P31 or P32) pull-low, Turn off LED output, Clear watch-dog register After the above action has been completed, the software will then set SUSLO ($1EH) to #55H and SUSHI ($1FH) to #AAH in order to enter the SUSPEND mode. The oscillator will stop for in order to save power. Resume: When the SIE detects a resume signal, the NT68P81 trigger oscillator to oscillate and resets whole chip. After a reset, software checks the status of POF bit in MODE_FG register to see whether a cold start reset or a warm start reset occurred. If cold reset, it executes all initial procedure. If warm reset, software checks the status of SUSF bit in MODE_FG register to see whether a watch-dog reset or resume reset. Under resume reset condition, programmer should restores all port status. After a warm start, user software should clear the SUSF bit. When any key stroked in suspend mode, it remotely resume NT68P81 functions. The action is same as host resume. 18 NT68P81 15. Reset Source Summary These are 5 reset sources in NT68P81 as shown below. No. 1 2 3 4 5 Type Cold Cold Cold Warm-1 Warm-2 Function External Pin ( RESET ) Power-on Reset USB Reset Signaling Resume Reset Watch-dog Reset Description Applied Externally Reset after Power-on 10 ms Reset Period USB Reset Period Reset every 0.15S (OSC = 6MHz) NT68P81 can also be reset externally through the RESET pin. A reset is initialed when the signal at the RESET pin is held Low for at least 10 system clocks. When RESET signal goes high, the NT68P81 begins to work. The following shows the definition of RESET input low pulse width. VDD VDD 2 0%VDD Trstb 20%VDD 16. PS/2 Mouse Application A PS/2 mouse interface is implemented in P32 (CLK), P33 (DATA) and P34 (Power Control). The timing diagrams are described as follows. 1st CLK T1 T3 T2 T4 T1A T5 2nd CLK 10th CLK 11th CLK CLK DATA Start Bit Bit 0 Parity Bit Stop Bit Auxiliary Device Sending Data Timings Timing T1 T1A T2 T3 T4 T5 Description Time from DATA transaction to falling edge of CLK 1 Time from DATA transaction to falling edge of CLK 2-11 Time from rising edge of CLK to DATA transaction Duration of CLK inactive (LOW) Duration of CLK active (HIGH) Time to Auxiliary Device inhibit after clock 11 to ensure the Auxiliary Device does not start another transmission MIN/MAX 5/25u s 5/25u s 5/T4-5 u s 30/50u s 30-50u s >0/50u s 19 NT68P81 CLK I/O Inhibit 1st CLK T6 T8 T7 2nd CLK 9th CLK 10th CLK 11th CLK T9 T10 DATA Start Bit Bit 0 Parity Bit Stop Bit Line Control Bit Auxiliary Device Receiving Data Timings Timing T6 T7 T8 T9 T10 Description Duration of CLK interface (LOW) Duration of CLK active (HIGH) Time from inactive to active CLK transition, used to time when the Auxiliary Device samples DATA Time from falling edge of line control bit to falling edge of clock 11 CLK Time from rising edge of clock 11 to rising edge of line control bit MIN/MAX 30/50u s 30/50u s 5/25 u s 5 u s/ 5/25 u s 20 NT68P81 Absolute Maximum Rating* DC Supply Voltage . . . . . . . . . . . . . . . . . . -0.3V to +7.0V Input/Output Voltage . . . . . . . .GND - 0.2V to VDD + 0.2V Operating Ambient Temperature . . . . . . . . .0 °C to 70 °C Storage Temperature . . . . . . . . . . . . . .-55 °C to +125 °C Operating Voltage (VDD ) . . . . . . . . . . . . .+4.4V to +5.25V *Comments Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical characteristics (VDD = 5V, GND = 0V, TA = 25°C, FOSC = 6MHz, unless otherwise noted) Symbol VDD IOP ISP VIH VIL VOH VOL1 VOL2 ILED VSTIH VSTIH Parameters Operating Voltage Operating Current Suspend Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage (P0/P1/P2) Output Low Voltage (P3) LED Sink Current Schmitt Trigger Input High Voltage Schmitt Trigger Input Low Voltage 0.8 6 10 1.7 1.1 2.4 0.4 0.4 14 2 2 0.8 Min. 4.4 Typ. 5 Max. 5.25 20 500 Unit V mA µA V V V V V mA V V IOH = -100µA IOL1 = 4 mA IOL2 = 5 mA VOL = 3.2V No load Conditions AC Electrical characteristics (VDD = 5V, GND = 0V, TA = 25°C, FOSC = 6MHz, unless otherwise noted) Symbol FOSC TRSTB TPOR Parameters Oscillator Frequency RESET Input Low Pulse Width Power-on Reset Time Min. 5.97 1.67 5 30 Typ. 6 Max. 6.03 Unit MHz µs ms Conditions OSC within +/- 0.5% 10 system clocks USB DC/AC SPECIFICATIONS Please refer to the UNIVERSAL SERIAL BUS specification Version 1.0 Chapter 7. 21 NT68P81 Application Circuit 1 (Simple Keyboard with PS/2 Mouse) VC C PS/2 Mouse CLK PS/2 Mouse DATA PS/2 Mouse Power Control P32 P33 P34 Vcc 10 µF GND 0.1 µF P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31 LED0 Scroll Lock LED1 Num Lock LED2 N T68P81 RESET Caps Lock *1 4.7KO OSCI *1 : RESET can be direct connect to VCC if the external reset is not used for module test. OSCO P20 P21 P22 P23 P24 P25 P26 P27 VDP VDM 6Mhz Crystal D+ To USB Cable D1.5KO VCP 4 . 7µF P20 E R U I O + (Num) 9 PgUp 8 7 Home P21 F3 T Y } ] F7 K107 6 5 (Num) 4 L-Shift P22 D F J K L Enter (Num) 3 PgDn 2 1 End R-Shift | \ (K29) : ; 000 00 P23 F4 G H F6 P24 C V M < , > . P25 K133 B N K56 APP P26 F2 % 5 ^ 6 + = F8 Home P27 # 3 $ 4 & 7 * 8 ( 9 End Page Down Kor_R Kor_L P10 P11 P00 P01 P02 P03 P04 P05 P06 P07 . Del 0 Ins Space * (Num) / (Num) Num Lock (Num) Page Up Insert Delete K14 P Scroll Lock Pause Back Space { [ F11 " ' L-Alt Enter | \(K42) F12 ? / R-Alt F9 _ - F10 ) 0 Print Screen P12 P13 P14 P15 R-Ctrl L-Ctrl F5 L-WIN P16 Kor_L Q W TAB R-Win A S Esc K45 Z X K131 K132 ~ ` F1 Kor_R ! 1 @ 2 P17 P30 P31 Caps Lock Notice: “Return Key” must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work. 22 NT68P81 Application Circuit 2 (Windows 2000 Compatible Keyboard) V CC Vcc 10 µF P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31 P32 GND 0.1 µ F LED0 Scroll Lock LED1 Num Lock LED2 N T68P81 RESET Caps Lock 4.7K O OSCI *1 *1 : RESETB can be direct connect to VCC if the external reset is not used for module test. OSCO P20 P21 P22 P23 P24 P25 P26 P27 VDP VDM 6Mhz Crystal D+ To USB Cable D1 . 5 KO VCP 4.7 µF P20 E R U I O + (Num) 9 PgUp 8 7 Home Wake Up K14 P Scroll Lock Pause VolumeKor_L Q W Treble- P21 F3 T Y } ] F7 K107 6 5 (Num) 4 L-Shift Back Space { [ BassPower Down L-WIN WWW Forward TAB P22 D F J K L Enter (Num) 3 PgDn 2 1 End P23 F4 G H F6 Bass+ P24 C V M < , > . Scan Next * (Num) / (Num) Num Lock P25 K133 B N K56 APP P26 F2 % 5 ^ 6 + = F8 Home P27 # 3 $ 4 & 7 * 8 ( 9 End Page Down Sleep Power Down Volume+ P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 . Del 0 Ins Space Scan (Num) Page Up Insert Delete R-Shift Previous Stop | \ (K29) : ; 000 00 Email F11 " ' L-Alt . Sleep Enter | \(K42) Euro Key R-Ctrl Play/ Pause F12 ? / R-Alt Wake Up Mute F9 _ - F10 P12 P13 P14 P15 ) 0 Print Treble+ Screen L-Ctrl Bass Boost F5 WWW Backward WWW WWW Search Home WWW WWW R-Win Stop Refresh A S Esc K45 Z X WWW Favorite P16 P17 P30 P31 P32 Kor_R ~ ` F1 ! 1 @ 2 K131 K132 Caps Lock Media Select My Calculator Computer Notice: “Return Key” must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work. 23 NT68P81 Application Circuit 3 (Mini Keyboard) V CC Vcc 10 µF P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31 P32 GND 0.1 µ F LED0 Scroll Lock LED1 Num Lock LED2 N T68P81 RESET Caps Lock 4.7K O OSCI *1 *1 : RESETB can be direct connect to VCC if the external reset is not used for module test. OSCO P20 P21 P22 P23 P24 P25 P26 P27 VDP VDM 6Mhz Crystal D+ To USB Cable D1 . 5 KO VCP 4.7 µF P20 E R U *4 I *5(Num) O *6 + (Num) 9 PgUp 8 7 Home Wake Up K14 P * -(Num) Scroll Lock *Num Lock P21 F3 *FN_K3 P22 D F J *1 End P23 F4 *FN_K4 P24 C V M *0 Ins < , >. *. Del P25 K133 B N K56 APP P26 F2 *FN_K2 P27 # 3 $ 4 &7 *7 Home *8 *8 (9 *9 PgUp End *FN_K19 Page Down *FN_K20 T Y } ] F7 G H F6 K *FN_K6 *2 L *FN_K7 *3 PgDn Bass+ K107 6 5 (Num) 4 L-Shift Back Space { [ BassPower Down L-WIN WWW Forward TAB % 5 ^ 6 + = F8 *FN_K8 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31 P32 Pause *FN_K14 VolumeKor_L Q W Treble- Caps Lock Media Select Enter Scan Home (Num) *FN_K21 Next *FN_K22 *FN_K16 . Page Up 3 * Del PgDn (Num) (Num) *FN_K17 / 2 0 Insert Ins (Num) *FN_K24 *FN_K15 Delete 1 Num Space End Lock *FN_K23 *FN_K18 Scan Play/ R-Shift Previous Stop Mute Pause F12 F9 | F11 Enter *FN_K12 *FN_K9 \ (K29) *FN_K11 _ :; | ?/ " \(K42) * /(Num) * +(Num) ' Euro 000 L-Alt R-Alt Treble+ Key . Wake Sleep 00 R-Ctrl L-Ctrl Up WWW WWW Bass Email Search Home Boost WWW WWW WWW FN R-Win Stop Refresh Favorite ~ Z Esc K131 A ` F1 K132 *FN_K1 S K45 X My Calculator Computer Sleep Power Down Volume+ F10 *FN_K10 )0 * *(Num) Print Screen *FN_K13 F5 *FN_K5 WWW Backward Kor_R ! 1 @ 2 Notice: “Return Key” must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work. *: For FN key model usage 24 NT68P81 FN Key Model Usage for Keypad FN+Scroll Lock FN+& FN+U FN+J FN+M 7 Num Lock 7 Home 4← 1 End 0 Ins FN+* FN+I FN+K 8 8↑ 5(Num) 2↓ FN + ( FN+O FN+L FN+> . 9 9 PgUp 6→ 3 PgDn . Del FN+) FN+P FN+: FN+? ; / 0 *(Num) -(Num) +(Num) /(Num) FN Key Model Usage for Consumer Keys FN_K1 FN_K3 FN_K5 FN_K7 FN_K9 FN_K11 FN_K13 FN_K15 FN_K17 FN_K19 FN_K21 FN_K23 FN+F1 FN+F3 FN+F5 FN+F7 FN+F9 FN+F11 FN+Print Screen FN+Insert FN+Page Up FN+End FN+ ↑ FN+ ↓ WWW Backward WWW Stop WWW Search WWW Home My Computer Media Select Bass Boost Volume+ Treble+ BassStop Play/Pause FN_K2 FN_K4 FN_K6 FN_K8 FN_K10 FN_K12 FN_K14 FN_K16 FN_K18 FN_K20 FN_K22 FN_K24 FN+F2 FN+F4 FN+F6 FN+F8 FN+F10 FN+F12 FN+Pause FN+Home FN+Delete FN+Page Down FN+ ← FN+ → WWW Forward WWW Refresh WWW Favorite Email Calculator Mute Sleep Bass+ VolumeTrebleScan Previous Track Scan Next Track 25 NT68P81 Bonding Diagram P15 25 26 27 28 29 30 31 10 32 9 33 8 34 7 35 36 37 P14 24 P13 23 P12 22 P11 21 P10 20 P07 19 P06 18 P05 17 16 P04 P03 P02 P01 P00 Reset B P34 P33 P32 P31 P30 5470 µ m P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 LED0 LED1 15 NT68P81 14 13 12 (0,0) 11 6 1 38 39 40 41 42 2 3 4 5 VCC VCC OSCO OSCI GND GND VCP VDP VDM LED2 3400 µ m Substrate connect to VCC Unit: µm Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Designation GND GND VCP VDP VDM P30 P31 P32 P33 P34 RESET P00 P01 P02 P03 P04 P05 P06 P07 P10 X 264.50 424.50 734.95 1069.35 1368.85 1443.05 1443.05 1443.05 1443.05 1443.05 1443.05 1443.05 1443.05 1443.05 1443.05 1443.05 1463.90 1173.90 883.90 593.90 Y -2460.05 -2481.00 -2470.00 -2466.00 -2466.00 -2069.05 -1768.65 -1468.25 -1167.85 -867.45 -560.45 -235.35 65.05 365.45 659.85 1007.20 2545.00 2545.00 2545.00 2545.00 26 21 Pad No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P11 Designation P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 LED0 LED1 LED2 VCC VCC 303.90 X -308.10 -598.10 -888.10 -1178.10 -1478.00 -1478.00 -1478.00 -1478.00 -1478.00 -1478.00 -1478.00 -1478.00 -1478.00 -1478.00 -1478.00 -1478.00 -1112.85 -812.45 -626.85 2545.00 Y 2545.00 2545.00 2545.00 2545.00 1012.50 670.80 370.40 70.00 -230.40 -530.80 -831.20 -1131.60 -1432.00 -1732.40 -2037.15 -2337.55 -2481.00 -2470.55 -2470.55 NT68P81 41 OSCO -326.45 -2481.00 42 OSCI -7.75 -2481.00 27 NT68P81 Ordering Information Part No. NT68P81H NT68P81 Packages CHIP FORM 40L DIP Standard code functional descriptions Code Number NT68P81-D01012 Name Simple Keyboard with PS/2 Mouse Windows 2000 Compatible Keyboard Reference application circuit Application circuit 1 Functional Description 1. PS/2 mouse port 2. '000' and '00' keys Application circuit 2 1. ACPI keys 2. '000', '00' and Euro keys 3. Consumer keys (Windows 2000) NT68P81-D01014 Mini Keyboard Application circuit 3 1. ACPI keys 2. ‘ 000’ ‘ and Euro keys , 00’ 3. Consumer keys (Windows 2000) 4. FN key and 40 Translated keys NT68P81-D01013 28 NT68P81 Package Information P-DIP 40L Outline Dimensions unit: inches/mm D 40 21 E1 1 S 20 E C A2 A A1 Base Plane Seating Plane B B1 e1 a eA L Symbol A A1 A2 B B1 C D E E1 e1 L α eA S Dimensions in inches Dimensions in mm 0.210 Max. 5.33 Max. 0.010 Min. 0.25 Min. 0.155±0.010 3.94±0.25 0.018 +0.004 0.46 +0.10 -0.002 -0.05 0.050 +0.004 1.27 +0.10 -0.002 -0.05 0.010 +0.004 0.25 +0.10 -0.002 -0.05 2.055 Typ. (2.075 Max.) 52.20 Typ. (52.71 Max.) 0.600±0.010 15.24±0.25 0.550 Typ. (0.562 Max.) 13.97 Typ. (14.27 Max.) 0.100±0.010 2.54±0.25 0.130±0.010 3.30±0.25 0°~ 15° 0°~ 15° 0.655±0.035 0.093 Max. 16.64±0.89 2.36 Max. Note: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash. 29 NT68P81 Product Spec. Change Notice NT68P81 Specification Revision History Version 2.1 Content FN Key Model Usage for Consumer Keys modified - FN_K22 and FN_K24 (Page 24) Volume Knob Application deleted (Page 18) PS/2 Mouse Application added (Page 18 and 19) Application circuit 2 and 3 modified (Page 22 and 23) FN key usage added (Page 24) Standard code functional descriptions modified (Page 26) Application circuits modified (Page 20, 21 and 22) Standard code functional description added (Page 24) Original Data Oct. 2002 2.0 Sep. 2002 1.3 July 2002 1.0 Nov. 1998 30