NT7701

NT7701 160 Output LCD Segment/Common Driver Features (Segment mode) ! Shift Clock frequency : 14 MHz (Max.) (VDD = 5V ± 10%) 8 MHz (Max.) (VDD = 2.5V - 4.5V) ! Adopts a data bus system ! 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin ! Automatic transfer function with an enable signal ! Automatic counting function when in the chip select mode, causes the internal clock to be stopped by automatically counting 160 bits of input data (Common mode) ! Shift clock frequency: 4.0MHz (Max.) ! Built-in 160-bits bidirectional shift register (divisible into 80-bits x 2) ! Available in a single mode (160-bits shift register) or in a dual mode (80-bits shift register x 2) 1. Y1 → Y160 Single mode 2. Y160 → Y1 Single mode 3. Y1 → Y80, Y81 → Y160 Dual mode 4. Y160 → Y81, Y80 → Y1 Dual mode The above 4 shift directions are pin-selectable (Both segment mode and common mode) ! Supply voltage for LCD drive: 15.0 to 30.0V ! Number of LCD driver outputs: 160 ! Low output impedance ! Low power consumption ! Supply voltage for the logic system: +2.5 to +5.5V ! COMS process ! Package : 190pin TCP (Tape Carrier Package) ! Not designed or rated as radiation hardened General Description The NT7701 is a 160-bit output segment/common driver LSI suitable for driving the large scale dot matrix LCD panels used by PDA's, personal computers and work stations for example. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The NT7701 is good as both a segment driver and a common driver, and a low power consuming, high-precision LCD panel display can be assembled using the NT7701. In the segment mode, the data input is selected 4bit parallel input mode or as 8bit parallel input mode by a mode (MD) pin. In common mode, the data input/output pins are bi-directional and the four data shift directions are pin-selectable. Pin Configuration D U M M Y D U M M Y Y 1 6 0 Y 1 5 9 Y 1 5 8 Y 1 5 7 Y 1 5 6 Y 1 5 5 Y 8 3 Y 8 2 Y 8 1 Y 8 0 Y 7 9 Y 7 8 Y 6 Y 5 Y 4 Y 3 Y 2 DD UU MM YMM 1YY 190 189 188 187 186 185 113 112 111 110 109 108 36 35 34 33 32 31 NT7701 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DVVVVVLVSEDDDDDDDDXDLEFMTTVVVVVD U0 1 45S / D / I 01 2 34 5 67C I P I RDEES5 4 1OU ML23LSRDCO KS O SSSR32RM M M P LL 2 1 TT RR Y Y O 12 F F 1 V2.0 NT7701 Pad Configuration 199 200 54 53 NT7701 216 1 36 37 Block Diagram V0R V12R V43R V5R Y1 Y2 Y159 Y160 FR Level Shifter DISPOFF V5L 160 Bits 4 Level Driver /160 V43L V12L 160 Bits Level Shifter EIO1 EIO2 /16 V0L V5R Active Control /160 160 Bits Line Latch/Shift Register /16 /16 /16 /16 /16 /16 /16 /16 /16 LP XCK 8Bits x 2 Data Latch Control Logic Data Latch Control L/R MD S/C /8 SP Conversion & Data Control (4 to 8 or 8 to 8) DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 VDD VSS VSS 2 NT7701 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 - 190 Designation V0L V12L V43L V5L VSS L/R VDD S/C EIO2 D0 - D6 D7 XCK DISPOFF LP EIO1 FR MD TEST1 TEST2 VSS V5R V43R V12R V0R Y1 - Y160 I/O P P P P P I P I I/O I I I I I I/O I I I I P P P P P O Description Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Ground (0V), these two pads must be connected to each other Display data shift direction selection Power supply for the logic system (+2.5 to +5.5V) Segment mode / common mode selection Input / output for chip select or data of shift register Display data input for segment mode Display data input for Segment mode / Dual mode data input Display data shift clock input for segment mode Control input for deselect output level Latch pulse input/shift clock input for the shift register Input / output for chip select or data of the shift register AC-converting signal input for LCD driver waveform Mode selection input Test pin, no connection for user Test pin, no connection for user Ground (0V), these two pads must be connected to each other Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver LCD driver output 3 NT7701 Pad Description Pad No. 1, 2 3, 4 5, 6 7, 8 9,10 - 21, 22 23, 24 25, 26 27, 28 29, 30 31, 32 33, 34 35, 36 37, 38, 39, 40 41, 42 43, 44 45, 46 47 - 206 207, 208 209, 210 211, 212 213, 214 215, 216 Designation L/R VDD S/C EIO2 D0 - D6 D7 XCK DISPOFF LP EIO1 FR MD VSS V5R V43R V12R V0R Y1 - Y160 V0L V12L V43L V5L VSS I/O I P I I/O I I I I I I/O I I P P P P P O P P P P P Description Display data shift direction selection Power supply for the logic system (+2.5 to + 5.5V) Segment mode/common mode selection Input/output for chip select or data of shift register Display data input for segment mode Display data input for Segment mode / Dual mode data input Display data shift clock input for segment mode Control input for deselect output level Latch pulse input / shift clock input for the shift register Input/output for chip select or data of the shift register AC-converting signal input for LCD driver waveform Mode selection input Ground (0V), these two pads must be connected to each other Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver LCD driver output Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Ground (0V), these two pads must be connected to each other 4 NT7701 Input / Output Circuits VDD I Input Signal VSS Input Circuit (1) Applicable Pins L/R, S/C, D0 - D6, DISPOFF , LP, FR, MD VDD I Control Signal Input Signal Applicable Pins D7, XCK VSS VSS Input Circuit (2) 5 NT7701 VDD Input Signal Control Signal VSS VDD VSS Output Signal I/O Control Signal VSS Input / Output Circuit Applicable Pins EIO1, EIO2 V0 V12 Control Signal 1 O Control Signal 3 Control Signal 2 Control Signal 4 Applicable Pins Y1 to Y160 V43 VSS V5 LCD Driver Output circuit 6 NT7701 Pad Description Segment mode Symbol VDD VSS VOR, VOL V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects to +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias # Normally, the bias voltage used is set by a resistor divider # Ensure that the voltages are set such that VSS ≤ V5 < V43 < V12 < V0 # To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y160, externally connect ViR and ViL (I = 0, 12, 43) Input pin for display data # In 4-bit parallel input mode, input data into the 4 pins D0 - D3. Connect D4 - D7 to VSS or VDD # In 8-bit parallel input mode, input data into the 8 pins D0 - D7 Clock input pin for taking display data # Data is read on the falling edge of the clock pulse Latch pulse input pin for display data # Data is latched on the falling edge of the clock pulse Direction selection pin for reading display data # When set to VSS level "L", data is read sequentially from Y160 to Y1 # When set to VDD level "H", data is read sequentially from Y1 to Y160 Control input pin for output deselect level # The input signal is level-shifted from logic voltage level to LCD driver voltage level, and controls LCD driver circuit # When set to VSS level “L”, the LCD driver output pins (Y1 - Yl60) are set to level V5 DISPOFF # While DISPOFF is set to “L”, the contents of the line latch are reset, but the display data in the data latch are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled, the driver outputs deselect level (V12 or V43), then outputs the contents of the date latch onto the next falling edge of the LP. That time, if DISPOFF removal time can not keep regulation what is shown AC characteristics, can not output the reading data correctly AC signal input for LCD driving waveform # The input signal is level-shifted from the logic voltage level to the driver voltage level, and controls LCD driver circuit # Normally inputs a frame inversion signal The LCD driver output pin’s output voltage level can be set to the line latch output signal and the FR signal Mode selection pin # When set to VSS level “L”, 4-bit parallel input mode is set # When set to VDD level “H", 8-bit parallel input mode is set D0 - D7 XCK LP L/R FR MD 7 NT7701 Segment mode continued Symbol S/C Function Segment mode/common mode selection pin # When set to VDD level "H", segment mode is set. # When set to VSS level "L", common mode is set. Input/output pin for chip selection # When L/R input is at VSS level “L”, EIO1 is set for output, and EIO2 is set for input. # When L/R input is at VDD level “H”, EIO1 is set for input, and EIO2 is set for output. # During output, it is set to “H” while LP* XCK is “H” and after 160-bits of data have been read, it is set to “L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H” # During input, after the LP signal is input, the chip is selected while EI is set to “L”. After 160-bits of data have been read, the chip is deselected LCD driver output pins These corresponding directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output EIO1, EIO2 Y1 - Y160 Common mode Symbol VDD VSS V0R, V0L V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects to +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias. # Normally, the bias voltage used is set by a resistor divider # Ensure that the voltages are set such that VSS ≤ V5