NT7703

NT7703 160 Output LCD Segment/Common Driver Features (Segment mode) ! Shift Clock frequency: 14 MHz (Max.) (VDD = 5V ± 10%) 8 MHz (Max.) (VDD = 2.5V - 4.5V) ! Adopts a data bus system ! 4-bit / 8-bit parallel input modes are selectable with a mode (MD) pin ! Automatic transfer function with an enable signal ! Automatic counting function when in “chip select” mode, which causes the internal clock to be stopped by automatically counting 160 bits of input data (Common mode) ! Shift clock frequency: 4.0MHz (Max.) ! Built-in 160-bits bidirectional shift register (divisible into 80-bits x 2) ! Available in a single mode (160-bits shift register) or in a dual mode (80-bits shift register x 2) 1. Y1 → Y160 Single mode 2. Y160 → Y1 Single mode 3. Y1 → Y80, Y81 → Y160 Dual mode 4. Y160 → Y81, Y80 → Y1 Dual mode The above 4 shift directions are pin-selectable (Both segment mode and common mode) ! Supply voltage for LCD drive: 15.0 to 30.0V ! Number of LCD driver outputs: 160 ! Low output impedance ! Low power consumption ! Supply voltage for the logic system: +2.5 to +5.5V ! COMS process ! Package: Gold bump die / 186 Pin TCP (Tape Carrier Package) ! Not designed or rated as radiation hardened General Description The NT7703 is a 160-bit output segment/common driver LSI suitable for driving the large scale dot matrix LCD panels used by PDA's, personal computers and work stations for example. Through the use of COG technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The NT7703 is good as both a segment driver and a common driver, and a low power consuming, highprecision LCD panel display can be assembled using the NT7703. In the segment mode, the data input is selected as 4bit parallel input mode or as 8bit parallel input mode by a mode (MD) pin. In common mode, the data input/output pins are bi-directional and the four data shift directions are pinselectable. Pin Configuration D U M M Y D U M M Y D U M M Y D U M M Y Y 1 6 0 Y 1 5 9 Y 1 5 8 Y 1 5 7 Y 1 5 6 Y 1 5 5 Y 8 3 Y 8 2 Y 8 1 Y 8 0 Y 7 9 Y 7 8 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 D U M M Y D U M M Y D U M M Y D U M M Y 186 185 184 183 182 181 109 108 107 106 105 104 32 31 30 29 28 27 NT7703 1 V 0 L 2 V 1 2 L 3 V 4 3 L 4 V S S / V 5 L 5 L / R 6 V D D 7 S / C 8 E I O 2 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 X C K D I S P O F F L P E I O 1 F R M D V S S / V 5 R V 4 3 R V 1 2 R V 0 R 1 V1.0 NT7703 Pad Configuration 272 x x 145 x x 273 144 NT7703 288 x 1 ALK_L Dummy Pad x ALK_R 129 x 128 Block Diagram V0R V12R V43R V5R Y1 Y2 Y159 Y160 FR Level Shifter DISPOFF V5L 160 Bits 4 Level Driver /160 V43L V12L 160 Bits Level Shifter EIO1 V5R Active Control EIO2 /16 /16 /16 /16 /16 /16 /16 /16 /16 /16 /160 V0L 160 Bits Line Latch/Shift Register LP XCK 8Bits x 2 Data Latch Control Logic Data Latch Control L/R MD S/C /8 SP Conversion & Data Control (4 to 8 or 8 to 8) DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 VDD VSS VSS 2 NT7703 Pad Description Pad No. 1-7 8 - 12 13 - 17 18 - 22 23 - 39 40 - 41 42 - 57 58 - 59 60 - 61 62, 63 - 74, 75 76 - 77 78 - 79 80 - 81 82 - 83 84 - 85 86 - 87 88 - 89 90 - 106 107 - 111 112 - 116 117 - 121 122 - 128 129 - 288 Designation V0L V12L V43L V5L VSS L/R VDD S/C EIO2 D0 - D6 D7 XCK DISPOFF LP EIO1 FR MD VSS V5R V43R V12R V0R Y1 - Y160 I/O P P P P P I P I I/O I I I I I I/O I I P P P P P O Description Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Ground (0V), these two pads must be connected to each other Display data shift direction selection Power supply for the logic system (+2.5 to + 5.5V) Segment mode / common mode selection Input / output for chip select or data of shift register Display data input for segment mode Display data input for Segment mode / Dual mode data input Display data shift clock input for segment mode Control input for deselect output level Latch pulse input / shift clock input for the shift register Input / output for chip select or data of the shift register AC-converting signal input for LCD driver waveform Mode selection input Ground (0V), these two pads must be connected to each other Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver LCD driver output 3 NT7703 Input / Output Circuits VDD I Input Signal Applicable Pins L/R, S/C, D0 - D6, DISPOFF , LP, FR, MD VSS Input Circuit (1) VDD I Control Signal Input Signal Applicable Pins D7, XCK VSS VSS Input Circuit (2) 4 NT7703 VDD Input Signal Control Signal VSS VDD VSS Output Signal I/O Control Signal VSS Applicable Pins EIO1, EIO2 Input / Output Circuit V0 V12 Control Signal 1 O Control Signal 3 Control Signal 2 Control Signal 4 Applicable Pins Y1 to Y160 V43 VSS V5 LCD Driver Output circuit 5 NT7703 Pad Description Segment mode Symbol VDD VSS VOR, VOL V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects from +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias " Normally, the bias voltage used is set by a resistor divider " Ensure that the voltages are set such that VSS ≤ V5 < V43 < V12 < V0 " To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y160, externally connect ViR and ViL (I = 0, 12, 43) Input pin for display data " In 4-bit parallel input mode, input data into the 4 pins D0 - D3. Connect D4 - D7 to VSS or VDD " In 8-bit parallel input mode, input data into the 8 pins D0 - D7 Clock input pin for taking display data " Data is read on the falling edge of the clock pulse Latch pulse input pin for display data " Data is latched on the falling edge of the clock pulse Direction selection pin for reading display data " When set to VSS level "L", data is read sequentially from Y160 to Y1 " When set to VDD level "H", data is read sequentially from Y1 to Y160 Control input pin for output deselect level " The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the LCD driver circuit " When set to VSS level “L”, the LCD driver output pins (Y1 - Yl60) are set to level V5 " When DISPOFF is set to “L”, the contents of the line latch are reset, but the display data in the data latch DISPOFF are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled, the driver outputs the deselect level (V12 or V43), then outputs the contents of the date latch onto the next falling edge of the LP At that time, if the DISPOFF removal time can not keep in regulation with what is shown on the AC characteristics, then it can not output the reading data correctly AC signal input for LCD driving waveform " The input signal is level-shifted from the logic voltage level to the driver voltage level, and controls LCD driver circuit " It normally inputs a frame inversion signal The LCD driver output pin’s output voltage level can be set to the line latch output signal and the FR signal Mode selection pin " When set to VSS level “L”, 4-bit parallel input mode is set " When set to VDD level “H", 8-bit parallel input mode is set D0 - D7 XCK LP L/R FR MD 6 NT7703 Segment mode continued Symbol S/C Function Segment mode/common mode selection pin " When set to VDD level "H", segment mode is set " When set to VSS level "L", common mode is set Input/output pin for chip selection " When L/R input is at VSS level “L”, EIO1 is set for output, and EIO2 is set for input " When L/R input is at VDD level “H”, EIO1 is set for input, and EIO2 is set for output " During output, it is set to “H” when LP* XCK is “H” and then after 160-bits of data have been read, it is set to “L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H” " During input, after the LP signal is input, the chip is selected while EI is set to “L”. After 160-bits of data have been read, the chip is deselected LCD driver output pins These correspond directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output EIO1, EIO2 Y1 - Y160 Common mode Symbol VDD VSS V0R, V0L V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects from +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias. " Normally, the bias voltage used is set by a resistor divider " Ensure that the voltages are set such that VSS ≤ V5