OV7620

Preliminary Company Confidential OV7620 Product Specifications -Rev. 1.3 (5/13/00) OV7620 SINGLE-CHIP CMOS VGA COLOR DIGITAL CAMERA Features • 326,688 pixels, 1/3” lens, VGA / QVGA format • Read out - progressive / Interlace • Data format - YCrCb 4:2:2, GRB 4:2:2, RGB Raw Data • 8/16 bit video data: CCIR601, CCIR656, ZV port • Video Timing - 525 line, 30 fps • Wide dynamic range, anti-blooming, zero smearing • SCCB (Serial Camera Control Bus) interface • Electronic exposure / Gain / white balance control • Image enhancement - brightness, contrast, gamma, saturation, sharpness, window, etc. • Internal / external synchronization scheme • Frame exposure / line exposure option • 5 Volt operation, low power dissipation. General Description OV7620 is a highly integrated high resolution (640x480) Interlaced / Progressive Scan CMOS digital color / black&white video camera chip. The digital video port supports 60Hz YCrCb 4:2:2 16Bit / 8 Bit format, ZV Port output format, RGB raw data 16Bit/8Bit output format and CCIR601/CCIR656 format. The builtin SCCB interface provides an easy way of controlling the built-in camera functions. • Video Conferencing • Video Phone • Video Mail • Still Image • PC Multimedia AG ND VREQ FREX AGCEN/RAMINT RESET SVDD SGND MID SIO-0 SIO-1 AVDD AG ND Array Elements Pixel Size Image Area Electronic Exposure 42 41 40 39 38 37 36 35 34 33 32 31 CHSYNC/BW Y0/CBAR Y1/PROG Y2/G2X Y3/RAW Y4/CS1 Y5/SHARP Y6/CS2 Y7/CS0 PCLK/OUTX2 DOVDD DOGND 664 x 492 7.6 x 7.6 um 4.86 x 3.64mm 500 : 1 progressive interlace 128 Curve Settings See specifics 2.5 lux @ f1.4 0.5 lux @ f1.4 (3000K) > 48dB 5VDC, ±5% 6*Tclk (2) Ths < Tvs < 2*858*Tclk FIG 1.5 Slave Mode External Sync Timing OV7620 will be stable after 1 frame. (2nd Vsync). 1.11 Frame Exposure Mode OV7620 support frame exposure mode when in Progressive Scan Mode. When the FREX pin is used as an external master device sets the exposure time. When FREX =1, the whole array is precharged. The exposure time is then determined by the external master device which controls FREX. When FREX=0, the OV7620 begins to output data line by line. While data is output, the OV7620 must be blocked from light by using a mechanical shutter, so that the whole array is exposed at the same time and has the same exposure period. In default line exposure mode, the array precharge and read mode is first charge 1st line, after one line read out, precharge 2nd line, so on. the width of FREX=1 must large the a fixed timing to make sure whole array has been precharged. Frame exposure mode timing is as below: 23 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. Tset FREX Tin HSYNC Prechage begin at rising edge of HSYNC ARRAY PRECHARGE Array Exposure Period Tex Array Precharge period Tpr DATA OUTPUT Invalid Data Head of Valid data Thd (8 line) VSYNC Next Frame 1 Frame (484 line) Valid Data Black Data Mechanical shutter closed Ths HREF FIG 1.6 Frame Exposure Timing Note: Tpr = 492 * 4 * Pclk, Pclk is internal pixel clock. For default 27MHz, Tclk=74 ns. If CLK set to divided number, Tclk will increase accordingly. Tex is array exposure time which is decided by external master device. Tin is undetermined due to the use of HSYNC rising edge to synchronize FREX, Tin < Ths When FREX=0, there are 8 lines of data output before valid data output. Thd = 4 * Ths. Valid data is output when HREF=1. Tset = Tin + Tpr + Tex. Tset > Tpr + Tin. Because Tin is uncertain, so exposure time setting resolution is Ths (one line). 24 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) 1.12 SCCB BUS SCCB access is enabled only if pin SBB=0. OV7620 is a slave device that supports 400kbit/s 7bit address data transfer protocol. Within each byte, MSB is always transferred first, read/write control bit is the LSB of the first byte The protocol requires SIO-0 must be stable during the HIGH period of the SIO-1. Each data bit can only change state when is SIO-1 LOW. OV7620 reserves CS(2:0) for the slave ID, which makes eight slave camera combinations. OV7620 SCCB supports multi-byte write and multi-byte read. In a write cycle, the master must supply the subaddress, however, the master does not supply the subaddress in the read cycle, therefore, OV7620 takes the read subaddress from the previous write cycle. In multi-byte write or multi-byte read cycles, the subaddress is auto increment after the first data byte so that continuous locations can be accessed in one bus cycle. Since a multi-byte cycle overwrites its original subaddress, if a read cycle follows immediately to a multi-byte cycle, it is necessary to insert a single byte write cycle that provides a new subaddress. If OV7620 support 400 kBit/s fast SCCB mode, system clock (CLK) must be at least 10 Mhz. OMNIVISION TECHNOLOGIES INC. 25 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) 1.13 SCCB REGISTER SETS OV7620 can be configured, by setting pin CS high or low at reset/power up, to one of eight slave IDs as listed below, the ID can not be altered once the chip is out of reset or power up state. Table 1.10: Slave ID CS WRITE ID (hex) READ ID (hex) OMNIVISION TECHNOLOGIES INC. 000 42 43 001 46 47 010 4a 4b 011 4e 4f 100 52 53 101 56 57 110 5a 5b 111 5e 5f OV7620 support two option: single chip and multiple chip decided by PIN MID. If MID set to LOW (Default value), chip slave ID is 42(for write) and 43(for read). If MID set to HIGH, OV7620 can support 8 slave ID selection. Default MID is LOW by internal setting. In write cycle, the second byte in SCCB bus is the subaddress for selecting the individual on chip registers, the third byte is the data associated with this register. Writing to unimplemented subaddress and reserved subaddress is ignored. In read cycle, the second byte is the data associated with the previous stored subaddress. reading of unimplemented subaddress returns unknown. Registers [00] ~ [02] contains image effect parameters that also can be modified by internal controls in auto adjust mode. This provides a simple way to read out those parameters computed by chip internal controls. To do this, first set the chip in auto adjust mode (Register 13 bit 0=1, register 12 bit 2 = 1, register 12 bit 5=1), wait for the image is stable, the register [00],[01] and [02] will be updated by internal control circuit. Then returns it to manual adjust mode(register 13 bit 0=0), all the registers retain the last adjusted values and can be read or overwritten by external host. When the chip is operated in auto adjust mode(register 13 bit 0=1), register [00] ~ [02] will be update by internal algorithm and if write data to them, there will be no effect on chip parameters. The register data can be read out. The detailed definitions of each register are described below. Register 00 - rw: AGC gain control Bits Default Null AGC6 AGC5 AGC4 AGC3 AGC2 AGC1 AGC0 - - 0 0 0 0 0 0 AGC - gain setting for the entire image channel. The formula is: Gain = (AGC/16+1)*(AGC+1)*(AGC+1); range (1x ~ 7.75x), AGC and AGC control SA2. 26 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) Register 01 - rw: Blue gain control Bits Default BLU7 BLU6 BLU5 BLU4 BLU3 BLU2 BLU1 BLU0 OMNIVISION TECHNOLOGIES INC. 1 0 0 0 0 0 0 0 BLU - white balance value for the blue channel. The formula is: Blue_gain=1+(BLU - [80])/[100]; range (0.5x ~ 1.5x). BLU - Sign bit. If “1”, Blue gain increase; “0” gain decrease. Register 02 - rw: Red gain control Bits Default RED7 RED6 RED5 RED4 RED3 RED2 RED1 RED0 1 0 0 0 0 0 0 0 RED - white balance value for the red channel. The formula is: Red_gain=1+(RED - [80])/[100]; range (0.5x ~ 1.5x). RED - Sign bit. If “1”, Red channel gain increase; “0” gain decrease. Register 03 - rw: Saturation control Bits Default SAT7 SAT6 SAT5 SAT4 SAT3 SAT2 SAT1 SAT0 1 0 -0 0 0 0 0 0 SAT - saturation adjustment for the UV channel based on the default setting; range (-4dB ~ +6dB). If SAT > [80], increase; if SAT < [80], decrease. Register 04 & 05 - w: Reserved Register This register is reserved for internal test use. Write data to this register will be no function. Register 06 - rw: Brightness control Bits Default BRT7 BRT6 BRT5 BRT4 BRT3 BRT2 BRT1 BRT0 1 0 0 0 0 0 0 0 BRT - brightness adjustment for the Y/RGB channel based on the default setting; range (-200mv ~ +200mv). If BRT > [80], brightness increase; If BRT < [80], brightness decrease. This register is auto/manual controllable. If register 2D bit 4=1, this register is controlled by chip automatically, if write value to this register, this value will be updated by internal circuit. Only when register 2D bit 4=0, this register can be set to any value 27 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. Register 07 - rw: Angalog Sharpness control Bits Default SHP7 SHP6 SHP5 SHP4 SHP3 SHP2 SHP1 SHP0 1 1 0 0 0 0 1 1 SHP - Sharpness Threshold. SHP - Sharpness Magnitude. Register [08] ~ [0B] - w: Reserved. These four registers are reserved for internal use. Write data to these registers will not function. Register 0C - rw: White Balance background control -- Blue channel Bits Default Null Null ABLU5 ABLU4 ABLU3 ABLU2 ABLU1 ABLU0 - - 1 0 0 0 0 0 Changes AWB Hue Control ABLU - White Balance background blue color component ratio adjustment. Adjust resolution is 0.625% and total range is (+20% - -20%) This register is used to offset image background blue component ratio. ABLU - Sign bit. If “1”, decrease background blue component ratio; “0” increase blue component ratio. Register 0D - rw: White Balance background control -- Red channel Bits Default Null Null ARED5 ARED4 ARED3 ARED2 ARED1 ARED0 - - 1 0 0 0 0 0 Changes AWB Hue Control ARED - White Balance background red color component ratio adjustment. Adjust resolution is 1.5% and total range is (+20% - -20%) This register is used to offset image background red component ratio. ARED - Sign bit. If “1”, decrease background red component ratio; “0” increase red component ratio. Register 0E ~ 0F- rw: Reserved These two registers are reserved for internal use. Write data to these registers will not function. 28 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) Register 10 - rw: Auto-Exposure-Control Register Bits Interlace Progressive Scan AEC7 AEC6 AEC5 AEC4 AEC3 AEC2 AEC1 AEC0 OMNIVISION TECHNOLOGIES INC. 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AEC - exposure time setting; the formula is Interlaced: TEXPOSURE = TLINE x AEC(7:0); Progressive: TEXPOSURE = TLINE x AEC(7:0)x2; where TLINE = Frame Time / 525 if use 27MHz, TLINE = 63.5 uS Range is: [00] - [7F] for Interlaced; [00] - [FF] for Progressive Scan. * This register setting is only effective when operated in manual adjust mode (register 13 bit 0=0). Nevertheless, this register is always accessible through the SCCB bus. If register 13 bit 0=1, this register will be updated by internal circuit according AEC algorithm, and if write special value to this register will be useless. The register value can be read out at any time and latest AEC value will be return. If register 13 bit 0=0, or register 29 bit 7=1, the register will hold last value unchanged (either input from SCCB or AEC algorithm result). * It generally takes no more than two fields for the image to reach the intended exposure after changing the setting. Register 11 - rw: Clock rate control Bits Default SYN7 SYN6 CLK5 CLK4 CLK3 CLK2 CLK1 CLK0 0 0 0 0 0 0 0 0 CLK - system clock prescaler; this register defines the chip pixel clock rate, clock rate is defined by following fulmar: (16 Bit mode) PCLK = (CLK_input / (( CLK + 1) * 2)) (8 Bit mode) PCLK = (CLK_input / ( CLK + 1)) SYN - Three sync output polarity selection: SYN7 = 0, SYN6 = 0: HSYNC negative, CHSYNC negative, VSYNC positive edge; SYN7 = 0, SYN6 = 1:.HSYNC negative, CHSYNC negative, VSYNC negative; SYN7 = 1, SYN6 = 0: HSYNC positive, CHSYNC negative, VSYNC positive. SYN7 = 1, SYN6 = 1: HSYNC negative, CHSYNC positive, VSYNC positive. * The effect of the change is immediate, however, it generally takes about two fields for the image to reach the stable state 29 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) . OMNIVISION TECHNOLOGIES INC. Register 12 - rw: Common control A Bits Default COMA7 COMA6 COMA5 COMA4 COMA3 COMA2 COMA1 COMA0 0 0 1 0 0 1 0 0 COMA7 - “1” initiates the chip soft reset, the reset takes place after the acknowledge bit is issued, the effect is the same as power up the chip, the chip is initialized to a default state, all registers including SCCB’s contents are set to default, this bit is self cleared after the reset. COMA6 - “1” selects mirror image COMA5 - “1” enables AGC. “0” - stop AGC and set register [00] to default value. Only effective in auto adjust mode. COMA4 - “1” select 8 Bit Digital output format is Y U Y V Y U Y V ... COMA3 - “1” selects raw data signal as video data output, “0” selects YCrCb as video data output. The selection applies to both analog video and digital video. COMA2 - “1” enable auto white balance, “0” AWB stop and AWB register [01] and [02] value is held at last updated value. Can used as one-shot AWB mode. Valid only in auto mode. COMA1 - “1” selects Color Bar Test pattern output. COMA0 - “1” select precise A/D Black Level Compensation (BLC) line method. “0” use standard black level compensation to do A/D BLC field method which is more stable but less precise. Register 13 - rw: Common control B Bits Default COMB7 COMB6 COMB5 COMB4 COMB3 COMB2 COMB1 COMB0 - - 0 0 0 0 0 1 COMB7 - Reserved. COMB6 - Reserved. COMB5 - “1” selects 8 bit data format, Y/CrCb and RGB video data is multiplexed to the eight bit Y bus, tristate UV bus; “0” selects 16 bit format, data go to both Y bus and UV bus. COMB4 - “0” enables digital output in CCIR601 format. “1” enables CCIR656 format. COMB3 - “0” selects horizontal sync for output to pin CHSYNC, “1” selects composite sync for output. COMB2 - “1” tri-states bus Y and UV, “0” enables both buses. COMB1 - “1” initiates the single frame transfer, for this function to work, field drop mode (FD in register [16]) must set to “OFF”. See figure below. After this bit is set, for Interlaced mode, HREF is only asserted for consecutive two fields beginning at Odd field. This bit is cleared automatically at the end of this frame. For Progressive Scan mode, HREF is only asserted for one frame. Clearing this bit in the middle of active frame has no effect to the assertion of current HREF. COMB0 - “1” enables auto adjust mode, in this mode, internal exposure circuitry overwrites those parameters in registers [00]~[02], the chip adjusts the image based on a preset algorithm. “0” manual adjust mode. 30 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) . OMNIVISION TECHNOLOGIES INC. FODD VSYNC 1 FRAME FD SCCB BIT CLEAR COMB1 SCCB BIT SET END OF FRAME BIT CLEAR SCCB BIT SET SCCB BIT CLEAR HREF FIG 1.7 Single Frame Transfer Example (Interlaced Mode) VSYNC 1 FRAME FD SCCB BIT CLEAR SCCB BIT CLEAR COMB1 SCCB BIT SET END OF FRAME BIT CLEAR SCCB BIT SET SCCB BIT CLEAR HREF FIG 1.8 Single Frame Transfer Example (Progressive Scan Mode) 31 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. Register 14- rw: Common control C Bits Default COMC7 COMC6 COMC5 COMC4 COMC3 COMC2 COMC1 COMC0 0 - 0 0 0 1 - - COMC7 - AWB activation threshold selection: 1- high; 0-low. COMC6 - Reserved. COMC5 - QVGA digital output format selection. 1 - 320x240; 0 - 640x480. COMC4 - Field/Frame vertical sync output in VSYNC port selection: 1 - frame sync, only inserted in ODD field vertical sync; 0 - field vertical sync, effect in Interlaced mode COMC3 - HREF polarity selection: 0 - HREF positive effective, 1 - HREF negative. COMC2 - RGB gamma selection: 1 - Gamma on, value defined by register [62] value; 0 - gamma is 1 (linear). COMC1 - Reserved. COMC0 - Reserved. Register 15- rw: Common control D Bits Default COMD7 COMD6 COMD5 COMD4 COMD3 COMD2 COMD1 COMD0 - 0 - - - - - 1 COMD7 - Reserved. COMD6 - PCLK polarity selection. “0” OV7620 output data at PCLK falling edge and data bus will be stable at PCLK rising edge; “1” rising edge output data and stable at PCLK falling edge. When OV7620 work as CCIR656 format, COMB4=1, this bit is disable and should use PCLK rising edge latch data bus. COMD - Reserved. COMD0 - U V digital output sequence exchange control. 0 - V U V U ... for 16Bit, V Y U Y ... for 8 Bit; 1- U V U V ... for 16Bit and U Y V Y ... for 8 Bit. Register 16 - rw: Frame Drop Bits Default FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 0 0 0 0 0 0 1 1 FD- Frame drop selection, it operates in ODD and EVEN mode as defined by FD, it is ignored in OFF & FRAME mode. Its purpose is to divide the video signal into programmed number of time slots in unit of field/frame, and to allow HREF to be active only one field/frame during the period. This function does not affect the video data or pixel rate. 000000 - 000001: disable digital data output, only output black reference level. 000010 - 111111: Output 1 of (2 ~ 63) frame. If set register 33 bit 1= 1, that means only drop 1 frame from (2 ~ 63) frame. 32 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. 1 field FODD EVEN MODE HREF EVEN MODE FD=000010 FD=10 slot 1 slot 2 slot 3 slot 4 slot 1 slot 2 slot 3 slot 4 ODD MODE HREF ODD MODE FD=000001 FD=01 slot 2 slot 1 slot 2 slot 1 slot 2 slot 1 slot 2 slot 1 FIG 1.9 Field Division Examples (Interlaced Mode) Interlaced: FD- field mode selection. Each frame consists of two fields: Odd & Even, these bits defines the assertion of HREF in relation to the two fields. 00 - OFF mode; HREF is not asserted in both fields, one exception is the single frame transfer operation (see the description for the register [13]) 01 - ODD mode; HREF is asserted in odd field only. 10 - EVEN mode; HREF is asserted in even field only. 11 - FRAME mode; HREF is asserted in both odd field and even field. FD useless (default). 1 frame VSYNC SLOT MODE HREF FD=000001 FD=01 slot 2 slot 1 slot 2 slot 1 slot 2 slot 1 slot 2 slot 1 FIG 1.10 Frame Division Examples (Progressive Scan Mode) Progressive Scan: FD - frame mode selection. 00 - OFF mode; HREF is not asserted in both fields, one exception is the single frame transfer operation (see the description for the register [13]) 01,10 - SLOT mode; HREF is asserted in frame according FD. 11 - FRAME mode; HREF is asserted in every frame. FD useless 33 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) Register 17 - rw: Horizontal Window start Bits Default HS7 HS6 HS5 HS4 HS3 HS2 HS1 HS0 OMNIVISION TECHNOLOGIES INC. 0 0 1 0 1 1 1 1 HS - selects the starting point of HREF window, each LSB represents four pixels for Interlaced/Progressive full resolution mode, two pixels for QVGA resolution mode, this value is set based on an internal column counter, the default value corresponds to 640 horizontal window. Maximum window size is 664. see window description below. HS programmable range is [2C]- [D2], and should less than HE. HS should be programmable to value larger than or equal to [2C]. Value larger than [D2] is invalid. See Figure 1.14. Register 18 - rw: Horizontal Window end Bits Default HE7 HE6 HE5 HE4 HE3 HE2 HE1 HE0 1 1 0 0 1 1 1 1 HE - selects the ending point of HREF window, each LSB represents four pixels for full resolution and two pixels for QVGA resolution, this value is set based on an internal column counter, the default value corresponds to the last available pixel. The HE programmable range is [2D] - [D2]. HE should be larger than HS and less than or equal to [D2]. Value larger than [D2] is invalid. See Figure 1.14. Register 19- rw: Vertical Window start Bits Default VS7 VS6 VS5 VS4 VS3 VS2 VS1 VS0 0 0 0 0 0 1 1 0 VS - selects the starting row of vertical window, in full resolution mode, each LSB represents 1scan line in one field for Interlaced Mode, 2 scan line in one frame for Progressive Scan Mode. In QVGA resolution (set by register 14 bit 5), each LSB represents 1 scan line in one field for Interlaced Mode, 1scan line in one frame for Progressive Scan Mode. See Figure 1.14. Min. is [05], max. is [F6] and should less than VE. Register 1A- rw: Vertical Window end Bits Default VE7 VE6 VE5 VE4 VE3 VE2 VE1 VE0 1 1 1 1 0 1 0 1 VE- selects the ending row of vertical window, in full resolution mode, each LSB represents 1scan line in one field for Interlaced Mode, 2 scan line in one frame for Progressive Scan Mode. In QVGA resolution, each LSB represents 1 scan line in one field for Interlaced Mode, 1scan line in one frame for Progressive Scan Mode. See Figure 1.14. Min. is [05], max. is [F6] and should larger than VS. 34 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. HREF HS VS HE Active Window VE FULL image boundary FIG 1.11 Window Sizing As shown above, HS defines the starting pixel within a scan line, HE defines the ending pixel within a scan line. VS defines the starting row within a field, VE defines the ending row within a field. VS/VE automatically defines the window height of a image frame. The rectangular window defined by HS/HE/VS/VE is the active image window. Only pixels insides this window is valid, along with the HREF timing signals, black level substitutes the pixel data when outside the active window. Identical value for HS/HE or VS/VE is not permitted since it causes undefined window size. If end point is lower than the starting point, the window begins from the starting point and ends at the far end of the available image boundary. The window size calculate formula is as below: 1. Horizontal size: VGA mode: Horizontal window size = (Register [18] - Register [17])*4. QVGA mode: Horizontal window size = (Register [18] - Register [17])*2. 2. Vertical size: VGA mode: Vertical window size = (Register [1A]- Register [19]+1); QVGA mode: Horizontal window size = (Register [1A] - Register [19]+ 1). 35 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. Register 1B- rw: Pixel shift Bits Default PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 0 0 0 0 0 0 0 0 PS - to provide a way to fine tune the output timing of the pixel data relative to that of HREF, it physically shifts the video data output time early or late in unit of pixel clock as shown in the figure below. This function is different from changing the size of the window as is defined by HS & HE in register [17] and [18]. 36 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. The number of pixels that can only be shifted late. Maximum shift pixel number is 255. define by HS define by HE HREF ACTIVE WINDOW BLACK LEVEL Y - DEFAULT LEFT SIDE PIXEL ADDED RIGHT SIDE PIXEL LOST Y - LATE right shift Full= 664 physical image boundary FIG 1.12 Pixel Shift Examples Register 1C- r: Manufacture ID high byte Bits Default MIDH7 MIDH6 MIDH5 MIDH4 MIDH3 MIDH2 MIDH1 MIDH0 0 1 1 1 1 1 1 1 MIDH - read only, always returns “7F”. Register 1D- r: Manufacture ID low byte Bits Default MIDL7 MIDL6 MIDL5 MIDL4 MIDL3 MIDL2 MIDL1 MIDL0 1 0 1 0 0 0 1 0 37 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) MIDL- read only, always returns “A2” OMNIVISION TECHNOLOGIES INC. Register 1E ~ 1F- rw: Reserved These two registers are reserved for internal use. Write data to these registers will not function. Register 20- rw: Common control E Bits Default COME7 COME6 COME5 COME4 COME3 COME2 COME1 COME0 0 0 0 0 0 - 0 0 COME7 - Modified CCIR656 format vertical sizing enabled. “1” will enable vertical windowing function. “0” will limit vertical size to 480 lines - unchanged by [19] and [1B ]. COME6 - Field luminance average signal generation enable.Value is stored in register [7C] COME5 - “1” First stage aperture correction enable. Correction strength will be decided by register [07]. “0” disable first stage aperture correction. COME4 - “1” Second stage aperture correction enable. Correction strength and threshold value will be decided by register 26 bit 7 ~ register 26 bit 4. COME3 - AWB smart mode enable. 1 - Drop out pixel when compare pixel red, blue and green component level to change register [01] and [02], which luminance level is higher than presetting level and lower than presetting level, this two level is set by register [0F]. 0 - calculate all pixels to get AWB result. Valid only when register 13 bit 0=1 and register 12 bit 2=1 COME2 - Reserved. COME1 - AWB fast/slow mode selection. “1” - AWB is always fast mode, that is register [01] and [02] is changed every field/frame. “0” AWB is slow mode, [01] and [02] change every 16/64 field/ frame decided by register 70 bit 1. When AWB enable, register 12 bit 2=1, AWB is working as fast mode at first 1024 field/frame, than as slow mode later. COME0 - Digital output driver capability increase selection: “1” Double digital output driver current; “0” low output driver current status. Register 21- rw: Y Channel Offset Adjustment Bits Default Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 1 0 0 0 0 0 0 0 Y6-Y0: Y channel digital output offset adjustment. Range: +127mV ~ -127mV. If COMG2=0, this register will be updated by internal auto A/D BLC circuit, and write a value to this register with SCCB has no effect. If COMG2=1, Y channel offset adjustment will use the register stored value which can be changed by SCCB. If COMF1=0, this register has no adjustment effect to A/D output data. If output RGB raw data, this register will adjust R/G/B data. Y7: Offset adjustment direction 0 - Add Y[6:0]; 1 - Subtract Y[6:0]. 38 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. Register 22- rw: U Channel Offset Adjustment Bits Default U7 U6 U5 U4 U3 U2 U1 U0 1 0 0 0 0 0 0 0 U6-U0: U channel digital output offset adjustment. Range: +128mV ~ -128mV. If register 27 bit 2=0, this register will be updated by internal auto A/D BLC circuit, and write a value to this register with SCCB has no effect. If register 27 bit 2=1, U channel offset adjustment will use the register stored value which can be changed by SCCB. If register 26 bit 1=1, this register has no effect to A/D output data. If output RGB raw data, this register will adjust R/G/B data. U7: Offset adjustment direction: 0 - Add U[6:0]; 1 -Subtract U[6:0]. If register 2D bit 0 = 0, this register has no function. Register 23- rw: Crystal Current control. Bits Default CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 0 0 0 - - - - - CC7 - CC6: Crystal amplifier current gain. (00) maximum current; (11) minimum current CC5 ~ CC0: Reserved Register 24- rw: AEW Auto Exposure White Pixel Ratio Bits Interlace Progressive Scan AEW7 AEW6 AEW5 AEW4 AEW3 AEW2 AEW1 AEW0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Registers 24 and 25 together control the AEC target values for image brightness. For a brighter image, increase register 24 and decrease register 25. For a darker image, decrease register 24 and decrease reister 25. AEW7-AEW0 - used to calculate the white pixel ratio. OV7620 AEC algorithm counts the whole field/frame white pixel (its luminance level is higher than a fixed level) and black pixel (its luminance level is lower than a fixed level) number. When white/black pixel ratio is same as the ratio defined by registers [25] and [26], image stable. This register is used to define the white pixel ratio, default is 25%, each LSB represent step: Interlaced: 1.3%; Progressive Scan: 0.7%. Change range is: Interlaced: [01] ~ [4A]; Progressive Scan: [01] ~ [96]. Increase AEW will increase the white pixel ratio. For same light condition, the image brightness will increase if AEW increase. Note: AEW must combined with register [26] AEB. Keep the relation always true: AEW + AEB > [4A] for Interlaced; AEW + AEB > [90]. 39 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) Register 25- rw: AEC Auto Exposure Black Pixel Ratio Bits Interlace Progressive Scan AEB7 AEB6 AEB5 AEB4 AEB3 AEB2 AEB1 AEB0 OMNIVISION TECHNOLOGIES INC. 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 AEB7-AEB0 - used to calculate the black pixel ratio. OV7620 AEC algorithm is count whole field/frame white pixel (its luminance level is higher than a fixed level) and black pixel (its luminance level is lower than a fixed level) number. When white/black pixel ratio is same as the ratio defined by registers [25] and [26], image stable. This register is used to define black pixel ratio, default is 75%, each LSB represent step: Interlaced: 1.3%; Progressive Scan: 0.7%. Change range is: Interlaced: [01] ~ [4A]; Progressive Scan: [01] ~ [96]. Increase AEB will increase black pixel ratio. For same light condition, the image brightness will decrease if AEB increase. Note: AEB must combined with register [25] AEW. Keep the relation always true: AEW + AEB > [4D] for Interlaced; AEW + AEB > [90]. Register 26 - rw: Common control F Bits Default COMF7 COMF6 COMF5 COMF4 COMF3 COMF2 COMF1 COMF0 1 0 1 0 0 0 1 0 COMF7 - COMF6: Digital Sharpness threshold selection. [00] - Difference of neighbor pixel luminance is larger than 8 mV, correction on. [01] - 16 mV. [10] - 32 mV. [11] - 64 mV. COMF5 - COMF4: Digital Sharpness Magnitude selection. [01] - Strength is 50% of difference of neighbor pixel luminance. [10] - 100%. [11] - 200%. COMF3 - Reserved COMF2 - Swap bus MSB/LSB. “1” LSB->Bit7, MSB->Bit0; “0” normal. COMF1 - “1” A/D Black level calibration enable. Do not use “0”. COMF0 - “1” Output first 4 line black level for Interlaced Mode and 8 line black level for Progressive Scan Mode before valid data output. HREF number will increase 4/8 relatively. “0” no black level output. 40 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) Register 27 - rw: Common control G Bits Default COMG7 COMG6 COMG5 COMG4 COMG3 COMG2 COMG1 COMG0 OMNIVISION TECHNOLOGIES INC. 1 1 1 0 0 0 1 0 COMG7: Reserved. COMG6: Reserved. COMG5: Reserved. COMG4: RGB matrix disable. “1” - Bypass RGB matrix. “0” - Enable RGB matrix. COMG3: Reserved. COMG2: “1” Enables manual adjustment of A/D offset: 1 - A/D data will add or subtract a value defined by registers [21] and [22]. 0 - A/D data will be shifted by a value defined by registers [21], [22] and [2E], which is updated by internal circuit. COMG1: - Disables CCIR range clip. COMG0: - Special interface for external micro-controller and RAM timing control. See timing chart. Register 28 - rw: Common control H Bits Default COMH7 COMH6 COMH5 COMH4 COMH3 COMH2 COMH1 COMH0 0 0 0 0 0 0 0 0 COMH7: - “1” selects One-Line RGB raw data output format, “0” selects normal dual-line (repetitive) raw data output, effective only in Progressive Scan mode. COMH6: - “1” enable Black/White mode. COMH5: - “1” select Progressive Scan mode; “0” select Interlaced mode. COMH4: - Freeze AEC/AGC value - current values retained. This is effective only when register 13 bit 0=1. COMH3: - AGC disable. COMH2: - Raw data output format: “1” - Green on Y channel, B R B R....on UV channel (GRB422), “0” - G R G R.... on Y channel, B G B G..... on UV channel. COMH1: - 2x Gain boost. “1” Double PreAmp gain to 6dB. “0” PreAmp gain is 0dB. COMH0: - Reserved. Register 29 - rw: Common control I Bits Default COMI7 COMI6 COMI5 COMI4 COMI3 COMI2 COMI1 COMI0 0 0 0 0 0 0 0 0 COMI7: - AEC disable. “1” If register 13 bit 0=1, AEC stop and register [10] value will be held at last AEC value and not be updated by internal circuit. “0” - if register 13 bit 0=1, register [10] value will be updated by internal circuit COMI6: - Enable slave sync mode selection. “1” slave mode, use external CHSYNC and VSYNC. “0” master mode COMI - Reserved. COMI3: - Central weighted exposure control. COMI2: - Reserved. COMI1 - COMI0: Version flag. 41 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) Register [2A] - rw: Frame Rate Adjust Register 1 Bits Default EHSH7 EHSH6 EHSH5 EHSH4 EHSH3 EHSH2 EHSH1 EHSH0 OMNIVISION TECHNOLOGIES INC. 0 0 0 0 0 0 0 0 EHSH7 - Frame Rate adjustment enable bit. “1” Enable. EHSH - Highest 2 bit of frame rate adjust control byte. See explanation in register [2B]. EHSH4 - “1” - UV component delay 2 pixel. “ 0” no 2*Tp delay. EHSH3 - Y channel brightness adjustment enable. When COMF2=1 active. EHSH2 - For QVGA raw data format. “1” will force Y to output B G B G and UV to output G R G R EHSH - Reserved. Register [2B] - rw: Frame Rate Adjust Register 2 Bits Default EHSL7 EHSL6 EHSL5 EHSL4 EHSL3 EHSL2 EHSL1 EHSL0 0 0 0 0 0 0 0 0 EHSL - Lowest 8 bit of frame rate adjust control byte. Frame rate adjustment resolution is 0.12%. Control word is 10 bit. Every count decreases frame rate by 0.12%. Range is 0.12% - 112%. If frame rate adjustment is enabled, COME7 must be set to “0”. Register [2C] - rw: Black Expanding Register Bits Default EXBK7 EXBK6 EXBK5 EXBK4 EXBK3 EXBK2 EXBK1 EXBK0 1 0 0 0 1 0 0 0 EXBK - Coarse Auto Black Level adjustment. Range is 0.08% - 1.3% EXBK - Fine Auto Black Level adjustment. Range is 0.08% - 1.3%. Register [2D] - rw: Common Control J Bits Default COMJ7 COMJ6 COMJ5 OMJ4 COMJ3 COMJ2 COMJ1 COMJ0 1 0 0 0 0 0 - 1 COMJ7 - Reserved. Always set to “1”. COMJ6 - QVGA 60 frame/s selection. “1” Only Odd field in Interlace Mode data output, “0” Odd/Even field data output frame rate is 30 frames/s. VGA is output at 60 frames/s in dual line mode raw data. COMJ5 - Reserved. Always set to “0”. COMJ4 - Auto brightness enabled. COMJ3 - Reserved. Always set to “0”. COMJ2 - Banding filter enable. After adjust frame rate to match indoor light frequency, this bit enable a different exposure algorithm to cut light band induced by fluorescent light. COMJ1 - Reserved. Always set to “0”. COMJ0 - Reserved. Always set to “1”. 42 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. Register [2E]- rw: V Channel Offset Adjustment Bits Default V7 V6 V5 V4 V3 V2 V1 V0 1 0 0 0 0 0 0 0 V7-V0: V channel digital output offset adjustment. Range: +128mV ~ -128mV. If COMG2=0, this register will be updated by internal auto A/D BLC circuit, and write a value to this register with SCCB has no effect. If COMG2=1, V channel offset adjustment will use the register stored value which can be changed by SCCB. If COMF1=1, this register has no effect to A/D output data. If output raw data, this register will adjust R/G/B data. V7: Offset adjustment direction: o - Add V[6:0]; 0-Substrate V[6:0]. If COMJ0 = 0, this register value is common to U and V channel. Register 2F ~ 5F - w: Reserved Address [2F] - [5F] are reserved for internal use. Register 60- rw: Signal Process Control A Bits Default SPCA7 SPCA6 SPCA5 SPCA4 SPCA3 SPCA2 SPCA1 SPCA0 0 0 1 0 0 1 1 1 SPCA7: 1.5x gain boost. SPCA6: Reserved. SPCA5: “1” disables green averaging for UV channel. SPCA4: “1” disables green averaging for lumninance channel. SPCA Reserved. SPCA: Reserved. Color set to “0111”; B&W set to “0000”. Register 61- rw: Signal Process Control B Bits Default SPCB7 SPCB6 SPCB5 SPCB4 SPCB3 SPCB2 SPCB1 SPCB0 1 0 0 0 0 0 1 0 SPCB7: “1” YUV mode; “0” raw data mode. SPCB6: Reserved. Always set to “0”. SPCB5: Reserved. Always set to “0”. SPCB4: Reserved. Always set to “0”. SPCB3: Reserved. Always set to “0”. SPCB2: Limits range of register [6] to half value. SPCB: Auto Brightness target reference level: (00) -- 0 IRE; (01) -- 6 IRE; (10) -- 10 IRE; (11) -- 20 IRE. 43 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. Register 62- rw: RGB Gamma Control Bits Default RGM7 RGM6 RGM5 RGM4 RGM3 RGM2 RGM1 RGM0 0 0 0 1 0 0 1 0 RGM raw data or UV gamma curve selection. RGM0: Reserved. Always set to “0”. Register 63- rw: Reserved Address [63] are reserved for internal use. Register 64- rw: Y Gamma Control Bits Default YGM7 YGM6 YGM5 YGM4 YGM3 YGM2 YGM1 YGM0 0 1 0 1 1 0 0 1 YGM: Y gamma curve selection. YGM: “1” enable; “0” disable (linear). Register 65- rw: Signal Process Control C Bits Default SPCC7 SPCC6 SPCC5 SPCC4 SPCC3 SPCC2 SPCC1 SPCC0 0 1 0 0 0 0 1 0 SPCC Reserved. SPCC2: A/D mode selection. Increase A/D range by 1.5X SPCC: A/D reference selection. : input signal range 0.9V; : 1.0V peak : 1.15V peak; : 1.26V peak. Do not use selection. 44 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) Register 66- rw: AWB Process Control Bits Default AWBC7 AWBC6 AWBC5 AWBC4 AWBC3 AWBC2 AWBC1 AWBC0 OMNIVISION TECHNOLOGIES INC. 0 1 0 1 0 1 0 1 White balance limiting function - YUV matrix control. Register 74:7 must be enabled for AWB process control. AWBC: Smart AWB ignores RGB raw data pixel values above (00):70%, (01): 80%, (10): 90%, (11):100%. AWBC: Smart AWB ignores RGB raw data pixel values below (00):10%, (01) 20%, (10) 30%, (11) 40%. AWBC: U threshold level selection if use U/V as white balance feedback 00: (-10% ~ 10%); 01: (-20% ~ 20%); 10: (-30% ~ 30%); 11: (-40% ~ 40%) AWBC: V threshold level selection if use U/V as white balance feedback 00: (-10% ~ 10%); 01: (-20% ~ 20%); 10: (-30% ~ 30%); 11: (-40% ~ 40%) Register 67- rw: Color Space Selection Bits Default YUV7 YUV6 YUV5 YUV4 YUV3 YUV2 YUV1 YUV0 0 0 0 1 1 0 1 0 YUV: UV coefficient selection (U/V is output and u/v is input) • [00]: YUV • [01]: Analog YUV • [10]: CCIR 601 YCrCb • [11]: PAL YUV YUV5: U/V signal delay 2 pixel selection YUV4: U/V signal with 3 point chroma average(2 pixel delay accordingly) YUV: Y signal delay selection: (00) - 0; (01) - 1; (10) - 2; (11) - 3 pixels YUV1: Auto saturation control (decreases color noise) enable. YUV0: Auto saturation control range selection: 0 - 1.5x; 1 - 1x. Register 68- rw: Signal Process Control D Bits Default SPCD7 SPCD6 SPCD5 SPCD4 SPCD3 SPCD2 SPCD1 SPCD0 1 1 0 0 1 1 0 0 SPCD: AEC/AGC Brighness Target level selection. 000 - 10%; 001 - 30%; 010 - 50%; 011 - 70%; 100 - 80%; 101 - 90%; 110 - 100%; 111 - 110%. SPCD4: Reserved. Always set to “0”. SPCD: Anti-alias threshold: 11 lowest threshold; 01, 10 midrange threshold; 00 highest threshold. SPCD: Anti-alias magnitude: 00 - low strength; 01, 10 mid strength; 11:high strength. 45 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) Register 69- rw: Analog Sharpness Bits Default EDGE7 EDGE6 EDGE5 EDGE4 EDGE3 EDGE2 EDGE1 EDGE0 OMNIVISION TECHNOLOGIES INC. 0 1 1 1 0 0 1 0 EDGE Reserved. EDGE2: Vertical Edge Enhancement enable. Register 20:5 must be set to “1”. EDGE: Reserved. Register 6A- rw: Vertical Edge Enhancement Control Bits Default VEG7 VEG6 VEG5 VEG4 VEG3 VEG2 VEG1 VEG0 - 1 0 0 0 0 1 0 VEG: Vertical Edge Enhancement threshold range VEG: Vertical Edge Enhancement magnitude value. 0000: weakest; 1111: strongest. Register 6B-6E rw: Reserved Address [6B] - [6E] are reserved for internal use. Register 6F - rw: Even/Odd Noise Compensation Control Bits Default EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 - - 1 1 1 0 1 0 EOC: Reserved. EOC: Color Kill luminance threshold selection: 00 - none; 01 - 2.6v; 10 - 2.4v; 11 - 2.3v. Lower luminance selection will activate color kill. EOC: Set to factory recomended values. 46 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) Register 70 - rw: Common Control K Bits Default COMK7 COMK6 COMK5 COMK4 COMK3 COMK2 COMK1 COMK0 OMNIVISION TECHNOLOGIES INC. 1 0 0 0 0 0 0 1 COMK7 - “1” HREF edges coincident (no delay) with PCLK negative/falling edges (COMD6 must be set to “0”). “0” HREF edge occurs 10 ns after PCLK positive/rising edge. COMK6 - Output port drive current additional 2x control bit. COMK5 - Reserved. COMK4 - Selects ZV port timing. “1” VSYNC output ZV port vertical sync signal. “0” normal TV vertical sync signal. COMK3 - Accelerated saturation mode for camera mode change. (QVGA, 8 Bit output, CCIR 656 mode and Progressive Scan Mode). After relative control bit set, the first VS will be the stable image with suitable AEC/AWB setting. “0” - slow mode, after mode change need more field/frame to get stable AEC/AWB setting image. COMK2 - Reserved. COMK1 - AWB update rate selection. “1” fast mode; “0” slow mode. COMK0 - Set to “1” in single line mode, otherwise set to “0” and set COMG4 to disable. Register 71 - rw: Common Control J Bits Default COML7 COML6 COML5 COML4 COML3 COMK2 COML1 COML0 0 0 0 0 0 0 0 0 COML7 - Auto Brightness update rate: “1” - Slow mode; “0” - fast mode. COML6 - Gated PCLK selection. “1” - Enables PCLK gated by HREF; “0” - PCLK is free running clock COML5 - Swap HREF output pin with CHSYNC. “1” - HREF pin output CHSYNC signal; “0” - No swap. COML4 - Swap CHSYNC output pin with HREF. “1” - CHSYNC pin output HREF signal; “0” - normal output. COML- Highest 2 bit for HSYNC rising edge shift control, combined with register [72] COML- Highest 2 bit for HSYNC falling edge shift control, combined with register [73] Register 72- rw: Horizontal Sync 1st Edge shifting Bits Default HSDY7 HSDY6 HSDy5 HSDY4 HSDY3 HSDY2 HSDY1 HSDY0 0 0 0 1 0 1 0 0 HSDY - Lower 8 bit control for shifting horizontal sync CHSYNC first edge. Range is [000] - [3FF]. Every count equals 1 PCLK. 47 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) Register 73 - rw: Horizontal Sync 2nd Edge shifting Bits Default HEDY7 HEDY6 HEDY5 HEDY4 HEDY3 HEDY2 HEDY1 HEDY0 OMNIVISION TECHNOLOGIES INC. 0 1 0 1 0 1 0 0 HSDY - Lower 8 bit control for shifting horizontal sync CHSYNC second edge. Range is [000] - [3FF]. Every count equals 1 PCLK. Register 74 - rw: Common Control M Bits Default COMM7 COMM6 COMM5 COMM4 COMM3 COMM2 COMM1 COMM0 0 0 1 0 0 0 0 0 COMM7 - Enable UV Smart AWB threshold control. COMM - AGC maximum gain selection: 00 - 2x; 01 - 4x; 10 - 2x; 11 - 8x COMM - Reserved. Register 75 - rw: Common Control N Bits Default COMN7 COMN6 COMN5 COMN4 COMN3 COMN2 COMN1 COMN0 1 0 0 0 0 0 1 0 COMN7 - “1” enables Auto brightness range limit. Minimum will be [40]. Otherwise will be [00] ~ [FF]. COMN - Reserved. COMN2 - This bit further reduces the exposure time to 1/120 second or 1/100 second when the banding filter is enabled and the light is too strong. COMN1- If enabled, manual write white balance value, then change to auto, the stable time will be less. Speeds white balance stable time when switching from manual to AWB. COMN0 - Enables addition of 2 pixel averaging. Register 76 - rw: Common Control O Bits Default COMO7 COMO6 COMO5 COMO4 COMO3 COMO2 COMO1 COMO0 0 0 0 0 0 0 0 0 COMO7 - Output XCLK from FODD pin. COMO6 - Reserved. COMO5 - Software power down enable: 1 - enable; 0 - wake up COMO4 - Reserved. COMO3 - Limits the Minimum Exposure time to 4 lines rather 1 line with AEC enable COMO2 - Tri-state sync and CLK output, except data line COMO - Reserved. 48 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) Register 77-7B - rw: Reserved Address [2F] - [5F] are reserved for internal use. OMNIVISION TECHNOLOGIES INC. Register 7C - rw: Field Average Level Storage Bits Default AVG7 AVG6 AVG5 AVG4 AVG3 AVG2 AVG1 AVG0 0 0 0 0 0 0 0 0 AVG -- Strorage fileld luminance average value if register 20 bit 6=1. Notice: for QVGA and Progressive Scan mode, the real luminance average value is double of this register value, other mode is same. If set to RGB raw data mode, the value is Green component average value. 49 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. SECTION 2 PIN DESCRIPTION 2.1 PINOUT ASUB VrEQ FREX A GC E N FSIN SVD D S GN D MU L T SIO-0 SIO-1 DEVDD D E GN D 6 5 4 3 2 1 48 47 46 45 44 43 7 8 9 10 11 12 13 14 15 16 17 18 AGND AVDD PWDN NS1 VcCHG SBB VTO ADVDD ADGND VSYNC / CSYS FODD/SRAM HREF/VSFRAM OV7620 top view BW/CHSYNC CBAR/Y0 PROG/Y1 G2X / Y2 RGB / Y3 CS1 / Y4 SHARP / Y5 CS2 / Y6 CS0 / Y7 PWDB/PCLK DOVDD DOGND 42 41 40 39 38 37 36 35 34 33 32 31 FIG 2.1 OV7620 48Pin Digital Package 19 20 21 22 23 24 25 26 27 28 29 30 UV7 / B8 UV6 / BPAL F UV5 / MIR UV4 /SLAEN UV3 / ECL KO U V 2 / QV GA UV1 / CC656 U V 0 / GA MMA XCL K1 XCL K2 DVDD D GN D 50 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. ELECTRICAL SPECIFICATION Table 3.1: DC CHARACTERISTICS (0oC < TA < 85oC, Voltages referenced to GND) Symbol Descriptions Min Max Typ Units Supply VDD1 VDD2 IDD1 IDD2 Supply voltage- internal analog DEVDD,ADVDD,AVDD,SVDD,AOVDD,DVDD Supply voltage - internal digital &output digital (DOVDD) Supply Current (@ 60Hz frame rate & 5 volt digital I/O,25pf + 1TTL load on 16 bit data bus) Standby supply current 4.75 4.5 3.0 5.25 5.5 3.6 40 10 5.0 5.0 3.3 5 V V V mA uA Digital Inputs VIL VIH Cin input voltage LOW input voltage HIGH input capacitor 2.0 0.8 10 V V pF Digital Outputs - standard load 25pf, 1.2kΩ to 3.0volts VOH VOL output voltage HIGH output voltage LOW 2.4 0.6 V V SCCB Inputs VIL VIH VIL VIH SIO-0 and SIO-1 (VDD2=5V) SIO-0 and SIO-1(VDD2=5V) SIO-0 and SIO-1 (VDD2=3V) SIO-0 and SIO-1(VDD2=3V) -0.5 3.0 -0.5 2.5 1.5 Vdd + .5 1 3.5 0 5 0 3 V V V 51 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. Table 3.2: ANALOG CHARACTERISTICS (TA=25oC; Vdd=5V) Symbol Descriptions Min Max Typ Units RGB/YCrCb output Iso Vrgb Vy maximum sourcing current DC level at zero signal RGB peak-peak amplitude DC level at zero signal Y peak-peak 100% amplitude (without sync) sync amplitude DC level at zero signal Cr peak-peak (75% saturation) DC level at zero signal Cb peak-peak (75% saturation) 15 1 1 1 1 0.3 1.2 700 1.2 890 mA V V V V V V mV V mV Vry Vby User Adjustable Controls (VcBRT) Ri input resistance 100 ΚΩ factory set reference bias (VrAD1,VrAD2,VrAD3,VrEQ,VrPK,NSSA1,VcCHG, VcBLM) VrEQ NS1SA1 VcCHG biased level SA1 reference level Photo cell Charge level 2.0 3.0 2.5 2.2 2.6 V V V ADC parameters B DLE ILE analog bandwidth DC differential linearity error DC integral linearity error 0.5 0.5 MHz LSB LSB 52 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. Table 3.3: AC CHARACTERISTICS (0oC < TA < 85oC, Voltages referenced to GND) Symbol Descriptions Min Max Typ Units Oscillator & Clock in fosc tr , tf CLKO V frequency (XCLK1,XCLK2) clock input rise/fall time clock input duty cycle 45 10 30 5 55 50 27.0 MHz ns % SCCB timing(400kbit/s) tBUF tHD:SAT tLOW tHIGH tHD:DAT tSU:DAT tSU:STP Bus free time between STOP & START SIO-1 change after START status SIO-1 low period SIO-1 high period Data hold time Data set-up time Set-up time for STOP status 1.3 0.6 1.3 0.6 0 0.1 0.6 us us us us us us us Digital timing tpclk PCLK cycle time 16 bit operation 8 bit operation PCLK rise/fall time PCLK to data valid PCLK to HREF delay 74 37 5 15 15 20 10 ns ns ns ns ns tr,tf tpdd tphd 53 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. tr tf tpclk PCLK tphd tphd HREF tpdd Y UV 10 Y Y 10 80 U V 80 FIG 2.2 Pixel Timing 54 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. tBUF SIO-0 tHD:DAT tHD:SAT SIO-1 tHIGH tLOW tSU:DAT tSU:STP FIG 2.3 SCCB Bus Timing 55 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. h10 Y0 Y1 Y642 Y643 h10 h10 U0 V0 U642 V643 h10 (a) HORIZONTAL TIMING 483 484 1 2 3 241 242 243 (b) VERTICAL TIMING (Interlaced Mode) FIG 2.4 16 Bit 4:2:2 Video Port Timing (Interlaced Mode) 56 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. h10 Y0 Y1 Y642 Y643 h10 h10 U0 V0 U642 V643 h10 (a) HORIZONTAL TIMING 1 2 483 484 (b) VERTICAL TIMING (Progressive Scan Mode) FIG 2.5 16 Bit 4:2:2 Video Port Timing (Progressive Scan Mode) 57 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. 3. Different Method to get QVGA format Compare Table 3.4: Compare of QVGA Method Method A B C D Resolution 320x240 320x240 322x240 354x288 Frame Rate 60 frame/s 30 frame/s 30 frame/s 30 frame/s 1/3” 1/3” 1/4” 1/4” Lens Note: To get the frame rate, OV7620 must use 27 MHz crystal. 58 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. 0.440 ±0.005 31 0.040 ±0.003 42 +0.010 0.060 -0.005 TYP. 0.040 ±0.007 TYP. 43 NOTES: 1) All dimensions in inches 30 48 Bottom View 0.020 ±0.003 TYP. 19 6 R 0.0075 18 4 CORNERS R 0.0075 48 PLCS 7 0.085 ±0.010 0.003 0.003 0.065 ±0.007 0.002 0.030 ±0.003 0.015 ±0.002 0.020 ±0.002 0.036 MIN. 42 +0.012 0.560 SQ. -0.005 0.430 SQ. ±0.005 0.350 SQ. ±0.005 31 31 30 43 43 42 30 Side View 48 1 6 6 7 7 0.006 MAX. 0.002 TYP. 18 19 19 Top View 18 FIG 2.6 Package Mechanical Data 59 Preliminary Company Confidential OV7620 Product Specifications - Rev. 1.2 (5/13/00) OMNIVISION TECHNOLOGIES INC. . 1 Array Center (0.0094, 0.0015) DIE Sensor Array Package Center (0, 0) Top View FIG 2.7 OV7620 Sensor Array Location (in inches) Ordering Information Part Number OV7620 Color Digital Sensor Description Comments 48 pin LCC OmniVision Technologies, Inc. reserves the right to make changes without further notice to any product herein to improve reliability, function, or design. OmniVision Technologies, Inc. does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. No part of this publication may be copied or reproduced, in any form without the prior written consent of OmniVision Technologies, Inc. 60