PE3293

PRODUCT SPECIFICATION PE3293 Product Description The PE3293 is a dual fractional-N phase-lock loop (PLL) IC designed for frequency synthesis and fabricated on Peregrine’s patented UTSi® CMOS process. Each PLL includes a prescaler, phase detector, charge pump and on-board fractional spur compensation. The patented spur compensation circuitry designed into the device ensures superior spur performance over the full temperature and VCO tuning range. The PE3293 provides fractional-N division with power-oftwo denominator values up to 32. This allows comparison frequencies up to 32 times the channel spacing, providing a lower phase noise floor than integer PLLs. The 32/33 RF prescaler (PLL1) operates up to 1.8 GHz and the 16/17 IF prescaler (PLL2) operates up to 550 MHz. Applications • Triple mode,dual-band PCS / Cellular handset • PCS/CDMA/Cellular handsets • PCS/CDMA/Cellular base stations Figure 1. Block Diagram 1.8 GHz / 550 MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis Features • Industry leading fractional spur compensation: no adjusting required, stable over temp. • Ultra-Low Power consumption: 4.0 mA typical, both loops operating • Modulo-32 fractional-N main counters • Supply voltage range 2.7 to 3.3 VDC fin1 32/33 Prescaler 19-bit Fractional-N Main Divider Fractional Spur Compensation fr Ref. Amp. 9-bit Reference Divider Phase Detector Charge Pump CP1 Clock Data LE 21-bit Serial Control Interface Multiplexer foLD 9-bit Reference Divider Phase Detector Charge Pump CP2 fin2 16/17 Prescaler 18-bit Fractional-N Main Divider Fractional Spur Compensation PEREGRINE SEMICONDUCTOR CORP.  | http://www.peregrine-semi.com Copyright  Peregrine Semiconductor Corp. 2003 Page 1 of 18 PE3293 Product Specification Figure 2. Pin Configuration: TSSOP (JEDEC MO-153-AC) N/C VDD CP1 GND fin1 Dec1 VDD1 fr GND 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VDD VDD CP2 GND fin2 DEC2 VDD2 LE Data Clock foLD 10 Table 1. Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name N/C VDD CP1 GND fin1 Dec1 VDD1 fr GND foLD Clock Data LE VDD2 Dec2 fin2 GND CP2 VDD VDD Type No connect. (Note 1) Output Description Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external VCO. Ground. Input Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.8 GHz. Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. PLL1 prescaler power supply. 3.3 kohm resistor to VDD. Input Reference frequency input. Ground. Output Input Input Input Output Output Input Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and data out of the shift register. CMOS output (see Table 11, foLD Programming Truth Table). CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift register. Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits. Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into one of the four appropriate latches (as assigned by the control bits). PLL2 prescaler power supply. 3.3 kohm resistor to VDD. Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550 MHz. Ground. Output (Note 1) (Note 1) Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external VCO. Same as pin 2. Same as pin 2. Note 1: VDD pins 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level. Copyright  Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi  CMOS RFIC SOLUTIONS Page 2 of 18 PE3293 Product Specification Figure 3. Pin Configuration: 24-Pin BCC (Top View) GND N/C CP2 VDD VDD N/C VDD N/C 19 20 21 22 23 24 1 2 3 4 5 6 18 fin2 17 Dec2 16 VDD2 15 LE 14 13 12 11 10 9 8 7 N/C Data Clock foLD GND fr N/C CP1 GND fin1 VDD1 DEC1 Table 2. Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Name N/C CP1 GND fin1 Dec1 VDD1 N/C fr GND foLD Clock Data N/C LE VDD2 Dec2 fin2 GND N/C CP2 VDD Type No connect. Output Description Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external VCO. Ground Input Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.8 GHz. Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. PLL1 prescaler power supply (FlexiPower 1). No connect. Input Reference frequency input. Ground. Output Input Input Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and data out of the shift register. CMOS output (see Table 11, foLD Programming Truth Table). CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift register. Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits. No connect. Input Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into one of the four appropriate latches (as assigned by the control bits). PLL2 prescaler power supply. 3.3 kohm resistor to VDD. Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Input Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550MHz. Ground. No connect. Output (Note 1) Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external VCO. Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. http://www.peregrine-semi.com Copyright  Peregrine Semiconductor Corp. 2003 PEREGRINE SEMICONDUCTOR CORP.  | Page 3 of 18 PE3293 Product Specification Pin No. 22 23 24 Pin Name VDD N/C VDD Type (Note 1) Same as pin 21. No connect. (Note 1) Same as pin 21. Description Note 1: VDD pins 21, 22, and 24 are connected by diodes and must be supplied with the same voltage level. PE3293 Description The PE3293 is intended for such applications as the local oscillator for the RF and first IF of dualconversion transceivers. The RF PLL (PLL1) includes a 32/33 prescaler with a 1.8 GHz maximum frequency of operation, where the IF PLL (PLL2) incorporates a 16/17 prescaler with a 550 MHz maximum frequency of operation. Using an advanced fractional-N phase-locked loop technique, the PE3293 can generate a stable, very low phase- noise signal. The dual fractional architecture allows fine resolution in both PLLs, with no degradation in phase noise performance. Data is transferred into the PE3293 via a threewire interface (Data, Clock, LE). Supply voltage can range from 2.7 to 3.3 volts for VDD. PE3293 features very low power consumption and is available in a JEDEC MO-153-AC (TSSOP), 20pin package and 24-lead BCC package. Spurious Response A critical parameter for synthesizer designs is spurious output. Spurs occur at the integer multiples of the step size away from center tone. An important feature of fractional synthesizers is their ability to reduce these spurious sidebands. The PE3293 has a built-in method for reducing these spurs, with no external components or tuning required. In addition, this circuitry works over the full commercial temperature and VCO tuning range. Copyright  Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi  CMOS RFIC SOLUTIONS Page 4 of 18 PE3293 Product Specification Table 3. Absolute Maximum Ratings Symbol VDD VDDI, VDD2 VI Electrostatic Discharge (ESD) Precautions Max 4.0 VDD VDD + 0.3 +10 150 Parameter/Conditions Supply voltage Prescaler supply voltage Voltage on any input Min -0.3 -0.3 -0.3 Units V V V When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 5. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up. II Tstg DC into any input Storage temperature range -10 -65 mA °C Table 4. Operating Ratings Symbol VDD VDD1, VDD2 TA Parameter/Conditions Supply voltage Prescaler supply voltage Operating ambient temperature range Min 2.7 0.8 -40 Max 3.3 VDD 85 Units V °C °C Table 5. ESD Ratings Symbol VESD Parameter/Conditions ESD voltage human body model (Note 1) Level 2000 Units V Note 1: Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2 PEREGRINE SEMICONDUCTOR CORP.  | http://www.peregrine-semi.com Copyright  Peregrine Semiconductor Corp. 2003 Page 5 of 18 PE3293 Product Specification Table 6. DC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol IDD Istby VIH VIL IIH IIL IIHR IILR VOLD VOHD ICP - Source ICP - Sink ICPL ICP – Source vs. ICP - Sink ICP vs TA ICP vs. VCP Parameter 3 V supply current Total standby current High level input voltage Low level input voltage High level input current Low level input current Input current Input current Output voltage LOW Output voltage HIGH Conditions C10, C20 = 00 (both PLLs on) Min Typ 4.0 5.0 Max 50 Units mA µA V Digital inputs: Clock, Data, LE VDD = 2.7 to 3.3 volts VDD = 2.7 to 3.3 volts VIH = VDD = 3.3 volts VIL = 0, VDD = 3.3 volts VIH = VDD = 3.3 volts VIL = 0, VDD = 3.3 volts Iout = 1 mA Iout = -1 mA VDD – 0.4 -70 -70 -5 10 10 10 5 % % % -25 0.4 -1 -1 0.7 x VDD 0.3 x VDD +1 +1 +25 V µA µA µA µA V V µA µA nA Reference Divider input: fr Digital output: foLD Charge Pump outputs: CP1, CP2 Drive current Leakage current Sink vs. source mismatch Output current vs. temperature Output current magnitude variation vs. voltage VCP = VDD / 2 0.5 V < VCP < VDD – 0.5 volt VCP = VDD / 2, TA = 25° C VCP = VDD / 2 0.5 V < VCP < VDD – 0.5 volt, TA = 25° C Copyright  Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi  CMOS RFIC SOLUTIONS Page 6 of 18 PE3293 Product Specification Table 7. AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol fClock tClockH tClockL tDSU tDHLD tLEW tCLE tLEC tData Out fin1 fin2 Pfin1 Pfin2 fc Reference Divider fr Vfr Note 1: Operating frequency Input sensitivity CMOS logic levels may be used if DC coupled. External AC coupling (note 1) 0.5 50 MHz VP-P Parameter Serial data clock frequency Serial clock HIGH time Serial clock LOW time Data set-up time to Clock rising edge Data hold time after Clock rising edge LE pulse width Clock falling edge to LE rising edge LE falling edge to Clock rising edge Data Out delay after Clock falling edge (foLD pin) Operating frequency Operating frequency Input level range Input level range Comparison frequency CL = 50 pf Conditions Min Max 10 Units MHz ns ns ns ns ns ns ns Control Interface and Latches (see figure 6) 50 50 50 10 50 50 50 90 300 45 External AC coupling External AC coupling -7 -10 1800 550 5 5 10 ns MHz MHz dBm dBm MHz Main Divider (Including Prescaler) PEREGRINE SEMICONDUCTOR CORP.  | http://www.peregrine-semi.com Copyright  Peregrine Semiconductor Corp. 2003 Page 7 of 18 PE3293 Product Specification Functional Description The Functional Block Diagram in Figure 5 shows a 21-bit serial control register, a multiplexed output, and PLL sections PLL1 and PLL2. Each PLL contains a fractional-N main counter chain, a reference counter, a phase detector, and an internal charge pump with on-chip fractional spur compensation. Each fractional-N main counter chain includes an internal dual modulus prescaler, supporting counters, and a fractional accumulator. Serial input data is clocked on the rising edge of Clock, MSB first. The last two bits are the address bits that determine the register address. Data is transferred into the counters as shown in Table 8, PE3293 Register Set. If the foLD pin is configured as data out, then the contents of shift register bit S20 are clocked on the falling edge of Clock onto the foLD pin. This feature allows the PE3293 and compatible devices to be connected in a daisychain configuration. The PLL1 (RF) VCO frequency fin1 is related to the reference frequency fr by the following equation: fin1 = [(32 x M1) + A1 + (F1/32)] x (fr/R1) (1) Note that A1 must be less than or equal to M1. Also, fin1 must be greater than or equal to 1024 x (fr/R1) to obtain contiguous channels. The PLL2 (IF) VCO frequency fin2 is related to the reference frequency fr by the following equation: fin2 = [(16 x M2) + A2 + (F2/32)] x (fr/R2) (2) Note that A2 must be less than or equal to M2. Also, fin2 must be greater than or equal to 256 x (fr / R2) to obtain contiguous channels. F1 sets PLL1 fractionality. If F1 is an even number, the PE3293 automatically reduces the fraction. For example, if F1 = 12, then the fraction 12/32 is automatically reduced to 3/8. In this way, fractional denominators of 2, 4, 8, 16 and 32 are available. F2 sets the fractionality for PLL2 in the same manner. Figure 4. Functional Block Diagram A1 5 A1 Counter 0