PLL500-17TCL-R

P LL500-17 L ow Phase Noise VCXO (17MHz to 36MHz) F EATURES • • • • • • • • • • V CXO output for the 17MHz to 36MHz range L ow phase noise (-130 dBc @ 10kHz offset at 35.328MHz). C MOS output with OE tri-state control. 1 7 to 36MHz fundamental crystal input. I ntegrated high linearity variable capacitors. 1 2mA drive capability at TTL output. + /- 150 ppm pull range, max 5% linearity. L ow jitter (RMS): 2.5ps period jitter. 2 .5 to 3.3V operation. A vailable in 8-Pin SOIC, 6-pin SOT23 packages, or DIE. B LOCK DIAGRAM PIN CONFIGURATION XIN VDD* VIN GND 1 2 3 4 8 7 6 5 XOUT OE^ VDD* CLK ^: Denotes internal Pull-up *: Only one VDD pin needs to be connected PLL500-17 D ESCRIPTION T he PLL500-17 is a low cost, high performance and low phase noise VCXO for the 17 to 36MHz range, providing less than -130dBc at 10kHz offset at 35.328MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 17 to 36MHz (fundamental resonant mode). OUT GND CLK 1 2 3 6 5 4 XIN VDD VIN PLL500-17 F REQUENCY RANGE M ULTIPLIER N o PLL FREQUENCY 17 – 36 MHz OUTPUT BUFFER CMOS 8-pin SOIC 6-pin SOT XIN XOUT XTAL OSC VARICAP OE VCON 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 03/29/05 Page 1 P LL500-17 L ow Phase Noise VCXO (17MHz to 36MHz) D IE PAD LAYOUT 32 mil (812,986) DIE SPECIFICATIONS N ame Value 8 1 XIN XOUT OE^ 7 39 mil 2 VDD VDD 6 S ize R everse side P ad dimensions T hickness 39 x 32 mil GND 80 micron x 80 micron 10 mil 3 VCON 4 GND CLK 5 DIE ID: PLL500-17: C500A0404-04A Y X (0,0) Note: ^ denotes internal pull up P IN ASSIGNMENT (8-pin SOIC package) AND PAD DESCRIPTION (8-pin SOIC package) N ame X IN V DD V CON G ND C LK V DD OE X OUT Pin# 1 2 3 4 5 6 7 8 D ie Pad Position X ( µ m) 94.183 94.157 94.183 94.193 715.472 715.307 715.472 476.906 Y ( µ m) 768.599 605.029 331.756 140.379 203.866 455.726 626.716 888.881 Type I P I P O P I I Description Crystal input pin. VDD power supply pin. Only one VDD pin is necessary. Frequency control voltage input pin. Ground pin. Output clock pin. VDD power supply pin. Only one VDD pin is necessary. Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected to low. Crystal output pin. Ref Clock input. * O E (Output Enable) pin is not available in SOT-26 package, the output will always be enabled by the build in pull-up resister. P IN ASSIGNMNET AND DESCRIPTION (6-pin SOIC package) N ame X OUT G ND C LK V CON V DD X IN Pin# 1 2 3 4 5 6 Type I P O I P I Description Crystal Output pin. Ref. Clock input. Ground pin. Output clock pin. Frequency control voltage input pin. VDD power supply pin. Crystal input pin. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 03/29/05 Page 2 P LL500-17 L ow Phase Noise VCXO (17MHz to 36MHz) E LECTRICAL SPECIFICATIONS 1 . Absolute Maximum Ratings P ARAMETERS S upply Voltage I nput Voltage, dc O utput Voltage, dc S torage Temperature A mbient Operating Temperature* J unction Temperature L ead Temperature (soldering, 10s) E SD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. - 0.5 - 0.5 - 65 - 40 MAX. 4 .6 V DD +0.5 V DD +0.5 150 85 1 25 260 2 UNITS V V V °C °C °C °C kV E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * N ote : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2 . AC Electrical Specifications P ARAMETERS I nput Crystal Frequency O utput Clock Rise/Fall Time O utput Clock Duty Cycle S hort Circuit Current 0 .8V ~ 2.0V with 10 pF load 0 .3V ~ 3.0V with 15 pF load M easured @ 1.4V 45 SYMBOL CONDITIONS MIN. 17 TYP. 1.15 3.7 50 ± 50 MAX. 36 UNITS MHz ns 55 % mA 3 . Voltage Control Crystal Oscillator P ARAMETERS V CXO Stabilization Time * V CXO Tuning Range C LK output pullability V CXO Tuning Characteristic P ull range linearity P ower Supply Rejection V CON pin input impedance V CON modulation BW PWSRR SYMBOL T VCXOSTB CONDITIONS F rom power valid F XIN = 1 2 – 25MHz; XTAL C 0 /C 1 < 2 50 0V ≤ V CON ≤ 3 .3V VCON=1.65V, ± 1.65V MIN. TYP. MAX. 10 UNITS ms ppm ppm ppm/V % ppm kΩ kHz 300 ± 150 1 00 5 F requency change with VDD varied +/- 10% 0 V ≤ V CON ≤ 3 .3V, -3dB -1 2 000 45 +1 N ote: P arameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4 . Jitter and Phase Noise Specifications 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 03/29/05 Page 3 P LL500-17 L ow Phase Noise VCXO (17MHz to 36MHz) P ARAMETERS R MS Period Jitter (1 sigma – 1000 samples) P hase Noise relative to carrier P hase Noise relative to carrier P hase Noise relative to carrier P hase Noise relative to carrier P hase Noise relative to carrier CONDITIONS With capacitive decoupling between VDD and GND. 36MHz @100Hz offset 36MHz @1kHz offset 36MHz @10kHz offset 36MHz @100kHz offset 36MHz @1MHz offset MIN. TYP. 2.5 -80 -110 -130 -138 -145 MAX. UNITS ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 5 . DC Specifications P ARAMETERS S upply Current, Dynamic, with Loaded Outputs O perating Voltage O utput Low Voltage at CMOS level O utput High Voltage at CMOS level O utput drive current S hort Circuit Current V CXO Control Voltage SYMBOL I DD V DD V OLC V OHC CONDITIONS F XIN = 3 6MHz Output load of 15pF MIN. TYP. 5 MAX. 6 3.63 0.4 UNITS mA V V V 2 .25 I OL = + 4mA I OH = - 4mA For V OL 2.4V V DD – 0 .4 8 0 9.5 ± 50 VCON V DD mA mA V 6 . Crystal Specifications P ARAMETERS C rystal Resonator Frequency C rystal Loading Rating (VCON = 1.65V) M aximum Sustainable Drive Level O perating Drive Level C0 C 0/C1 E SR SYMBOL F XIN C L (xtal) MIN. 17 TYP. 8 .5 MAX. 36 200 UNITS MHz pF µW µW pF Ω 50 5 250 30 RS N ote : The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 03/29/05 Page 4 P LL500-17 L ow Phase Noise VCXO (17MHz to 36MHz) P ACKAGE INFORMATION 8 PIN ( dimensions in mm ) Narrow SOIC Symbol A A1 B C D E H L e Min. 1.47 0.10 0.33 0.19 4.80 3.80 5.80 0.38 Max. 1.73 0.25 0.51 0.25 4.95 4.00 6.20 1.27 1.27 BSC A 1 e B A C L D E H 6 - p in SOT ( Dimensions in mm ) 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 03/29/05 Page 5 P LL500-17 L ow Phase Noise VCXO (17MHz to 36MHz) O RDERING INFORMATION F or part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER T he order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL500-17 X X R Part Number Package S=SOIC T= SOT D=Die NONE= TUBE R=TAPE and REEL Temperature C=Commercial I= Industrial P art / Order Number P LL500-17DC P LL500-17SC P LL500-17SC-R P LL500-17SCL P LL500-17SCL-R P LL500-17TC P LL500-17TC-R P LL500-17TCL P LL500-17TCL-R Marking P500-17DC P500-17 P500-17 P500-17L P500-17L P500-17 P500-17 P500-17L P500-17L Package Option Die (Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 6-Pin SOT (Tube) 6-Pin SOT (Tape and Reel) 6-Pin SOT (Tube) 6-Pin SOT (Tape and Reel) P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 01/21/05 Page 6