RTC-8564JE

Real time clock module I2 C-BUS INTERFACE REAL TIME CLOCK MODULE • Built-in crystal unit allows adjustment-free efficient operation. • Compliant with I C high-speed bus specifications. (400 kHz) • Equipped with alarm, timer, and frequency output (32.768 kHz, 1024 Hz,32 Hz,1 Hz) features. • Inclusion of century bit to enable correct date even after year 2000 • Operating in wide voltage range from 1.8 to 5.5 V, and in wide range of clock voltage from 1.2 to 5.5 V. • Low power consumption at 275 nA/3.0 V. (Typ.) 2 RTC-8564JE Actual size Specifications (characteristics) Absolute Max. rating Item Supply voltage Input voltage Output voltage DC Input current DC Output current Symbol VDD IDD Vi Vo Ii Io TSTG As single part Condition Min. -0.5 -50 GND-0.5 Max. +6.5 50 VDD+0.5 Unit V mA V The I 2 C-Bus is a trademark of Philips Electronics N.V. Terminal connection No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin terminal N.C N.C CLKOE VDD CLKOUT SCL SDA (GND) GND INT N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C Between VDD and GND VDD pin Input pin INT pins — -10 -55 10 +125 mA 2019 18 17 1615 14 13 12 11 Storage temperature Range ˚C Operating range Item Supply voltage range Clock voltage range VDD TOPR Symbol Condition Min. 1.8 VLOW — -40 5.5 +85 V ˚C Max. Unit 1 2 3 4 5 6 7 8 9 10 I2C-BUS access at 400 kHz Operating temperature range Frequency characteristics Item Frequency precision Frequency temperature characteristics Frequency voltage characteristics Oscillation start-up time Symbol ∆f/fo T op fv tSTA fa Condition Ta=+25 ˚C, VDD=3.0 V Ta=+25˚C, -10 to +70 ˚C,VDD=3.0 V Ta=+25 ˚C, VDD=1.2 V to 5.5 V Ta=+25 ˚C, VDD=1.8 V Ta=+25 ˚C, VDD=3.0 V Max. 5±23 +10 -120 Unit × 10-6 ±2 3 ±5 × 10-6/V s External dimensions R8564 E 8476A 5.4 (Unit: mm) Aging × 10 /year -6 DC characteristics Item Power current (during access) Pin (VDD=1.8 to 5.5 V, Ta=-40 to +85˚C) Symbol IDD0 IDD Power current (not during access) — IDD32k “L” input voltage “H” input voltage “L” output voltage “L” output current “H” output current Leakage current SDA INT VIL VIH Min. Typ. Max. Unit Condition — 800 fSCL=400 kHz 200 fSCL=100 kHz 0.33 0.80 fSCL=0 Hz, VDD=5.0 V 0.275 0.70 fSCL=0 Hz, VDD=3.0 V fSCL=0 Hz, VDD=2.0 V — 0.25 0.65 µA 2.5 3.4 fSCL=0 Hz, VDD=5.0 V 1.5 2.2 fSCL=0 Hz, VDD=3.0 V 1.1 1.6 fSCL=0 Hz, VDD=2.0 V 0.3xVDD GND -0.5 V — VDD+0.5 0.7xVDD — — 1 1 0.9 0.9 1.1 1.0 µA V mA 6.0±0.2 1.5 Max. 7.0±0.3 1.3 0.65 0.22 (0.75) (0.75) Low voltage detection -3 IOL(SDA) IOL(INT) VOL=0.4 V, VDD=5 V -1 IOL(CLKOUT) CLKOUT — IOH(CLKOUT) ILO VO=VDD or GND -1 — Ta=-40 °C to +85 °C — VLOW Ta=-20 °C to +70 °C 69 Real time clock module Register table Address 0 1 2 3 4 5 6 7 8 9 A B C D E F Register symbol Control 1 Control 2 Sec Min Hour Day Week Month/Century Year Minutes Alarm Hours Alarm Day Alarm Week Alarm bit 7 TEST 0 VL ∗ ∗ ∗ ∗ C Year 80 AE AE AE AE FE TE 128 bit 6 0 0 S 40 Min 40 ∗ ∗ ∗ ∗ Year 40 A-Min 40 A-Hr 40 ∗ ∗ ∗ ∗ 64 bit 5 STOP 0 S 20 Min 20 Hour 20 Day 20 ∗ ∗ Year 20 A-Min 20 A-Hr 20 A-Day 20 ∗ ∗ ∗ 32 bit 4 0 TI/TP S 10 Min 10 Hour 10 Day 10 ∗ Month 10 Year 10 A-Min 10 A-Hr 10 A-Day 10 ∗ ∗ ∗ 16 bit 3 TEST AF S8 Min 8 Hour 8 Day 8 ∗ Month 8 Year 8 A-Min 8 A-Hr 8 A-Day 8 ∗ ∗ ∗ 8 bit 2 0 TF S4 Min 4 Hour 4 Day 4 W4 Month 4 Year 4 A-Min 4 A-Hr 4 A-Day 4 A-W 4 ∗ ∗ 4 bit 1 0 AIE S2 Min 2 Hour 2 Day 2 W2 Month 2 Year 2 A-Min 2 A-Hr 2 A-Day 2 A-W 2 FD1 TD1 2 bit 0 0 TIE S1 Min 1 Hour 1 Day 1 W1 Month 1 Year 1 A-Min 1 A-Hr 1 A-Day 1 A-W 1 FD0 TD0 1 CLKOUT frequency Timer control Timer 0 : Always set this bit to“0”. Switching characteristics Item SCL clock frequency Tolerance spike time on bus Start condition set-up time Start condition Hold time SCL “L” time SCL “H” time SCL and SDA rise time SCL and SDA fall time Date set-up time Date hold time Stop condition set-up time Symbol fSCL tSW tSU;STA (VDD=1.8 to 5.5 V, Ta=-40 ˚C to +85 ˚C) Timing chart Bit0 LSB (R/W) Min. Max. 400 50 Unit kHz ns Protocol Start Condition (s) tSU;STA Bit 7 MSB (A7) tLOW tHIGH Bit6 (A6) 1/fSCL ACK (A) Stop Condition (P) 0.6 tHD;STA tLOW tHIGH tr 0.3 tf tSU;DAT tHD;DAT tSU;STO 100 ns 0 4.0 µs 1.3 µs 0.6 SCL tr tBUF SDA tHD;STA tSU;DAT tHD;DAT tSU;STO tf Block diagram 32.768 kHz CRYSTAL OSC CLKOUT CLKOE INT Voltage Detector Divider Output Control Control Logic SCL SDA I C-BUS Interface Address Register POR 2 Control1 00 Control2 Seconds Minutes Hours Days Weekdays Month/Century Years Minutes Alarm Hour Alarm Day Alarm Weekday Alarm CLKOUT frequency Timer Control Timer 0F 70