SED1181DLA

SED1278 CMOS DOT MATRIX LCD CONTROLLER DRIVER s DESCRIPTION The SED1278 is a character LCD controller-driver, capable of driving displays as large as 2 lines of 8 characters (5 × 8 pixels), with minimum external components. The SED1278 has an internal CGROM consisting of 240 characters (5 × 7) plus the underline cursor, JIS, ASCII, and eight user-programmable characters in RAM. The SED1278 has 40 segment output and 16 common output built-in. Thus, one chip is capable of displaying up to 16 characters. The SED1278 can display one line of 48 characters using an SED1681F (80-bit output) as an expansion segment driver. The SED1278 is fabricated using a silicon gate CMOS technology process and features very low power dissipation. This makes the device suitable for handheld and portable applications. s FEATURES • Low-power CMOS technology • 40 segment output • 16 common output • Duty: 1/8 or 1/16 (set by command) • 4/8-bit CPU data interface, TTL compatible • Two frame AC drive wave form • CGROM: .................................... 240 characters • CGRAM: ........................................ 8 characters • Display data RAM: ... 80 × 8 bits (80 characters) expansion • Recommended64 output) segment driver: SED1181F ( LA • Built-in power on power-on reset • Built-in RC oscillator • Built-in LCD driver voltage-divider network • TTL compatible CPU interface Logic: 4.5V to 5.5V • Supply voltage ................... LCD: 3.5V to 5.5V • Package: QFP5-80 pins (F0A, F0B, F0C, F0D, F0G, F0H) Al pad (D0A, D0B, D0C, D0D, D0G, D0H) SED1681F (80 output) s SYSTEM BLOCK DIAGRAM 40 SEG DATA CPU CONTROL SED1278 16 COM 20 CHAR × 2 LINES 64 SEG XSCL, LP D0 SED1181 287 SED1278 s BLOCK DIAGRAM OSC1 OSC2 Instruction Decoder Address Counter ACC Cursor/ Brink Control Refresh Address Counter 7 7 8 E R/W RS I/O Control Instruction Register DB0 DB7 I/O Buffer Oscillation Circuit 8 XSCL LP FR M P X Data Register Timing Generator Display Data RAM DD RAM 80 Bytes Shift Register 16 Bits Common Driving Output Circuit M P X 8 COM1 COM16 SEG1 VDD VSS V1 V2 V3 V4 V5 8 Character Generator RAM (CG-RAM) 64 Bytes 5 M P 5 Character Generator RAM (CG-RAM) 5 x 10 x 240 Bits 5 X Segment Driving Output Circuit SEG40 Latch Circuit 40 Bits Parallel/Serial Data Converter Shift Register 40 Bits D0 s PIN CONFIGURATION SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG39 SEG40 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4 DB3 DB2 60 55 50 45 65 40 70 35 SED1278F 75 Index 30 80 1 5 10 15 20 25 DB1 DB0 E R/W RS DP FR VDD XSCL LP V5 V4 V3 V2 V1 OSC2 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 VSS OSC1 288 SED1278 s PIN DESCRIPTION Symbol RS R/W E DB0 to DB7 LP XSCL FR DO COM1 to COM16 No. of signals 1 1 1 8 1 1 1 1 16 Register select signal Read/write select signal Read/write execute signal Data bus Data latching pulse Data transfer clock LCD AC driving signal Serial data Common outputs COM9 to COM16 : non-select for 1/8 duty COM12 to COM16: non-select for 1/11 duty SEG1 to SEG40 V1 to V5 VDD VSS OSC1 OSC2 *1 40 5 1 1 2 RS 0 0 1 1 Segment outputs LCD driving power (V5≥VSS) +5V 0V (GND) Used to connect resistor (typ. 91KΩ) for oscillation; OSC1 is for external clock input. R/W 0 1 0 1 1 1 E Operation Instruction write cycle Busy flag read cycle Address counter read cycle DD RAM or CG RAM data write cycle DD RAM or CG RAM data read cycle *1 Functions s ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings • (VSS = 0V, Ta = 25°C) Symbol VDD V1 to V5 VI VO PD Topr Tstg Tsol Rating –0.3 to 7.0 –0.3 to VDD+0.3 –0.3 to VDD+0.3 –0.3 to VDD+0.3 300 –20 to 75 –65 to 150 260°C•10s (at lead) Unit V V V V mW °C °C — Parameter Supply voltage (1) Supply voltage (2) Input voltage Output voltage Power dissipation Operating temperature Storage temperature Soldering temperature and time Note: The following condition must always hold true: VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 289 SED1278 • DC Characteristics Parameter “H” level input voltage (1) “L” level input voltage (1) “H” level input voltage (2) “L” level input voltage (2) “H” level output voltage (1) “L” level output voltage (1) “H” level output voltage (2) “L” level output voltage (2) Driver-on resistor (COM) Driver-on resistor (SEG) I/O leakage current Pull-up MOS current Supply current External clock operation External clock operating frequency (VDD = 5.0V ±10%, VSS = 0V, Ta = –20 to 75°C) Symbol VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 RCOM RSEG IIL –IP Iop fEXTCL Duty trEXTCL tfEXTCL fOSC fOSC VLCD Rf=91kΩ± 2% Ceramic filter VDD–V5 IOH=–0.205mA IOL=1.6mA IOH=–0.04mA IOL=0.04mA |VCOM–Vn|=0.5V |VSEG–Vn|=0.5V VI=0 to VDD VDD=5V Rf oscillation, from external clock VDD=5V, fOSC=fCP=270kHz Condition Applicable Pin DB0~DB7 RS, R/W, E OSC1 DB0~DB7 XSCL LP D0 COM1~16 SEG1~40 Min 2.0 VSS VDD–1.0 VSS 2.4 — 0.9VDD — — — — 50 Typ — — — — — — — — 2 2.5 — 125 0.5 250 50 — — 270 250 — Max VDD 0.8 VDD 1.0 — 0.4 — 0.1VDD 10 10 1 250 0.8 350 55 0.2 0.2 350 255 VDD Unit V V V V V V V V kΩ kΩ µA µA mA kHz % µs µs kHz kHz V VDD — 125 45 — — 190 245 3.0 External clock duty External clock rise time External clock fall time Oscillation frequency Oscillation frequency LCD driving voltage Internal clock operation (Rf oscillation) Internal clock operation (Ceramic filter oscillation) • ° AC Characteristics Read cycle Parameter Enable cycle time Enable “H” level pulse width Enable rise/fall time RS, R/W setup time RS, R/W address hold time Read data output delay Read data hold time Symbol tcycE tWEH trE, tfE tAS tAH tRD tDHR (VDD = 5.0V ± 10%, VSS = 0V, Ta = –20 to 75°C) Conditions Min 500 220 — 40 10 CL=100pF — 20 Typ — — — — — — — Max — — 25 — — 120 — Unit ns ns ns ns ns ns ns 290 SED1278 ° Write cycle Parameter Enable cycle time Enable “H” level pulse width Enable rise/fall time RS, R/W setup time RS, R/W address hold time Data setup time Write data hold time Symbol tcycE tWEH trE, tfE tAS tAH tDS tDH (VDD = 5.0V±10%, VSS = 0V, Ta = –20 to 75°C) Conditions Min 500 220 — 40 10 60 10 Typ — — — — — — — Max — — 25 — — — — Unit ns ns ns ns ns ns ns • ° Timing Chart Read cycle RS VIH1 VIL1 VIH1 VIL1 tAS tAH VIH1 R/W VIH1 tWEH tAH VIH1 E VIL1 VIH1 tfE VIL1 VIL1 trE tRD VOH1 VOL1 tDHR Significant Data VOH1 VOL1 DB0 to DB7 tcycE ° Write cycle RS VIH1 VIL1 VIH1 VIL1 tAS tAH VIL1 R/W VIL1 tWEH tAH VIH1 E VIL1 VIH1 tfE VIL1 VIL1 trE tDS VIH1 VIL1 tDH VIH1 VIL1 DB0 to DB7 Significant Data tcycE 291 SED1278 s DISPLAY COMMAND Parameter CLEAR DISPLAY CURSOR HOME ENTRY MODE SET DISPLAY ON/OFF CURSOR/DISPLAY SHIFT RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 D 0 1 I/D C * 1 * S B * Note DB1=1 : Increment, DB1=0 : Decrement DB0=1 : The display is shifted. DB0=0 : The display is not shifted. DB2=1 : Display on DB2=0 : Display off DB1=1 : Cursor on DB0=1 : Brinking on DB1=0 : Cursor off DB0=0 : Brinking off S/C R/L DB3=1 : Shifts display one character DB2=1 : Right shift, DB2=0 : Left shift DB4=1 : 8 bits, DB4=0 : 4 bits DB3=1 : 2 lines display (1/16 duty), SYSTEM SET 0 0 0 0 1 DL N F * * DB3=0 : 1 line display DB2=1 : 5x10 dots, 1/11 duty ( DB2=0 : 5x7dots, 1/8 duty ) SET CGRAM ADDRESS 0 SET DDRAM ADDRESS 0 READ BUSY FLAG/ ADDRESS COUNTER 0 WRITE DATA 1 READ DATA * Don’t care 0 0 1 0 1 0 1 BF 1 ACG ADD AC Write Data Read Data The address length that can be set is 64 addresses. The address length that can be set is 80 addresses. DB7=1 : Busy (instruction not accepted) DB7=0 : Ready (instruction accepted) 1 292 SED1278 s EXAMPLE OF APPLICATION (2 lines × 20 characters) SED1278 LCD COM1 16 COM16 16 × 100 Dots SEG1 SEG40 40 60 D0 SEG0 D0 SEG59 DO1 D1 DO0 OPEN SED1181FLA/DLA LP XSCL FR VDD VSS V2 V3 VSSH LP XSCL FR VDD VSS V2 V3 V5 OSC1 OSC2 Rf SED1278 is usually connected to 8-bit MPU via I/O ports. 293 SED1278 s PAD LAYOUT 4,500 ••••••••••••••• Y X ••••••••••••••• 1 25 • • • • • • • • • • • • • • • • • • • • •80 • • 24 (0,0) 3,670 •••••••• •••••••• Monitor Pad 40 • • • • • • • • • • • • • • • • • • • • •65 • • 41 64 Pad size: 109 × 109 294 SED1278 • PAD COORDINATES Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad Name SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1 OSC2 V1 V2 V3 V4 V5 LP XSCL VCC FR DO RS R/W E DB0 DB1 X 2087 1905 1723 1541 1359 1177 995 814 633 452 272 91 –91 –272 –452 –633 –814 –995 –1177 –1359 –1541 –1723 –1905 –2087 –2087 –2087 –2087 –2087 –2087 –2087 –2087 –2087 –2087 –2087 –2087 –2087 –2087 –2087 –2087 –2087 Y 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1365 1183 1001 819 637 455 273 91 –91 –273 –455 –637 –819 –1001 –1183 –1365 Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pad Name DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 X –2087 –1905 –1723 –1541 –1359 –1177 –995 –814 –633 –452 –272 –91 91 272 452 633 814 995 1177 1359 1541 1723 1905 2087 2087 2087 2087 2087 2087 2087 2087 2087 2087 2087 2087 2087 2087 2087 2087 2087 Y –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1671 –1365 –1183 –1001 –819 –637 –455 –273 –91 91 273 455 637 819 1001 1183 1365 295 SED1278 s SED1278F0A/D0A CHARACTER FONT 0 CG 0 RAM (1) CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) CG 4 RAM (5) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 1 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9A B C D E F CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) 296 SED1278 s SED1278F0B/D0B CHARACTER FONT 0 CG 0 RAM (1) CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) CG 4 RAM (5) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 1 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9A B C D E F CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) 297 SED1278 s SED1278F0C/D0C CHARACTER FONT 0 CG 0 RAM (1) CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) CG 4 RAM (5) 1 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9A B C D E F Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) 298 SED1278 s SED1278F0D/D0D CHARACTER FONT 0 CG 0 RAM (1) CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) CG 4 RAM (5) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 1 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9A B C D E F CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) 299 SED1278 s SED1278F0G/D0G CHARACTER FONT 0 CG 0 RAM (1) CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) CG 4 RAM (5) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 1 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9A B C D E F CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) 300 SED1278 s SED1278F0H/D0H CHARACTER FONT Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9A B C D 0 CG 0 RAM (1) CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) CG 4 RAM (5) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 1 2 E F CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) * Character codes (00H-0FH) of SED1278F are assigned to the area of character generator RAM (CG RAM). The CG ROM of the SED1278F is masked; if you wish to have your own CG ROM, consult S-MOS Marketing Department for conversion of the masked ROM. 301 THIS PAGE INTENTIONALLY BLANK 302