SED1330

SED1330 CMOS GRAPHIC LCD CONTROLLER This part is replaced by SED1335. Some pin differences between SED1330 and SED1335 exist. Please check SED1335 data sheet. S-MOS Systems, Inc., will continue to support existing designs which use SED1330. s DESCRIPTION The SED1330 is a CMOS low-power dot matrix liquid crystal graphic display controller. The device stores in external RAM display data sent by an 8-bit microcomputer, and generates all the signals required by the LCD drivers. The LSI incorporates an internal character generator ROM which supports user-defined characters (also an external CGROM can be supported). The SED1330 can be interfaced to high-speed microprocessors such as the Intel family or Motorola family. The controller supports a set of rich commands that will allow the user to create a layered display of characters and graphics. Also, the controller functions as a pipeline buffer between the MPU and display memory so that low-cost, medium-speed SRAM can be used. s FEATURES • CMOS low-power graphic and character display controller interface is compatible • Selectable MPUand the Motorola family with both the Intel family • Smooth scrolling support: • • Horizontal and vertical scroll Scrolling of selected areas of the display Multimode display: 2 layers of overlapping character and graphics 3 layers of overlapping graphics Selectable display synthesis: Inverse video Flashing display, cursor on/off/blink Under and bar cursor, block cursor Simple animation • Programmable cursor • Internal character generator ROM • Supports external character generator ROM: • • • • • 8 × 8 or 8 × 16 pixel characters Allows mixing of ROM and RAM character sets Supports 64K bytes of memory: 2 of 32K × 8 100ns SRAM or 8 of 8K × 8 100ns SRAM Display duty .................................. 1/2 to 1/256 Low power dissipation ................ 5mA (typical) 0.05µA (typical), standby Logic power supply ........................ 4.5 to 5.5V Package ................ Plastic QFP5-60 pin (FBA) Plastic QFP6-60 pin (FBB) s SYSTEM BLOCK DIAGRAM DATA CPU 68xx 80xx CONTROL SED1330F LCD SRAM 125 SED1330 s BLOCK DIAGRAM Video RAM CG RAM VA0 to VA15 External CG ROM VD0 to VD7 YSCL,YDIS LCD XSCL, XECL XD0 to XD3 XD3 D7 D6 D5 D4 D3 D2 D1 D0 VDD A0 CS XD XG SEL1 VCE VRAM Interface VR/W I/O Register LCD Controller Cursor Address Controller Display Address Controller Refresh Address Counter Dot Counter CG ROM MPU Interface LP, WF Layered Display Controller OSC A0, CS D0 to D7 RD, WR SEL1 SEL0 RES XD s PINOUT XG SEL1 SEL2 WR RD NC NC RES NC VCE VR/W VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 XD CS A0 VDD D0 D1 D2 D3 D4 D5 D6 55 50 45 40 60 1 5 SED1330FBA Index 30 29 VA8 VA9 VA10 VA11 VA12 VA13 NC VA14 VA15 VD0 VD1 VD2 6 10 15 20 VD3 VD2 VD1 VD0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 NC 45 46 60 1 D7 XD3 XD2 XD1 XD0 XECL XSCL VSS LP WF YDIS YD YSCL VD7 VD6 VD5 VD4 VD3 126 VA5 VA4 VA3 VA2 VA1 VA0 VR/W VCE NC RES NC NC RD WR SEL2 VD4 VD5 VD6 VD7 YSCL YD YDIS WF LP VSS XSCL XECL XD0 XD1 XD2 31 30 SED1330FBB Index 16 15 XG SED1330 s PIN DESCRIPTIONS Pin Name XG XD VDD VSS SEL1, 2 D0 to D7 A0 RD WR CS RES VA0 to VA15 VD0 to VD7 VR/W VCE XD0 to XD3 XSCL XECL LP WF YSCL YD YDIS Pin No. SED1330FBA 54 55 58 13 53 • 52 59 to 60 1 to 6 57 50 51 56 47 43 to 30 28 to 27 26 to 19 44 45 10 to 7 12 11 14 15 18 17 16 SED1330FBB 17 18 21 36 16 • 15 22 to 29 20 13 14 19 10 6 to 1 59 to 50 49 to 42 7 8 33 to 30 35 34 37 38 41 40 39 I/O I O +5V GND (0V) I I/O I I I I I O I/O O O O O O O O O O O Functions Oscillator terminal Oscillator terminal Power supply Power supply MPU interface format selection Data bus Data type selection 80 series Read strobe signal 68 series “E” clock 80 series Write strobe signal 68 series R/W signal Chip select Reset VRAM address bus VRAM data bus VRAM R/W signal Memory control signal Dot data output bus to X driver Dot data shift clock for X driver Chip enable shift clock for Y driver Dot data latch pulse Frame signal Scan data shift clock for Y driver Scan data output Power down signal when display OFF NC: No Connection s ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings • (VSS = 0V) Symbol VDD VI PD Topr Tstg Tsol Ratings –0.3 to 7.0 –0.5 to VDD+0.5 300 –20 to 75 –60 to 150 260°C, 10s (at lead) Unit V V mW °C °C — Parameter Supply voltage Input voltage Power dissipation Operating temperature Storage temperature Soldering temperature and time 127 SED1330 • DC ELECTRICAL CHARACTERISTICS Parameter Operating voltage Register data retention voltage High level input voltage Low level input voltage High level output voltage Low level output voltage High level input voltage Low level input voltage High level output voltage Low level output voltage Positive trigger threshold voltage Negative trigger threshold voltage Symbol VDD VOH VIHT VILT VOHT VOLT VIHC VILC VOHC VOLC VT+ VT– ILI ILO IDDA IDDS fOSC fCLK Rf (VDD = 5V±10%, VSS = 0V, Ta = –20 to 75°C) Condition Min 4.5 2.0 D0 to D7, A0, CS, RD, WR, VD0 to VD7, IOH= –5.0mA, IOL=5.0mA, VR/W, VCE, REF IOH=1.6mA, IOL= –1.6mA, SEL1, 2, SYNC, YD, XD0 to YSCL, YDIS, OSC1, OSC2 RES * VI=VDD or VSS fOSC=10MHz, No load (No external V-RAM) XG=CS=VDD Typ 5.0 — — — — — — — — — Max 5.5 6.0 VDD+0.3 0.8 — 0.4 — 0.2VDD — 0.4 Unit V V V V V V V V V V V V µA µA mA µA MHz MHz MΩ T T L C M O S SCHMITT 2.2 –0.3 2.4 — 0.8VDD — — XD3, XSCL, XECL, LP, FR, VDD–0.4 0.5VDD 0.7VDD 0.8VDD 0.2VDD 0.3VDD 0.5VDD — — — — 1.0 — 0.5 0.05 0.10 8 0.05 — — 1.0 2.0 5.0 12 20 10.0 10.0 5.0 Input leakage current Output leakage current Average operating current Standby current Oscillation frequency External clock frequency Feed back resistance AT X’tal XG, XD * RES input pulse should be longer than 1.0ms. VL5 should be OFF when RES is “L”. 128 SED1330 • ° AC CHARACTERISTICS System Bus READ/WRITE Timing I (8080) tAH8 A0, CS tAW8 tCYC tCC tDS8 WR, RD tDH8 D0~D7 (WRITE) tACC8 tOH8 D0~D7 (READ) Signal A0, CS WR, RD Parameter Address hold time Address setup time System cycle time Control pulse width Data setup time Data hold time RD access time Output disable time Symbol tAH8 tAW8 tCYC tCC tDS8 tDH8 tACC8 tOH8 D0 to D7 Rating Min Max 10 — 30 — *1 — 220 — 120 — 10 — — 120 10 50 Unit ns ns ns ns ns ns ns ns Remark CL = 100 pF + 1TTL *1. tCYC = 2tc + tCC + tCEA + 75 > tACV + 245 ................ Memory control/movement control commands. = 4tC + tCC + 30 .............................................. All other commands. 129 SED1330 ° System Bus READ/WRITE Timing II (6800) tCYC6 E tAW6 tEW R/W tAH6 A0, CS tDS6 tDH6 D0~D7 (WRITE) tACC6 tOH6 D0~D7 (READ) Signal Parameter System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time Access time Enable pulse width Symbol tCYC6*1 tAW6 tAH6 tDS6 tDH6 tOH6 tACC6 tEW A0, CS, R/W D0 to D7 E Rating Min Max *2 — 30 — 10 — 120 — 10 — 10 50 — 120 220 — Unit ns ns ns ns ns ns ns ns Remark CL = 100 pF + 1 TTL *1. tCYC6 means a cycle of (CS.E) not E alone. *2. tCYC6 = 2tc + tEW + tCEA + 75 > tACV + 245 .............. Memory control/movement control commands. = 4tC + tEW + 30 ............................................ All other commands. 130 SED1330 ° Display Memory READ Timing tC EXTφO tW tCE tW VCE tCYR VA0~VA15 tASC tAHC tRCS tCEA tACY tRCH tCE3 tOH2 VR/W VD0~VD7 Signal EXT φ0 VCE Parameter Clock cycle VCE high-level pulse width VCE low-level pulse width Read cycle time VCE address setup time (fall) VCE address hold time (fall) VCE read cycle setup time (fall) VCE read cycle hold time (fall) Address access time VCE access time Output data hold time VCE data off time Symbol tC tW tCE tCYR tASC tAHC tRCS tRCH tACV tCEA tOH2 tCE3 VA0 to VA15 VR/W VD0 to VD7 Rating Min Max 100 — tC – 40 — 2tC – 40 — *1 — tC – 45 — 2tC – 40 — tC – 45 — tC/2 – 35 — — *2 — *3 0 — 0 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Remark CL = 100 pF + 1TTL *1. tCYR = 3tC *2. tACV = 3tC – 120 *3. tCEA = 2tC – 120 131 SED1330 ° Display Memory WRITE Timing tC EXTφO tW tCE VCE tASC tAHC tCA VA0~VA15 tCYW tAS tWSC tWHC tAH2 VR/W tOSC tOH2 tOHC VD0~VD7 Signal EXT φ0 VCE Parameter Clock cycle VCE HIGH-level pulse width VCE LOW-level pulse width Write cycle time VCE address hold time (fall) VCE address setup time (fall) VCE address hold time (rise) VR/W address setup time (fall) VR/W address hold time (rise) VCE write setup time (fall) VCE write hold time (fall) VCE data input setup time (fall) VCE data input hold time (fall) VR/W data hold time (rise) Symbol tC tW tCE tCYW tAHC tASC tCA tAS tAH2 tWSC tWHC tDSC tDHC tDH2 VA0 to VA15 VR/W Rating Min Max 100 — tC – 40 — 2tC – 40 — 3tC — 2tC – 40 — tC – 55 — 5 — 0 — 15 — tC – 55 — 2tC – 40 tWSC – 10 2tC – 30 10* — — — 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remark CL = 100 pF + 1TTL VD0 to VD7 * Lines VD0 to VD7 are latched. 132 SED1330 ° LCD Control Timing ROW NO LP YD WF YSCL 1 frame period WF YSCL ROW64 1 line period ROW1 ROW2 LP XSCL XD0~XD3 XECL tr tWX tf tCX XSCL XD0~XD3 tDS tDH tWL tL1 tS2 tL2 tS1 LP XECL WF(B) YD tWXE tDf YSCL tLD tDHY tWY 133 SED1330 Signal EXT φ0 Parameter Clock cycle Rising time Falling time Shift clock cycle time XSCL clock pulse width X-data hold time X-data setup time Latch data setup time LP signal pulse width XECL setup time XECL data hold time Enable setup time Enable delay time XECL clock pulse width Time allowance of WF delay LP delay time against YSCL YSCL clock pulse width Y-data hold time Symbol tC tr tf tCX tWX tDH tDS tLS tWL tL1 tL2 tS1 tS1 tWXE tDF tLD tWY tDHY Rating Min 100 — — 4tC tCX2 – 80 tCX2 – 100 tCX2 – 100 tCX2 – 100 tCX4 – 80 tCX3 – 100 tC – 30 tC – 30 tC – 30 tCX3 – 80 — tCX4 – 100 tCX4 – 80 tCX6 – 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remark XSCL XD0 to XD3 LP XECL WF YSCL YD Max — 35 35 — — — — — — — — — — — 100 — — — VDD = 5.0V ± 10% CL = 150F 134 SED1330 ° Oscillator Timing VDD tOSP CLO tOSS YDIS Power ON Sleep period tRCL tFCL EXT 0O tWL tCL tWH Signal Parameter Time to stable CLO output after power-ON Time to stable CLO after sleep OFF External clock rise time External clock fall time External clock high-pulse width External clock low-pulse width External clock cycle Symbol tOSP tOSS tRCL tFCL tWH tWL tCL Min — — Rating Max 3 1 15 15 *2 *2 — Unit ms ms ns ns ns ns ns Remark CLO RES = H 20 pF EXT φ0 — — *1 *1 100 *1. (tC – tRCL – tFCL) × 475/1000 < tWH, tWL *2. (tC – tRCL – tFCL) × 525/1000 > tWH, tWL 135 SED1330 s EXAMPLE OF APPLICATION 8.0MHz XG A0 A1 to A7 MPU XD HC138 G1 A0 VA13 to VA15 VR/W VA0 to VA12 A B C Y7 Y6 CS7 CS6 Y0 CS0 Chip Selector CS SED1330F IORQ VA12 A0 to A12 WE SRM2064 CS1 (RAM1) CS2 D0 to D7 OE A0 to A12 WE SRM2064 CS1 (RAM7) CS2 D0 to D7 OE A0 to A11 2732 (EXT.CG) D0 to D7 OE D0 to D7 RD WR RESET RESET D0 to D7 RD WR RES XD0 to XD3 CE VD0 to VD7 XECL XSCL LP WF YDIS YD YSCL YSCL DI YDIS FR LAF SPU SCI7661 Poff X2 SED1190F LCD VL1 VL2 VL3 VL4 VL5 (Y Driver) FR EI SED1180F LP XSCL ECL D0 to D3 LP XSCL ECL D0 to D3 Vreg (X Driver) 136 LP XSCL ECL D0 to D3 FR EI SED1180F FR EI SED1180F SED1330 s CHARACTER CODE TABLE (BUILT-IN CHARACTER GENERATOR) 0 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 1 2 Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 3 4 5 6 7 8 9A B C D E F 3 4 5 6 7 A B C D 1 Note: 321 321 321 321 means all dots of 6 × 8 matrix are on. 137 THIS PAGE INTENTIONALLY BLANK 138