SI5318

Si5318 SONET/SDH P R E C I S I O N C L O C K M U L T I P L I E R I C Features Jitter generation as low as 0.7 psRMS (typ), compliant with GR-253-CORE OC-48 specifications No external components (other than a resistor and standard bypassing) Input clock ranges at 19, 39, 78, and 155 MHz Output clock ranges at 19 or 155 MHz Digital hold for loss of input clock Selectable loop bandwidth Loss-of-signal alarm output Low power Small size (9x9 mm) Si5318 Si5318 Applications SONET/SDH line/port cards Optical modules Core switches Digital cross connects Terabit routers Ordering Information: See page 26. Description The Si5318 is a precision clock multiplier designed to exceed the requirements of high-speed communication systems, including OC-48. The device phase locks to an input clock in the 19, 39, 78, or 155 MHz frequency range and generates a low jitter output clock in the 19 or 155 MHz range. Silicon Laboratories’ DSPLL® technology delivers all PLL functionality with unparalleled performance while eliminating external loop filter components, providing programmable loop parameters, and simplifying design. The Si5318 establishes a new standard in performance and integration for ultra-low-jitter clock generation. It operates from a single 3.3 V supply. Functional Block Diagram REXT VDD GND Biasing & Supply Regulation FXDDELAY CLKIN+ CLKIN– VALTIME LOS 2 CAL_ACTV ÷ Signal Detect 3 DSPLL ® DH_ACTV ÷ Calibration 2 CLKOUT+ CLKOUT– FRQSEL[1:0] RSTN/CAL 2 INFRQSEL[2:0] BWSEL[1:0] DBLBW Rev. 1.0 4/05 Copyright © 2005 by Silicon Laboratories Si5318 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5318 NOTES: 2 Rev. 1.0 S i5318 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1. DSPLL® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.6. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3. Pin Descriptions: Si5318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Rev. 1.0 3 S i5318 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Si5318 Supply Voltage3 Symbol TA VDD33 Test Condition Min1 –202 3.135 Typ 25 3.3 Max1 85 3.465 Unit °C V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5318 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient temperature of –20 to 85° C. 3. The Si5318 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 13. 4 Rev. 1.0 S i5318 CLKIN+ CLKIN– VIS A. Operation with Single-Ended Clock Input Note: When using single-ended clock sources, the unused clock input on the Si5318 must be ac-coupled to ground. CLKIN+ CLKIN– 0.5 VID (CLKIN+) – (CLKIN–) VID B. Operation with Differential Clock Input Note: Transmission line termination, when required, must be provided externally . Figure 1. CLKIN Voltage Characteristics 80% 20% tF tR Figure 2. Rise/Fall Time Measurement (C L K IN + ) – (C L K IN – ) 0V tLOS Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition Rev. 1.0 5 S i5318 Table 2. DC Characteristics, VDD = 3.3 V (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Supply Current Power Dissipation Using 3.3 V Supply Common Mode Input Voltage (CLKIN) 1,2,3 IDD PD VICM VIS VID RIN VOD VOCM ISC(–) ISC(+) VIL VIH IIL IIH Ipd RIN VOL VOH Clock in = 19.44 MHz Clock out = 155.52 MHz Clock in = 19.44 MHz Clock out = 155.52 MHz — — 1.0 135 445 1.5 — — 80 938 1.8 — 15 — — — — — — — — 145 479 2.0 5004 5004 — 1155 2.2 — — 0.8 — 50 50 50 — 0.4 — mA mW V mVPP mVPP kΩ mVPP V mA mA V V µA µA µA kΩ V V Single-Ended Input Voltage2,3,4 (CLKIN) Differential Input Voltage Swing2,3,4 (CLKIN) Input Impedance (CLKIN+, CLKIN–) Differential Output Voltage Swing (CLKOUT) Output Common Mode Voltage (CLKOUT) Output Short to GND (CLKOUT) Output Short to VDD25 (CLKOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Internal Pulldowns (All LVTTL Inputs) Input Impedance (LVTTL Inputs) Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) Notes: See Figure 1A See Figure 1B 200 200 — 100 Ω Load Line-to-Line 100 Ω Load Line-to-Line 720 1.4 –60 — — 2.0 — — — 50 IO = .5 mA IO = .5 mA — 2.0 1. The Si5318 device provides weak 1.5 V internal biasing that enables ac-coupled operation. 2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac coupled to ground. 3. Transmission line termination, when required, must be provided externally. 4. Although the Si5318 device can operate with input clock swings as high as 1500 mVPP, Silicon Laboratories recommends maintaining the input clock amplitude below 500 mVPP for optimal performance. 6 Rev. 1.0 S i5318 Table 3. AC Characteristics (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Input Clock Frequency (CLKIN) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 Input Clock Rise Time (CLKIN) Input Clock Fall Time (CLKIN) Input Clock Duty Cycle CLKOUT Frequency Range* FRQSEL[1:0] = 00 (no output) FRQSEL[1:0] = 01 FRQSEL[1:0] = 10 CLKOUT Rise Time CLKOUT Fall Time CLKOUT Duty Cycle RSTN/CAL Pulse Width Transitionless Period Required on CLKIN for Detecting a LOS Condition. INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 Recovery Time for Clearing an LOS Condition VALTIME = 0 VALTIME = 1 fCLKIN 19.436 38.872 77.744 155.48 Figure 2 Figure 2 — — 40 — 19.436 155.48 Figure 2; single-ended; after 3 cm of 50 Ω FR4 stripline Figure 2; single-ended; after 3 cm of 50 Ω FR4 stripline Differential: (CLKOUT+) – (CLKOUT–) Figure 3 — — 48 20 — — — — — — 50 — — — 213 191 — — 21.685 43.369 86.738 173.48 11 11 60 — 21.685 173.48 260 260 52 — MHz tR tF CDUTY_IN ns ns % fO_19 fO_155 tR tF CDUTY_O UT MHz ps ps % ns tRSTN tLOS /fo_155 3 /fo_155 5/ 2 x fo_155 9 /4 x fo_155 9 /4 x fo_155 tVAL Measured from when a valid reference clock is applied until the LOS flag clears 4 6/ fo_155 — — — — — — 8 /fo_155 8 /fo_155 8/ fo_155 8 /fo_155 8 /fo_155 8/ fo_155 s 0.09 12.0 — — 0.22 14.1 s *Note: The Si5318 provides a 1/8, 1/4, 1/2, 1, 2, 4 or 8x clock frequency multiplication function. Rev. 1.0 7 S i5318 Table 4. AC Characteristics (PLL Performance Characteristics) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Wander/Jitter at 800 Hz Bandwidth (BWSEL[1:0] = 10 and DBLBW = 0) Symbol Test Condition Min Typ Max Unit Jitter Tolerance (see Figure 7) JTOL(PP) f = 8 Hz f = 80 Hz f = 800 Hz 1000 100 10 — — — — — — — 0.87 7.3 800 0.0 — — — 1.2 10.0 — 0.05 ns ns ns ps ps Hz dB CLKOUT RMS Jitter Generation CLKOUT Peak-Peak Jitter Generation Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 1600 Hz Bandwidth (BWSEL[1:0] = 10 and DBLBW = 1) JGEN(RMS) JGEN(PP) FBW JP 12 kHz to 20 MHz 12 kHz to 20 MHz BW = 800 Hz < 800 Hz Jitter Tolerance (see Figure 7) f = 16 Hz f = 160 Hz f = 1600 Hz 500 50 5 — — — — — — — 0.78 7.0 1600 0.00 — — — 1.2 9.0 — 0.05 ns ns ns ps ps Hz dB CLKOUT RMS Jitter Generation CLKOUT Peak-Peak Jitter Generation Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 1600 Hz Bandwidth (BWSEL[1:0] = 01 and DBLBW = 0) JGEN(RMS) JGEN(PP) FBW JP 12 kHz to 20 MHz 12 kHz to 20 MHz BW = 1600 Hz < 1600 Hz Jitter Tolerance (see Figure 7) JTOL(PP) f = 16 Hz f = 160 Hz f = 1600 Hz 1000 100 10 — — — — — — — 0.82 7.3 1600 0.0 — — — 1.0 10.0 — 0.1 ns ns ns ps ps Hz dB CLKOUT RMS Jitter Generation CLKOUT Peak-Peak Jitter Generation Jitter Transfer Bandwidth (see Figure 10) Wander/Jitter Transfer Peaking JGEN(RMS) JGEN(PP) FBW JP 12 kHz to 20 MHz 12 kHz to 20 MHz BW = 1600 Hz < 1600 Hz Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5318 (tPT_MTIE) never reaches one nanosecond. 8 Rev. 1.0 S i5318 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Wander/Jitter at 3200 Hz Bandwidth (BWSEL[1:0] = 01 and DBLBW = 1) Symbol Test Condition Min Typ Max Unit Jitter Tolerance (see Figure 7) f = 32 Hz f = 320 Hz f = 3200 Hz 500 50 5 — — — — — — — 0.72 6.8 3200 0.05 — — — 0.9 10.0 — 0.1 ns ns ns ps ps Hz dB CLKOUT RMS Jitter Generation CLKOUT Peak-Peak Jitter Generation Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 3200 Hz Bandwidth (BWSEL[1:0] = 00 and DBLBW = 0) JGEN(RMS) JGEN(PP) FBW JP 12 kHz to 20 MHz 12 kHz to 20 MHz BW = 3200 Hz < 3200 Hz Jitter Tolerance (see Figure 7) JTOL(PP) f = 32 Hz f = 320 Hz f = 3200 Hz 1000 100 10 — — — — — — — 0.86 7.7 3200 0.05 — — — 1.2 10.0 — 0.1 ns ns ns ps ps Hz dB CLKOUT RMS Jitter Generation CLKOUT Peak-Peak Jitter Generation Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 6400 Hz Bandwidth (BWSEL[1:0] = 00 and DBLBW = 1) JGEN(RMS) JGEN(PP) FBW JP 12 kHz to 20 MHz 12 kHz to 20 MHz BW = 3200 Hz < 3200 Hz Jitter Tolerance (see Figure 7) f = 64 Hz f = 640 Hz f = 6400 Hz 500 50 5 — — — — — — — 0.7 6.6 6400 0.05 — — — 1.0 9.0 — 0.1 ns ns ns ps ps Hz dB CLKOUT RMS Jitter Generation CLKOUT Peak-Peak Jitter Generation Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking JGEN(RMS) JGEN(PP) FBW JP 12 kHz to 20 MHz 12 kHz to 20 MHz BW = 6400 Hz < 6400 Hz Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5318 (tPT_MTIE) never reaches one nanosecond. Rev. 1.0 9 S i5318 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Wander/Jitter at 6400 Hz Bandwidth (BWSEL[1:0] = 11 and DBLBW = 0) Symbol Test Condition Min Typ Max Unit Jitter Tolerance (see Figure 7) JTOL(PP) f = 64 Hz f = 640 Hz f = 6400 Hz 1000 100 10 — — — — — — — 1.0 9.4 6400 0.05 — — — 1.4 12.0 — 0.1 ns ns ns ps ps Hz dB CLKOUT RMS Jitter Generation CLKOUT Peak-Peak Jitter Generation Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 12800 Hz Bandwidth (BWSEL[1:0] = 11 and DBLBW = 1) JGEN(RMS) JGEN(PP) FBW JP 12 kHz to 20 MHz 12 kHz to 20 MHz BW = 6400 Hz < 6400 Hz Jitter Tolerance (see Figure 7) f = 128 Hz f = 1280 Hz f = 12800 Hz 500 50 5 — — — — — — — — 0.74 6.9 12800 0.05 300 — — — 1.0 9.0 — 0.1 350 ns ns ns ps ps Hz dB ms CLKOUT RMS Jitter Generation CLKOUT Peak-Peak Jitter Generation Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Acquisition Time JGEN(RMS) JGEN(PP) FBW JP TAQ 12 kHz to 20 MHz 12 kHz to 20 MHz BW = 12800 Hz < 12800 Hz RSTN/CAL high to CAL_ACTV low, with valid clock input and VALTIME = 0 Stable Input Clock; Temperature Gradient