SII161A

SiI 161A PanelLink® Receiver Datasheet General Description The SiI 161A receiver uses PanelLink Digital technology to support high resolution displays up to UXGA. The SiI 161A receiver supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode. In addition, the receiver data output is time staggered to reduce ground bounce that affects EMI. Since all PanelLink products are designed on scaleable CMOS architecture to support future performance requirements while maintaining the same logical interface, system designers can be assured that the interface will be fixed through a number of technology and performance generations. PanelLink Digital technology simplifies PC and display interface design by resolving many of the system level issues associated with high-speed mixed signal design, providing the system designer with a digital interface solution that is quicker to market and lower in cost. March 2001 Features • • • • • § Low Power: 3.3V core operation Time staggered data output for reduced ground bounce Sync Detect: for Plug & Display “Hot Plugging” Cable Distance Support: over 5m with twisted-pair, fiber-optics ready Compliant with DVI 1.0 (DVI is backwards compatible with VESA ® P&DT M and DFP) Supports Dual-Link operation up to 330 Megapixels/second CONTROLS HSYNC VSYNC OGND OUTPUT CLOCK SiI 161A Pin Diagram GPO OVCC QE23 CTL3 CTL2 CTL1 GND VCC EVEN 8-bits RED OGND OVCC QE22 QE21 QE20 QE19 QE18 QE17 QE16 QE15 QE14 ODCK QO1 QO0 DE ODD 8-bits BLUE QO2 QO3 QO4 QO5 QO6 QO7 OVCC OGND QO8 QO9 QO10 QO11 QO12 QO13 QO14 QO15 VCC GND QO16 QO17 QO18 QO19 QO20 QO21 QO22 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 100 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 QE13 QE12 QE11 QE10 QE9 QE8 OGND OVCC QE7 QE6 QE5 QE4 QE3 QE2 QE1 QE0 PDO SCDT VCC GND SiI 161A 100-Pin TQFP (Top View) STAG_OUT/SYNC ODD 8-bits RED PIXS/M_S ST PD S _D DIFFERENTIALS IGNAL PLL Silicon Image, Inc. Subject to Change without Notice RESERVED OCK_INV EXT_RES CONFIG. PINS OGND AGND AGND AGND AGND AGND OVCC AVCC AVCC AVCC AVCC PGND QO23 RX2+ RX1+ RX0+ RX2- RX1- RX0- PVCC RXC+ RXC- EVEN 8-bits BLUE PWR MANAGEMENT ODD 8-bits GREEN EVEN 8-bits GREEN 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Silicon Image, Inc. Functional Block Diagram PIXS DF0 OCK_INV EXT_RES Termination Control Data Recovery SYNC2 CH2 Data Recovery SYNC1 CH1 Data Recovery SYNC0 CH0 SiI 161A SiI-DS-0009-D RX2+ RX2RX1+ RX1RX0+ RX0RXC+ RXCPDO STAG_OUT ST VCR SYNC2 DATA C TL3 CTL2 DATA Decoder CTL1 DATA VSYNC HSYNC Panel Interface Logic 24 24 VCR Channel SYNC SYNC1 VCR SYNC0 QE[23:0] QO[23:0] ODCK DE HSYNC VSYNC SCDT CTL1 CTL2 CTL3 VCR PLL Absolute Maximum Conditions Symbol P arameter VCC Supply Voltage 3.3V VI Input Voltage VO TA TSTG θJA 1 Min -0.3 -0.3 -0.3 -25 -65 Typ Output Voltage Ambient Temperature (with power applied) Storage Temperature Thermal Resistance (Junction to Ambient) M ax 4.0 VCC+ 0.3 VCC+ 0.3 105 150 Units V V V °C °C °C/W 21 Notes: Permanent device damage may occur if absolute maximum conditions are exceeded. 2 Functional operation should be restricted to the conditions described under Normal Operating Conditions. Normal Operating Conditions Symbol P arameter VCC Supply Voltage VCCN Supply Voltage Noise TA Ambient Temperature (with power applied) Min 3.0 0 Typ 3.3 25 M ax 3.6 100 70 Units V mVP-P °C Silicon Image, Inc. 2 Subject to Change without Notice Silicon Image, Inc. DC Digital I/O Specifications SiI 161A SiI-DS-0009-D Under normal operating conditions unless otherwise specified. Symbol VIH VIL VOH VOL VCINL VCIPL VCONL VCOPL IOL 1 P arameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input Clamp Voltage1 Input Clamp Voltage1 Output Clamp Voltage1 Output Clamp Voltage1 Output Leakage Current Conditions Min 2 Typ M ax Units V V V 0.8 2.4 0.4 ICL = -18mA ICL = 18mA ICL = -18mA ICL = 18mA High Impedance -10 GND -0.8 IVCC + 0.8 GND -0.8 OVCC + 0.8 10 V V V V V µA Note: Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions for a pulse of greater than 3 ns or one third of the clock cycle. DC Specifications Under normal operating conditions unless otherwise specified. Symbol IOHD IOLD P arameter Output High Drive Data and Controls Output Low Drive Data and Controls Conditions VOUT = 2.4 V; ST = 1 ST = 0 VOUT = 0.8 V; ST = 1 VOUT = 0.4 V; ST = 1 ST = 0 ST = 1 ST = 0 ST = 1 ST = 1 ST = 0 Min 4.2 2.1 -7 -5.2 -2.6 8.5 4.2 -15 -10.4 -5.2 75 Typ 8 4 -11 -5.5 -2.8 17 9 -20 -16 -8 M ax 18 9 -15 -11 -5.5 37 18 -25 -23 -11 1000 1 270 Units mA mA mA mA mA mA mV mA mA IOHC IOLC ODCK, DE High Drive ODCK, DE Low Drive VOUT = 2.4 V; VOUT = 0.8V; VOUT = 0.4 V; VID IPD ICCR Differential Input Voltage Single Ended Amplitude Power-down Current 2 Receiver Supply Current IPDO Receiver Supply Current with Ouputs Powered Down ODCK=82.5MHz, 2-pixel/clock mode CLOAD = 10pF REXT_SWING = 510Ω Typical Pattern3 ODCK=82.5MHz, 2-pixel/clock mode CLOAD = 10pF REXT_SWING = 510Ω Worst Case Pattern4 ODCK=82.5MHz, 2-pixel/clock mode CLOAD = 10pF REXT_SWING = 510Ω Worst Case Pattern4 240 270 330 mA 240 mA Notes: 1 Guaranteed by design. Silicon Image, Inc. 3 Subject to Change without Notice Silicon Image, Inc. 2 SiI 161A SiI-DS-0009-D The transmitter must be in power-down mode, powered off, or disconnected for the current to be under this The Typical Pattern contains a gray scale area, checkerboard area, and text. Black and white checkerboard pattern, each checker is two pixel wide. maximum. 3 4 Silicon Image, Inc. 4 Subject to Change without Notice Silicon Image, Inc. AC Specifications Under normal operating conditions unless otherwise specified. SiI 161A SiI-DS-0009-D Symbol TDPS TCCS TIJIT P arameter Intra-Pair (+ to -) Differential Input Skew1 Channel to Channel Differential Input Skew1 Worst Case Differential Input Clock Jitter tolerance2,3 Low-to-High Transition Time: Data and Controls (70 C, 82.5 MHz, 2-pixel/clock, PIXS=1) DLHT Low-to-High Transition Time: Data and Controls (70 C, 165 MHz, 1-pixel/clock, PIXS=0) Low-to-High Transition Time: ODCK (70 C, 82.5 MHz, 2-pixel/clock, PIXS=1) Low-to-High Transition Time: ODCK (70 C, 165 MHz, 1-pixel/clock, PIXS=0) DHLT High-to-Low Transition Time: Data and Controls (70 C, 82.5 MHz, 2-pixel/clock, PIXS=1) High-to-Low Transition Time: Data and Controls (70 C, 165 MHz, 1-pixel/clock, PIXS=0) High-to-Low Transition Time: ODCK (70 C, 82.5 MHz, 2-pixel/clock, PIXS=1) High-to-Low Transition Time: ODCK (70 C, 165 MHz, 1-pixel/clock, PIXS=0) TSETUP Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup Time to ODCK falling edge (OCK_INV = 0) or to ODCK rising edge (OCK_INV = 1) at 165 MHz *OCK_INV = 1 Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time from ODCK falling edge, (OCK_INV = 0) or from ODCK rising edge (OCK_INV = 1) at 165 MHz, *OCK_INV = 0 1 2 3 4 5 Conditions 165MHz 165MHz 65 MHz 112 MHz 165 MHz CL = 10pF; ST = 1 CL = 5pF; ST = 0 CL = 10pF; ST = 1 CL = 5pF; ST = 0 CL = 10pF; ST = 1 CL = 5pF; ST = 0 CL = 10pF; ST = 1 CL = 5pF; ST = 0 CL = 10pF; ST = 1 CL = 5pF; ST = 0 CL = 10pF; ST = 1 CL = 5pF; ST = 0 CL = 10pF; ST = 1 CL = 5pF; ST = 0 CL = 10pF; ST = 1 CL = 5pF; ST = 0 CL = 10pF; ST = 1 CL = 5pF; ST = 0 CL = 10pF; ST = 1 CL = 5pF; ST = 0 Min Typ M ax 245 4 465 270 182 2.6 2.7 2.4 3.0 1.3 1.7 1.4 1.7 2.8 3.4 2.3 3.3 1.1 1.5 1.2 1.5 Units ps ns ps ps ps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.7 *0.7 0.7 *0.4 3.8 *3.8 4.2 *3.8 ns ns THOLD ns Notes: Guaranteed by design. Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification. Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures . Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle. Measured when transmitter was powered down (see SiI / AN-0005 “PanelLink Basic Design/Application Guide,” Section 2.4). Silicon Image, Inc. 5 Subject to Change without Notice Silicon Image, Inc. AC Specifications (continued) Under normal operating conditions unless otherwise specified. SiI 161A SiI-DS-0009-D Symbol RCIP FCIP RCIP FCIP RCIH P arameter ODCK Cycle Time1 ODCK Frequency1 ODCK Cycle Time1 ODCK Frequency 1 ODCK High Time4 (165MHz, 1-pixel/clock, Conditions (1-pixel/clock) (1-pixel/clock) (2-pixels/clock) (2-pixels/clock) PIXS = 0) CL = 10pF; ST = 1 CL = 5pF; ST = 0 CL = 10pF; ST = 1 CL = 5pF; ST = 0 Min 6.06 25 12.1 12.5 1.7 1.3 2.0 1.4 Typ M ax 40 165 80 82.5 Units ns MHz ns MHz ns ns ns ns RCIL ODCK Low Time4 (165MHz, 1-pixel/clock, PIXS = 0) TPDL THSC TFSC TST Notes: 1 2 3 4 5 Delay from PD Low to high impedance outputs1 Link disabled (DE inactive) to SCDT low1 Link disabled (Tx power down) to SCDT low5 Link enabled (DE active) to SCDT high1 ODCK high to even data output 1 10 100 25 0.25 250 40 ns ms ms DE edges RCIP Guaranteed by design. Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification. Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures . Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle. Measured when transmitter was powered down (see SiI/AN-0005 “PanelLink Basic Design/Application Guide,” Section 2.4). Setup and Hold Timings for data rates other than 165 MHz: The measurements shown above are minimum setup and hold timings based on the maximum data rate of 165 MHz. To estimate the setup and hold times for slower data rates (for either different resolutions or 2 pixel per clock mode), the following formula can be used: Time (at new frequency) = Time (165 MHz) + (Clock Period at new frequency – Clock Period at 165 MHz)/2 For the case of high strength output (ST=1) with a 10 pf load, and using the standard ODCK (ODCK_INV = 0), the table below shows the minimum set up and hold times for other speeds as follows: Data Rate (MHz) 165 112 82.5 56 Clock (ns) Setup (ns) Hold (ns) 6.06 0.70 3.80 8.93 2.13 5.23 12.12 3.73 6.83 17.86 6.60 9.70 UXGA SXGA UXGA SXGA 1 pixel/clock 1 pixel/clock 2 pixels/clock 2 pixels/clock Silicon Image, Inc. 6 Subject to Change without Notice Silicon Image, Inc. Timing Diagrams SiI 161A SiI-DS-0009-D 2.0 V SiI 161A 1 0pF 2.0 V 0.8 V D LHT D HLT 0.8 V Figure 1. Digital Output Transition Times RCIP RCIH 2.0 V 2.0 V 2.0 V 0.8 V RCIL Figure 2. Receiver Clock Cycle/High/Low Times 0.8 V RX0 VDIFF=0V RX1 TCCS RX2 VDIFF=0V Figure 3. Channel-to-Channel Skew Timing Output Timing ODCK_INV = 1 ODCK_INV = 0 TSetup QE[23:0]/QO[23:0], DE, HSYNC, VSYNC, CTL[3:1] T Hold Figure 4. Output Data, DE, and Control Signals Setup/Hold Times to ODCK Falling Edge when ODCK_INV=0, or ODCK Rising Edge when ODCK_INV = 1. Silicon Image, Inc. 7 Subject to Change without Notice Silicon Image, Inc. SiI 161A SiI-DS-0009-D Output Timing (continued) PD VIL TPDL QE[23:0]/QO[23:0], DE, CTL[3:1], VSYNC,HSYNC Figure 5. Output Signals Disabled Timing from PD Active TTFSC DE SCDT T THSC DE SCDT Figure 6. SCDT Timing from DE Inactive/Active Internal ODCK * 2 ODCK DE TST QE[23:0] FIRST DATA THIRD DATA QO[23:0] SECOND DATA FOURTH DATA Figure 7. TFT 2-Pixels/Clock Staggered Output Timing Diagram Silicon Image, Inc. 8 Subject to Change without Notice Silicon Image, Inc. Output Pins Description Pin Pin # Type N ame QE23Out See SiI QE0 161A Pin Diagram SiI 161A Description SiI-DS-0009-D QO23QO0 See SiI 161A Pin Diagram Out ODCK 44 Out DE 46 Out HSYNC VSYNC CTL1 CTL2 CTL3 48 47 40 41 42 Out Out Out Out Out Output Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode and to the first 24-bit pixel data for 2-pixels/clock mode. Output data is synchronized with output data clock (ODCK). Refer to the TFT Signal Mapping application note (SiI/AN-0007) which tabulates the relationship between the input data to the transmitter and output data from the receiver. A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Output Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode. During 1-pixel/clock mode, these outputs are driven low. Output data is synchronized with output data clock (ODCK). Refer to the TFT Signal Mapping application note ( iI/AN-0007) which tabulates the S relationship between the input data to the transmitter and output data from the receiver. A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Output Data Clock. This output can be inverted using the OCK_INV pin. A low level on PD or PDO will put the output driver into a high impedance (tri-state) mode. A weak internal pull-down device brings the output to ground. Output Data Enable. This signal qualifies the active data area. A HIGH level signifies active display time and a LOW level signifies blanking time. This output signal is synchronized with the output data. A low level on PD or PDO will put the output driver into a high impedance (tri-state) mode. A weak internal pull-down device brings the output to ground. In Dual Link Applications, the DE output pin of the Master is connected to the SYNC input pin of the Slave. Horizontal Sync input control signal. Vertical Sync input control signal. General output control signal 1. This output is not powered down by PDO. General output control signal 2. General output control signal 3. A low level on PD or PDO will put the output drivers (except CTL1 by PDO) into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Silicon Image, Inc. 9 Subject to Change without Notice Silicon Image, Inc. SiI 161A SiI-DS-0009-D Configuration Pins Description Pin Name Pin # Type Description OCK_INV 100 In ODCK Polarity. A LOW level selects normal ODCK output. A HIGH level selects inverted ODCK output. All other output signals are not affected by this pin. They will maintain the same timing no matter the setting of OCK_INV pin (See Fig. 8 on p.10). NOTE OCK_INV cannot be set HIGH (inverted) when operating in Dual Link Mode PIXS/M_S 4 In Pixel Select. A LOW level indicates one pixel (up to 24-bits) per clock mode using QE[23:0]. A HIGH level indicates two pixels (up to 48-bits) per clock mode using QE[23:0] for first pixel and QO[23:0] for second pixel. Master/Slave. When S_D pin is HIGH (Dual Link), this pin becomes M_S. When HIGH, it is in Master mode. When LOW, it is in Slave mode. The Master receiver is in one/two-pixels per clock mode depending upon Dual/Single (S_D) Link operation. The Slave receiver is always in one-pixel per clock mode. STAG_OUT/ SYNC 7 In Staggered Output. A HIGH level selects normal simultaneous outputs on all odd and even data lines. A LOW level selects staggered output drive. This function is only available in 2-pixels per clock mode. Synchronization. When S_D pin is HIGH (Dual Link), this pin is used to synchronize the Slave receiver to the Master receiver. The SYNC input pin of the Slave receiver is connected to the DE output pin of the Master receiver. Output Drive. A HIGH level selects HIGH output drive strength. A LOW level selects LOW output drive strength. Single/Dual Link Mode. When HIGH, it is in Dual Link Mode. When LOW it is in Single Link Mode. The Slave receiver is always in Dual Link mode. The Master receiver switches between Single and Dual Link mode depending upon the SCDT output of the Slave receiver that is connected to the S_D input of the Master receiver. ST S_D 3 1 In In Power Management Pins Description Pin Pin # Type Description N ame SCDT 8 Out Sync Detect. A HIGH level is outputted when DE is actively toggling indicating that the link is alive. A LOW level is outputted when DE is inactive, indicating the link is down. Can be connected to PDO to power down the outputs when DE is not detected. The SCDT output itself, however, remains in the active mode at all times. In Dual Link applications the SCDT pin of the Slave receiver is connected to the S_D pin of the Master receiver. PDO 9 In Output Driver Power Down (active LOW). A HIGH level indicates normal operation. A LOW level puts all the output drivers only (except SCDT and CTL1) into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. PDO is a sub-set of the PD description. The chip is not in power-down mode with this pin. SCDT and CTL1 are not tri-stated by this pin. PD 2 In Power Down (active LOW). A HIGH level indicates normal operation. A LOW level indicates power down mode. During power down mode, all the output drivers are put into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Additionally, all analog logic is powered down, and all inputs are disabled. Silicon Image, Inc. 10 Subject to Change without Notice Silicon Image, Inc. SiI 161A SiI-DS-0009-D Differential Signal Data Pins Description Pin Pin # Type Description N ame RX0+ 90 Analog TMDS Low Voltage Differential Signal input data pairs. RX091 Analog RX1+ 85 Analog RX186 Analog RX2+ 80 Analog RX281 Analog RXC+ 93 Analog TMDS Low Voltage Differential Signal input data pairs. RXC94 Analog EXT_RES 96 Analog Impedance Matching Control. Resistor value should be approximately ten times the characteristic impedance of the cable. In the common case of 50Ω transmission line, an external 560Ω resistor must be connected between AVCC and this pin. Reserved Pin Description Pin Name Pin # Type Description RESERVED 99 In Must be tied HIGH for normal operation. Power and Ground Pins Description Pin Name Pin # Type VCC 6,38,67 Power GND 5,39,68 Ground OVCC 18,29,43,57,78 Power OGND 19,28,45,58,76 Ground AVCC 82,84,88,95 Power AGND 79,83,87,89,92 Ground PVCC 97 Power PGND 98 Ground Description Digital Core VCC, must be set to 3.3V. Digital Core GND. Output VCC, must be set to 3.3V. Output GND. Analog VCC must be set to 3.3V. Analog GND. PLL Analog VCC must be set to 3.3V. PLL Analog GND. Data D Q ODCK ODCK_INV Silicon Image, Inc. 11 Subject to Change without Notice Silicon Image, Inc. SiI 161A SiI-DS-0009-D Figure 8: Block Diagram for ODCK_INV: note that ODCK_INV affects only the phase of the clock output, but does not change timing for data latching. Silicon Image, Inc. 12 Subject to Change without Notice Silicon Image, Inc. SiI 161A SiI-DS-0009-D TFT Panel Data Mapping The following table shows the output data mapping in one pixel per clock mode for the SiI 161A. This output data mapping is dependent upon the SiI PanelLink transmitters having the exact same type of input data mappings. Please refer to the SiI PanelLink transmitter for the specific input data mappings and to the TFT Signal Mapping application note (SiI A N-0007). SiI 161A 1-Pixel/Clock Output 18bpp BLUE[7:0] GREEN[7:0] RED[7:0] QE[7:2] QE[15:10] QE[23:18] 24bpp QE[7:0] QE[15:8] QE[23:16] T able 1. One Pixel/Clock Mode Data Mapping SiI 161A 2-Pixel/Clock Output 18bpp BLUE[7:0] - 0 GREEN[7:0] – 0 RED[7:0] – 0 BLUE[7:0] – 1 GREEN[7:0] – 1 RED[7:0] – 1 QE[7:2] QE[15:10] QE[23:18] QO[7:2] QO[15:10] QO[23:18] 24bpp QE[7:0] QE[15:8] QE[23:16] QO[7:0] QO[15:8] QO[23:16] T able 2. Two Pixel/Clock Mode Data Mapping Note: For 18-bit mode, the Flat Panel Timing Controller interfaces to the SiI 161A exactly the same as in the 24-bit mode; however, only 6 -bits per channel (color) are interfaced instead of the full 8. As can be seen from the above table, the data mapping for less than 24-bit per pixel interfaces are MSB justified. Silicon Image, Inc. 13 Subject to Change without Notice Silicon Image, Inc. Dual Link Mode Operation SiI 161A SiI-DS-0009-D SiI161A operates up to the full DVI Single Link bandwidth of 165MHz. In Dual Link applications, two SiI161A chips can be used to support pixel clock speeds up to 330MHz. These applications will only support panels with 48-bit, 2pixel per clock interfaces. See Figure 9 for connection details. In Single Link mode, the transmitter system does not send any Data over the second link connected to the Slave receiver. Therefore, the Slave receiver is not active and its outputs are tri-stated. All the Data, both EVEN and ODD pixels, are sent over the link connected to the Master receiver. Therefore all the Data, both EVEN and ODD pixels, for the panel is output by the Master receiver, which operates in 48-bit, 2-pixels per clock interface mode. In Dual Link mode, the transmitter system sends EVEN Data over the link connected to the Master receiver and the ODD Data over the link connected to the Slave receiver. Therefore, the EVEN Data for the panel is output by the Master receiver and the ODD Data is output by the Slave receiver. The Master receiver’s ODD Data bus is tri-stated to allow the Slave receiver’s EVEN Data bus to output the ODD Data for the panel. SCDT NC SiI161A SCDT Master Tx1(+/-)[3:1] TxC(+/-) SYNC Rx(+/-)[3:1] RxC(+/-) M_S S_D DE PDO ODCK HSYNC VSYNC DE[23:0] DO[23:0] PDO ODCK HSYNC VSYNC DE[23:0] DO[23:0] DE PANEL VCC SYSTEM SCDT SiI161A SYNC PDO ODCK HSYNC VSYNC DE[23:0] DO[23:0] NC NC NC Tx2(+/-)[3:1] Rx(+/-)[3:1] RxC(+/-) M_S S_D Slave DE NC VCC Configuration: Silicon Image, Inc. Figure 9: SiI161A Dual Link Block Diagram Master – The Master receiver will automatically configure to either Single or Dual Link operation (two or one pixel per clock mode, respectively) depending on the transmitter system output. This is accomplished by connecting the SCDT output pin of the Slave to the S_D pin on the Master. When the transmitter sends data on the second link, the SCDT output of the slave (and the S_D pin on the Master) becomes high, setting to Dual Link (one-pixel per clock) mode. If there is no data on the second link, the SCDT output of the Slave (and the S_D pin on the Master) becomes LOW, and the Master receiver is in Single Link (two-pixels per clock) mode. GND NC 14 Subject to Change without Notice Silicon Image, Inc. SiI 161A SiI-DS-0009-D The Master receiver is configured by tieing the M_S pin to HIGH. When it is in Dual Link mode, the Master receiver is in one-pixel per clock mode outputting the EVEN data for the panel. The Master receiver’s ODD data bus is tri-stated to allow the Slave receiver’s EVEN data bus to be used as the ODD data bus for the panel. When it is in Single Link mode, the Master receiver is in two-pixels per clock mode outputting both the EVEN and ODD data for the panel. The Slave receiver’s EVEN data bus is tri-stated to allow the Master receiver’s ODD data bus to be used as the ODD data for the panel. The DE output pin of the Master receiver is connected to the SYNC input pin of the Slave receiver. This is used for output synchronization between the Master receiver and Slave receiver. DE, HSYNC, VSYNC, and ODCK for the panel are all taken from the Master receiver. S lave – The Slave receiver is always configured for Dual Link (one pixel/clock) operation. This is accomplished by tieing the S_D pin to HIGH. The Slave receiver is never used in Single Link mode since the Master receiver is the primary receiver for Single Link Operation. The Slave receiver is configured by tieing the M_S pin to LOW. The Slave receiver will always contain the ODD data bus for the panel in Dual Link operation. Therefore, it will never be in two-pixels per clock mode. The SCDT output pin of the Slave receiver is connected to the S_D input pin of the Master receiver to automatically configure the Master for either Single or Dual Link mode depending upon whether the Slave receiver is active or not. The SYNC input pin of the Slave receiver is connected to the DE output pin of the Master receiver for synchronization. Since DE, HSYNC, VSYNC, and ODCK for the panel are all taken from the Master receiver, these pins are not connected from the Slave receiver. Power Down Outputs – The Slave receiver’s outputs are automatically tri-stated in Single Link mode, since it is not active. The Master receiver’s outputs are automatically tri-stated in Single or Dual Link mode when there are no sync signals coming from the transmitter. Both the Master and Slave receiver’s outputs can also be tri-stated by driving the PDO pins to LOW manually. For additional information about dual link operation, please see Application Notes SiI-AN-0030, (SiI161A Dual Link Receiver Implementation) and SiI-AN-0037 (SiI168 Transmitter Dual Link Applications). Silicon Image, Inc. 15 Subject to Change without Notice Silicon Image, Inc. Package Dimensions SiI 161A SiI-DS-0009-D PanelLink ® Lead Length 1.00mm Lead Width 0.20mm 100-pin Plastic TQFP Lead Pitch 0.50mm Body Size 14.00mm Device # Lot # Date Code # SiI Rev. # SiI161ACT 100 LNNNNN.NLLL XXYY X.XX Package Height 1.20mm max. Clearance 0.15mm max. 12.00mm Body Size 14.00mm Footprint 16.00mm Figure 10:100-pin TQFP Package Dimensions JEDEC code MS-026AED Silicon Image, Inc. 16 Subject to Change without Notice 12.00mm ® PanelLink Body Thickness 1.05 mm max. Footprint 16.00mm Silicon Image, Inc. PCB Thermal Design Options: SiI 161A SiI-DS-0009-D The SiI161A is packaged in a thermally enhanced 100 pin TQFP with an exposed metal pad (7.5mm x 7.5 mm) on the package designed for improved thermal dissipation. To improve the heat removal from the package, the exposed thermal pad may be soldered to a thermal landing area on the PCB, as described in the following section, entitled “Implementation Guidelines for Thermal Land Design”. Implementation of the thermal landing area on the PCB can, in some cases, make trace routing and board design complicated. In some applications, it may be desirable to eliminate the thermal landing area on the PCB. Generally the thermal performance of a package can be represented by the following parameter (JEDEC standard JESD 51-2, 51-6): θJA , Thermal resistance from junction to ambient θJA = (TJ - TA) / PH Where TJ is the junction temperature TA is the ambient temperature PH is the power dissipation θJA represents the resistance to the heat flows from the chip to ambient air. It is an index of heat dissipation capability. Lower θJA means better thermal performance. Implementation of the thermal landing area, combined with complete soldering of the package to the landing area results in a θJA of 21°C/W. If the SiI161A package is assembled to a standard PCB, without the thermal landing area, the θJA increases to 29°C/W. For comparison, the non-thermally enhanced 100 pin TQFP package has a θJA of 53°C/W, so the advantage of the exposed metal pad in the thermally enhanced SiI161A package is significant, even without a landing area on the PCB. In order to determine the requirements for soldering the SiI161A to the PCB, the following analysis is insightful. Assuming a worst case scenario, with operation at the maximum ambient temperature of 70°C, at maximum voltage (3.6V) and worst case pattern (330 mA) – the junction temperature would be 35°C above ambient, or 105°C. This is still well below the maximum junction temperature of 125°C, providing suitable margin even without requiring the use of solder and a specific landing area on the PCB. For comparison, with the improved thermal dissipation that results from complete soldering of the thermal pad on the chip to a thermal landing area on the PCB, the package temperature would be 23°C above ambient – or roughly 12°C cooler than a chip with no solder. Based on this analysis, the need for designing a thermal landing area on a PCB for use with the SiI161A receiver should be considered an optional design choice by the customer, and is not an absolute requirement. For more information regarding Thermal Design Options, please see Application Note SiI-AN-0045, Enhanced Thermal Packaging Options for SiI-161A. Silicon Image, Inc. 17 Subject to Change without Notice Silicon Image, Inc. SiI 161A SiI-DS-0009-D Implementation Guidelines for Thermal Land Design: As described above, a thermal land on the PCB may be incorporated on the PCB to improve the heat removal from the package. An example of this is shown in Figure 11, which depicts the exposed heat pad and Figure 12, which shows a TQFP Thermal Land Design on a PCB . The size of this thermal land can be smaller or larger than the exposed pad on the package. A clearance of at least 0.25 mm should be designed on the PCB between the outer edges of the thermal land and the inner edges of pad pattern for the leads to avoid any shorts. 7 .5 7 .5 Figure 11. Bottom View of Thermally Enhanced 100-pin TQFP Package 7.5 7.5 Figure 12. TQFP Thermal Land Design on PCB Silicon Image, Inc. 18 Subject to Change without Notice Silicon Image, Inc. SiI 161A SiI-DS-0009-D When a thermal land on the PCB is used to provide a means of improved heat transfer from the package to the board through a solder joint, thermal vias are required to remove the heat from the PCB. It is recommended that these vias connect to the ground plane of the PCB. These vias provide a heat transfer path from the top surface of the PCB to the inner layers and the bottom surface of the package. An array of vias should be incorporated in the thermal pad at 1.2 mm pitch grid, as shown in Figure 13. Thermal Pad Via Grid. It is also recommended that the via diameter should be around 12 to 13 mils (0.30 to 0.33 mm) and the via barrel should be plated with 1 oz copper to plug the via. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad and the thermal land. If the copper plating does not plug the vias, the thermal vias can be “tented” with solder mask on the top surface of the PCB to avoid solder wicking inside the via during assembly. The solder mask diameter should be at least 4 mils (0.1 mm) larger than the via diameter. 8.50 7 .00 8.00 7 .50 Figure 13. Thermal Pad Via Grid Board Mounting Guidelines The following are general recommendations for mounting exposed pad leadframe devices on the motherboard. This should serve as the starting point in assembly process development and it is recommended that the process should be developed based on past experience in mounting standard, non-thermally enhanced packages. Silicon Image, Inc. 19 Subject to Change without Notice Silicon Image, Inc. Stencil Design: SiI 161A SiI-DS-0009-D For improved heat transfer, the exposed pad on the package may be soldered to a thermal land on the PCB. This requires solder paste application not only on the pad pattern for lead attachment but also on the thermal land using the stencil. While for standard (non-thermally enhanced) leadframe based packages the stencil thickness depends on the lead pitch and package coplanarity only, the package standoff also needs to be considered for the thermally enhanced packages to determine the stencil thickness. For a nominal standoff of 0.1 mm, the stencil thickness of 5 to 8 mils (depending upon the pitch) should still provide good solder joint between the exposed pad and the thermal land. The aperture openings should be the same as the solder mask opening on the thermal land. Since a large stencil opening may result in poor release, the aperture opening can be subdivided into an array of smaller openings, similar to the thermal land pattern shown in Figure 14. Recommended Stencil Design. The above guidelines will result in the solder joint area to be about 80 to 90% of the exposed pad area. Figure 14. Recommended Stencil Design Silicon Image, Inc. 20 Subject to Change without Notice Silicon Image, Inc. SiI 161A SiI-DS-0009-D Application Information To obtain the most updated Application Notes and other useful information for your design application, please visit the Silicon Image web site at www. siimage.com, or contact your local Silicon Image sales office. Copyright Notice This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the express written permission of Silicon Image, Inc. Trademark Acknowledgment Silicon Image, the Silicon Image logo, PanelLink and the PanelLink Digital logo are trademarks or registered trademarks of Silicon Image, Inc. All other trademarks are the property of their respective holders. Disclaimer This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Ordering Information Part Number: SiI161ACT100 Revision History Revision Date A 3/00 B 7/00 C 11/00 D 3/01 Comment Full release Corrections to AC timing figures and values Addition of information for Dual Link Implementation and Thermal Design Corrected Functional Block Diagram © 2001 Silicon Image. Inc. 3/01 SiI-DS-0009-D Silicon Image, Inc. Tel: (408) 616-4000, 1-888-PanelLink Silicon Image, Inc. 21 Subject to Change without Notice Silicon Image, Inc. 1060 E. Arques Avenue Sunnyvale, CA 94086 USA SiI 161A Fax: (408) 830-9530 E-mail: s alessupport@ siimage.com Web: www.siimage.com www.panellink.com SiI-DS-0009-D Silicon Image, Inc. 22 Subject to Change without Notice