SL2364

ADVANCE INFORMATION DS 3305 -2.0 SL2364 VERY HIGH PERFORMANCE TRANSISTOR ARRAYS The SL2364 is an array of transistors internally connected to form a dual long-tailed pair with tail transistors. This is a monolithic integrated circuit manufactured on a very high speed bipolar process which has a minimum useable fT of 2.5GHz, (typically 5GHz). The SL2364 is in a 14 SO package and a high performance Dilmon encapsulation. 14 13 12 11 10 9 8 Q3 Q4 Q5 Q6 Q1 Q2 SUB FEATURES 1 2 3 4 5 6 7 Complete Dual Long-Tailed Pair in One Package Very High fT - Typically 5 GHz Very Good Matching Including Thermal Matching SL2364C DC14 MP14 APPLICATIONS Fig. 1 Pin connections (top view) Wide Band Amplification Stages 140 and 560 MBit PCM Systems Fibre Optic Systems High Performance Instrumentation Radio and Satellite Communications ELECTRICAL CHARACTERISTICS These characteristics are guaranteed of the following conditions (unless otherwise stated): Tamb = 22°C ±2°C Value Characteristics Min. BVCBO LVCEO BVEBO BVCIO hFE fT ∆VBE (See note 1) ∆VBE / TAMB CCB CCI 10 6 2.5 16 50 2.5 Typ. 20 9 5.0 40 80 5 2 -1.7 0.5 1.0 0.8 1.5 5 GHz mV mV/°C pF pF Max. V V V V IC = 10µA IC = 5mA IE = 10µA IC = 10µA IC = 8mA, VCE = 2V IC Tail) = 8mA, VCE = 2V IC Tail) = 8mA, VCE = 2V IC Tail) = 8mA, VCE = 2V VCB = 0 VCI = 0 Units Conditions NOTE 1. ∆VBE applies to | VBEQ3 - VBEQ4 | and | VBEQ5 - VBEQ6 | SL2364 TYPICAL CHARACTERISTICS 1.1 4 NORMALISED f (TYP) T 6 f (GHz) TYP T 1.0 0.9 2 0.8 fT NORMALISED AT +20°C VCE = 2V IC = 4.5mA 0 0 2 4 6 I (mA) C 8 10 0.7 Fig. 2 Collector current -60 -20 +20 +60 TEMPERATURE (°C) +100 +140 Fig. 3 Chip temperature ABSOLUTE MAXIMUM RATINGS Maximum individual transistor dissipation 200mW Storage temperature -55°C to + 150°C Maximum junction temperature + 150°C Package thermal resistance (°C/W): Chip to case 45 (MP14) 35 (DC14) Chip to ambient 123 (MP14) 120 (DC14) VCBO = 10V, VEBO = 2 5V VCEO = 6V. VCIO = 15V IC (any one transistor) = 20mA The substrate should be connected to the most negative point of the circuit to maintain electrical isolation between the transistors.