SLGSSTU32864E

SLGSSTU32864E DDR2 Configurable Registered Buffer Features: • Compatible with JEDEC standard SSTU32864 • Differential Clock inputs • SSTL_18 Clock and data input signaling • Output circuitry minimizes effects of SSO and unterminated lines • LVCMOS input levels on control and RESET pins • 1.7V-1.9V Supply voltage range. • Max Clock frequency > 300MHz General Description The SLGSSTU32864 is a configurable registered buffer designed for 1.7V to 1.9V VDD operating range. When C1 input pin is low, the SLGSSTU32864 is 1:1 25-bit configuration. When C1 input pin is high, the SLGSSTU32864 is 1:2 14-bit configuration. Additionally, C0 input pin controls the 1:2 pinout as register-A configuration (if low) , and register-B configuration (if high). The C0,C1, and RESET pins are LVCMOS input levels.The C0,C1 input pins are not intended to be switched dynamically during normal operation. They should be tied to logic high or low levels to configure the register. Data propagation from D to Q is controlled by the differential clock (CLK/CLK) and a control signals. The rising edge of CLK (crossing with CLK falling) is used to register the Data. All inputs are SSTL_18 except C0,C1, and RESET pins. The SLGSSTU32864 supports low-power standby operation. Setting RESET pin to a logic “low” disables (CLK/CLK) receivers, and allows floating inputs to all other receivers as well (D, VREF , CLK/CLK). Additionally, all internal registers are reset, and outputs (Q) are set “low”. RESET input pin must always be driven to a valid logic state “high” or “low”. RESET, an LVCMOS asynchronous signal, is also intended for use at the time of power-up. RESET must be held at a logic “low” level during power up. This ensures defined outputs before a stable CLK/CLK is supplied. The SLGSSTU32864 supports low-power active operation as it monitors DCS and CSR inputs. The Qn outputs will be prevented from changing states when both DCS and CSR inputs are high. The Qn outputs will be allowed to change state if either one of DCS or CSR inputs is low. If DCS control is not desired, then CSR input should be held low. In that case, the setup and hold times of DCS is the same as the other D inputs. Ordering Information: Package type LFBGA-96ball 13.5 X 5.5 mm body LFBGA-96ball 13.5 X 5.5 mm body Package suffix X X Topside marking SLGSSTU32864EX SLGSSTU32864EX Ordering code SLGSSTU32864EX-TR (2,000 pcs/tape and reel) SLGSSTU32864EX (2,000 pcs/tray) Applications: • PC3200/4300 DDR2 memory modules • 1:1 25-bit or 1:2 14-bit configurable registered buffer • 1.8V data registers Silego Technology Inc. (408) 327-8800 1 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E SLGSSTU32864 top view pinout, 1:1 (C0=0,C1=0) 1:1 Logic Diagram CLK CLK 1 A B C DCKE D2 D3 DODT D5 D6 NC CLK CLK D8 D9 D10 D11 D12 D13 D14 2 NC D15 D16 NC D17 D18 DCS CSR D19 D20 D21 D22 D23 D24 D25 3 VREF GND VDD GND VDD GND GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14 6 DNU Q15 Q16 DNU Q17 Q18 C0 DNU ZOL Q19 Q20 Q21 Q22 Q23 Q24 Q25 RESET DCKE VREF . . . . . .. . .. . . .. . D R CLK D E QCKE F G H J K RESET VDD R CLK D QODT L M N P R DODT R CLK D QCS T DCS CSR . Dn 1 of 22 . . .. CE R CLK D Qn To 21 other Dn channels Silego Technology Inc. (408) 327-8800 2 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E SLGSSTU32864 top view pinout, 1:2 “A”(C0=0,C1=1) 1:2 “A”- configuration Logic Diagram A CLK CLK 1 DCKE D2 D3 DODT D5 D6 NC CLK CLK D8 D9 D10 D11 D12 D13 D14 B C 2 NC DNU DNU NC DNU DNU RESET DCS CSR DNU DNU DNU DNU DNU DNU DNU 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 Q2A Q3A Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A Q11A Q12A Q13A Q14A 6 Q2B Q3B Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B Q11B Q12B Q13B Q14B QCKEA QCKEB RESET DCKE VREF . . . . . .. . .. . . .. . D R CLK D QODTA QODTB QCKEA . QCKEB E F G H J K L M N P R T R CLK D DODT . . QODTA QODTB R CLK D QCSA DCS QCSB CSR . Dn 1 of 11 . . .. CE R CLK D QnA . QnB To 10 other Dn channels Silego Technology Inc. (408) 327-8800 3 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E SLGSSTU32864 top view pinout, 1:2 “B”(C0=1,C1=1) 1:2 “B”- configuration Logic Diagram A CLK CLK 1 D1 D2 D3 D4 D5 D6 NC CLK CLK D8 D9 D10 DODT D12 D13 DCKE B C 2 NC DNU DNU NC DNU DNU RESET DCS CSR DNU DNU DNU DNU DNU DNU DNU 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A Q12A Q13A 6 Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B Q12B Q13B RESET DCKE VREF . . . . . .. . .. . . .. . D R CLK D QCKEA . QCKEB E F G H J K L M N P R T R CLK D DODT . . QODTA QODTB QODTA QODTB R CLK D QCSA QCKEA QCKEB DCS QCSB CSR . Dn 1 of 11 . . .. CE R CLK D QnA . QnB To 10 other Dn channels Silego Technology Inc. (408) 327-8800 4 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E SLGSSTU32864 Terminal Description: TERMINAL NAME Q (1:25) GND VDD D (1:25) CLK CLK C0,C1 RESET VREF CSR, DCS DODT DCKE QCS QODT QCKE NC DNU ZOL,ZOH TYPE OUTPUT GROUND POWER INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT NC DNU NC DESCRIPTION Q-Outputs that are stopped by CSR & DCS control. Ground Supply voltage D-Inputs latched in on the rising edge of CLK crossing falling edge of CLK Positive clock input Negative clock input Control inputs for register configurations: 1:1 , 1:2 A , 1:2 B Asynchronous reset (active low) Input reference voltage. Both inputs are internally connected together by 200Ω Chip select control pins. Q1-Q25 outputs stopped when CSR & DCS=high D-input. This register not stopped by CSR & DCS control. D-input. This register not stopped by CSR & DCS control. Q-Output. Not stopped by CSR & DCS control. Q-Output. Not stopped by CSR & DCS control. Q-Output. Not stopped by CSR & DCS control. No-connect. Ball present, but no internal connection to the die. Do-not-use. Ball internally connected to the die and should be left open-circuit. Reserved for future use. Ball present, not electrically connected to the die. Function Table Inputs RESET H H H H H H H H H H H H L DCS L L L L L L H H H H H H X, or Floating CSR L L L H H H L L L H H H X, or Floating L or H X, or Floating L or H X, or Floating L or H L or H L or H L or H L or H L or H CLK CLK Dn,DODT , DCKE L H X L H X L H X L H X X, or Floating Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs QCS L L Q0 L L Q0 H H Q0 H H Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L Silego Technology Inc. (408) 327-8800 5 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E Absolute Maximum Ratings Storage Temperature. . . . . . . . . . . . . . -65oC to +150oC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V Input Voltage1,2. . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V Output Voltage1,2 . . . . . . . . . . . . . . . . -0.5 to VDD +0.5 Input Clamp Current. . . . . . . . . . . . . . . . . . . . . . -50 mA Output Clamp Current . . . . . . . . . . . . . . . . . . . +50 mA Continuous VDD or GND Current/Pin. . . . . . . +100 mA BGA Package Thermal Impedance3 . . . . . . . . 37oC/W Notes: 1. The input and output negative voltage ratings may be exceded if the input and output clamp currents are within limits. 2. Limited to 2.5V Max. 3. The package thermal impedance is calculated according to JESD 51-7 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device. These ratings are stress specifications only and functional operation of the device at these or other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions: PARAMETER VDD VREF VTT VI VIH (DC) VIH (AC) VIL (DC) VIL (AC) VIH VIL VICR VID IOH IOL TA Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage DC Input Low Voltage AC Input Low Voltage Input High Voltage Level Input Low Voltage Level Common mode Input Range Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature 0 RESET, Cn CLK, CLK 0.65 X VDD 0.35 X VDD 0.675 0.6 -8 8 70 mA oC MIN 1.7 0.49 X VDD VREF - 0.04 0 VREF +0.125 Data Inputs VREF + 0.25 TYP .5 X VDD VREF MAX 1.9 0.51 X VDD VREF + 0.04 VDD UNITS VREF -0.125 VREF - 0.25 V 1.125 Silego Technology Inc. (408) 327-8800 6 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E SLGSSTU32864 DC Electrical Characteristics VDD = 1.8 +/-0.1V (unless otherwise stated) PARAMETER VOH VOL II IDD All Inputs Operating (Static) Dynamic operating (clock only) Dynamic IDDD Operating 1:1 (each data input) Dynamic Operating 1:2 (each data input) Data Inputs Ci CLK and CLK RESET CONDITIONS IOH = -100µA IOH = -6mA IOL = 100µA IOL = 6mA VI = VDD or GND VI = VIH(AC) or VIL(AC), RESET = VDD RESET = VDD, VI = VIH(AC) or VIL(AC), I = 0 O CLK & CLK switching 50% duty cycle RESET = VDD, VI = VIH(AC) or VIL(AC), CLK & CLK switching 50% duty cycle. One data input switching at half clock frequency, 50%duty cycle VI = VREF + 250 mV VICR=0.9V, VI(PP) = 600mV VI = VDD or GND 1.8V Standby (Static) RESET = GND 1.9V VDD 1.7V 1.7V -1.9V 1.7V 1.9V MIN 1.2 0.2 0.5 +5 100 40 µA µA mA V TYP MAX UNITS 1.7V -1.9V VDD - 0.2 28 µA/ MHz µA/ clock MHZ/ data µA/ clock MHZ/ data 5 5.2 5 pF 18 36 2.5 1.8V 4.4 4.2 3.8 4.8 4.6 Timing Requirements: (over operating free-air temperature range, unless otherwise noted) PARAMETER fclock tW tACT Clock frequency Pulse duration. CLK,CLK high or low Differential active time4 1 10 15 0.7 0.5 0.5 0.5 Input slew rates are 1V/ns + 20%. MIN MAX 300 UNITS MHz ns ns ns ns ns ns ns tINACT Differential inactive time5 tS tH Setup time Hold time , CLK , CSR high DCS before CLK , CLK , CSR low DCS before CLK CSR, ODT, CKE, and Data before CLK , CLK DCS, CSR, ODT, CKE, Data before CLK , CLK Notes: 4. Data and VREF inputs must be held low for a minimum time (tACT max) after RESET driven high 5. Data, VREF, and CLK,CLK inputs must be held at valid logic (high or low) levels for a minimum time (tINACT max) after RESET driven low Silego Technology Inc. (408) 327-8800 7 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E AC Specifications Switching Characteristics: (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL fMAX tPDM6,7 tRPHL CLK, CLK RESET Q Q From (Input) To (Output) VDD = 1.8V + 0.1V MIN 300 1.41 2.5 3 TYP MAX MHz ns ns UNITS Notes: 6. Includes 350pS trace delay of the test load 7. Guaranteed by design and may not be 100% production tested. Output Buffer Characteristics: (over recommended operating free-air temperature range, unless otherwise noted) VDD = 1.8V + 0.1V SYMBOL From To MIN TYP MAX dV/dt_r dV/dt_f 20% 80% 80% 20% 1 1 4 4 1 UNITS V/ns V/ns V/ns dV/dt_∆8 Notes: 8. Difference between rising and falling edge rates. VDD DUT 50 Ω Q . 10pF . Output 80% test point dv_f VOH 20% dt_f VOL Output load test circuit: high to low slew rate Voltage waveform: high to low slew rate DUT dt_r Q . 10pF . Output test point 50 Ω dv_r 80% 20% VOH VOL Output load test circuit: low to high slew rate Voltage waveform: low to high slew rate Silego Technology Inc. (408) 327-8800 8 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E test point VDD DUT Z=50 Ω 100Ω Q CLK 350ps trace 30pF 1k Ω 1k Ω . . test point CLK . . test point Output load test circuit RESET LVCMOS input tINACT IDD(2) VDD VDD/2 VDD/2 0V tACT Timing Input tPLH VICR VICR tPHL VID 90% 10% IDDH IDDL Output VOH VDD/2 VDD/2 VOL Voltage and Current Waveforms Inputs Active and Inactive Times Voltage Waveforms - Propagation Delay Times tw Input VIH VREF VREF VIL RESET LVCMOS input VIH VDD/2 VIL tPHL Output VOH VDD/2 VOL Voltage Waveforms - Pulse Duration Voltage Waveforms - Propagation Delay Times Timing Input VICR VID tS Input VREF tH VIH VREF VIL Voltage Waveforms - Setup and Hold Times Notes: 1. CL includes measurement probe and jig capacitance. 2. Conditions for IDD testing are with clock and data inputs at VDD or GND, and IO = 0mA 3. All input pulses are supplied by generators having: Zo=50Ω, input slew rate = 1 V/ns + 20% ( unless otherwise specified). 4. The outputs are measured individually with one transition per measurement. 5. VIH = VREF + 250mV (AC levels) for differential inputs. VIH = VDD for LVCMOS input. 6. VIL = VREF - 250mV (AC levels) for differential inputs. VIL = GND for LVCMOS input. 7. tPLH = tPHL = tPD Silego Technology Inc. (408) 327-8800 9 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E Package dimensions: SLGSSTU32864EX 96-LFBGA Silego Technology Inc. (408) 327-8800 10 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E Silego Technology Inc. reserves the right at any time to change specifications and circuitry without notice. Silego Technology Inc. does not assume responsibility for use of circuitry described. Circuit patent licenses are not implied. Silego Technology Inc. products are not authorized for use as critical components in life support devices or systems without obtaining express written approval from the president of Silego Technology Inc. A component is a critical component if failure to perform affects safety, effectiveness, or causes failure of the life support system. These systems are intended for surgical implant into the body, or support or sustain life, or whose failure to perform when properly used can be reasonably expected to result in injury to the user. Silego Technology Inc. (408) 327-8800 11 PRELIMINARY Data is subject to change. Mar 5, 2004