SPL09A

Preliminary GENERAL DESCRIPTION SPL09A 5KB LCD CONTROLLER/DRIVER The SPL09A is a CMOS 8-bit single chip microprocessor, which contains RAM, ROM, I/Os, interrupt/wakeup controller, timer and automatic display controller/driver for LCD. This chip is designed not only low power consumption but also provides standby mode controlled by software for power saving. It is very suitable for LCD hand-held products. FEATURES Built-in 8-bit CPU 96 bytes SRAM 5K bytes ROM Max. CPU frequency: 2.0MHz @ 3V CPU clock frequency is programmable, 1/2,1/4,1/8,or 1/16 of RC oscillator frequency W ide operating voltage : 2.4V - 3.4V 3.6V - 5.5V Provide 6 INT sources Built-in 32.768KHz crystal oscillator Crystal oscillator switches from strong to weak mode automatically Internal time base generator Built-in RC oscillator Only one resistor is needed Á 10 general purpose I/Os 6 IO pins support Key wake-up mode 2 IO pins are shared with LCD segments 1 IO pin is shared with LCD common BLOCK DIAGRAM 32.768KHz ROSC Interrupt/wakeup Control 32.768KHz Oscillator & Time base 10 I/O Ports IOCD3 - 0 (I/O) 5K bytes ROM One 16-bit Auto reload Timer One 16 bits timer / counter LCD controller Max. 26 segments x 5 commons 1/2, 1/3 bias ; 1/2, 1/3, 1/4,1/5 duty Provides useful display operation mode Low Voltage Reset Provides 2.2V low Voltage reset Low power consumption Operating current: 300 A/1.0MHz @ 3V Provides standby function (stop all oscillators) Very low current in Halt mode In Halt mode: IHALT < 1 A @ 3V 96 bytes RAM 8-bit RISC Processor IOEF5 - 0 (I/O) LCD RAM 26 SEGMENTS X 5 COMMONS LCD DRIVER COM4 - 0 SEG25 - 0 Sunplus Technology Co., Ltd. 1 Rev.: 0.1 1999.11.24 Preliminary SPL09A FUNCTION DESCRIPTION SPL09A provides 5K byte ROM with a LCD driver, which is capable to control 5 commons and 26 segments. The power consumption of SPL09A is very low in both Standby mode and Halt mode. It is very appropriate for LCD type hand-held product. OPERATING STATES The SPL09A provides three operating states: standby, halt, and operating. differences between the three operating states. Following table shows the Operating CPU 32768 oscillator LCD driver ON ON ON Halt OFF ON ON/OFF Standby OFF OFF OFF In operating state, all modules (CPU, 32768 oscillator, timer/counter, LCD driver…) are activated. Writing the SLEEP register ($09) enters the Halt/standby State. There are four wake-up sources in SPL09A: port IOEF wake-up, TIMR0 wake-up, 4Hz/8Hz/16Hz/32Hz wake-up and 2Hz/1Hz wake-up. If any wake-up event occurs, execution of the next instruction continues in the operating state. In standby mode, all modules will be shut down, and RAM and I/Os remain in their previous states. The current consumption is minimized. By writing to SLEEP register but keeps 32768 oscillator running, the system is in HALT State. CPU clock is halted while it waits for an event (key press, timer overflow) to generate a wake-up in HALT State. The 32768 related modules (timer/counter, LCD driver…) may remain active in the halt state. Following figure is a state diagram for the SPL09A. Write to SLEEP register, 32768 oscillator OFF OPERATING Wake-up or user reset , ter gis re N P rO EE to SL cilla to os rite 68 W 327 t se re STANDBY ak W up eor er us HALT State Diagram of SPL09A Sunplus Technology Co., Ltd. 2 Rev.: 0.1 1999.11.24 Preliminary SPL09A After the chip is awakened from Halt/standby State, CPU will continue to execute the next instruction. The RAM and I/O will not be affected by wake-up. MAP OF MEMORY AND I/Os * I/O PORT: - PORT IOCD $0004 IOEF $0005 - I/O CONFIG $0000 $0035 $0006 USER RAM and Stack * NMI SOURCE - INT1 (from TIMER 0) * INT SOURCE - INT0 (from TIMER 0) - 2KHz - T16Hz (4Hz/8Hz/16Hz/32Hz) - 128Hz - EXT INT (from IOCD0 pin) - T2 Hz (2Hz/1Hz) $1FFF $0800 UNUSED $0C00 USER PROGRAM $0100 UNUSED $0400 SUNPLUS TEST $0060 UNUSED $00A0 *MEMORY MAP (From ROM view) $0000 H/W Register I/Os, LCD RAM TIME-SETTING REGISTER RELATED Writing to TIME-SETTING register can program the time source of CPU wake-up and interrupt. For example, the programmer can change 2Hz wake-up and interrupt into 1Hz wake-up and interrupt by writing 80H into $0A. Thus, the system will wake up to service every second. Also, T16Hz (one of counter‘s clock source and wakeup & interrupt) can be one of 4Hz, 8Hz, 16Hz or 32Hz by setting bit0 and bit1 of TIME-SETTING register ($0A). At power on state, the default value of T16Hz is 4Hz and T2Hz is 2Hz. WATCHDOG TIMER (WDT) An on chip watchdog timer is available on SPL09A. The WDT is designed for recovering from system abnormal operation. If the system is hanged, WDT will generate a system reset to restart system after 1 second. If WDT is enabled, the WDT should be cleared every 0.5 seconds to avoid accidental reset. Writing the specified value 0FH to port $0F can clear the WDT. Note that the WDT only works when 32768 Hz clock is available. Sunplus Technology Co., Ltd. 3 Rev.: 0.1 1999.11.24 Preliminary SPL09A TIMER/COUNTER SPL09A contains one 16-bit timer/counter, TM0 respectively. In the timer mode, TM0 are auto-reload upcounters. When the timer overflows from $FFFF to $0000, the carry signal will generate the INT signal if the corresponding bit is enabled in INT ENABLE register ($0D). The timer will automatically reload the value assigned by the program and up count continuously. If TM0 is specified as a counter, the user can reset the counter by loading 0 into register $10 and $11 and loading 0 into the counter by writing to $12. After the counter is activated, the counter’s value can also be read from above registers ($10 and $11) and the read instruction will not affect the counter's value or reset it. The clock source of the timer/counter are selected as the following: TIMER/COUNTER ADDR. $0010 16-BIT TIMER $0011 $0012 TM0 16-BIT COUNTER $0010 $0011 $0012 Clock source 1: IOCD1, VDD,T16Hz,128Hz Clock source 2: IOCD0, VDD, Crystal oscillator, R-oscillator Output. Note:T16Hz can be one of 4Hz,8Hz,16Hz or 32Hz by setting $0A ( time-setting register ) MODE SELECT REGISTER $000B Select TM0 configuration R-oscillator Output, VDD ( 0Hz ) CLOCK SOURCE LCD CONTROLLER/DRIVER SPL09A contains a total of 130 dots LCD controller and driver. Programmers can set the LCD configuration (bias, duty, display mode) by writing to LCD control register ($18). Once the LCD configuration is initialized, the desired pattern can be displayed by filling the LCD buffer with appropriate data. The LCD driver can also operate during sleep by keeping 32768 oscillator running. For the power saving mode, programmer can set the LCD display option to turn the LCD display off by writing to control register ($18). The LCD driver in SPL09A is designed to fit most LCD's specifications. It can either be programmed as 1/2 or 1/3 bias. The duty is also programmable as 1/2, 1/3, 1/4 or 1/5 duty. MASK OPTIONS 32768 CRYSTAL OSCILLATOR X’TAL R-oscillator Sunplus Technology Co., Ltd. 4 Rev.: 0.1 1999.11.24 Preliminary SPL09A LOW VOLTAGE RESET (2.2V) Enable Disable LCD CHARGE PUMP CLOCK RATE 32KHz 4KHz I/O AND LCD DRIVER There are some examples shown as below: LCD Dots 130 125 96 Segment 26 25 24 Common 5 5 4 Input/Output IOCD1 - 0 IOCD2 - 0 IOCD3 - 0 Input/Output IOEF4 - 0 IOEF4 - 0 IOEF5 - 0 Each of input/output ports IOCD3 - 2 can be optioned to LCD segments independently, and IOEF5 can be optioned to LCD commons. PIN DESCRIPTION Mnemonic SEG23 – 0 COM3 – 0 IOEF5 – 0 IOCD3 – 0 ROSC RESET X32I X32O TEST VDD VSS VDD1, VDD2 CUP1, CUP2 LPWR Type O O I/O I/O I I I O I I I I I O LCD driver segment output LCD driver common output I/O port (IOEF5 can be optioned to COM4) I/O port (IOCD3 can be optioned to SEG24, and IOCD2 can be optional to SEG25) R-Oscillator input, connect to VDD through resistor System reset input 32.768KHz crystal input (provide LCD frequency) 32.768KHz crystal output TEST MODE Positive supply voltage input Ground Input Inputs for setting LCD Bias Inputs for setting LCD Bias Regulated voltage output terminal for oscillators Description Sunplus Technology Co., Ltd. 5 Rev.: 0.1 1999.11.24 SPL09A Bias option 1/2 Bias I/O Á VDD1 VDD2 0.01 CUP1 CUP2 1/3 Bias F 0.01 F IOCD3 IOCD2 IOCD1 IOCD0 (COM4) IOEF5 IOEF3 IOEF2 IOEF1 IOEF4 IOEF0 SEG23 SEG22 DEVICE Á (SEG25) (SEG24) SEG21 0.01 F VDD SEG20 SEG19 SEG18 RESET TEST 0.1 RESET X32I X32O VDD ROSC 20P 32768Hz 20P Rosc VDD F Inputs Á Preliminary C5 VDD1 VDD2 0.01 CUP1 0.01 CUP2 F Á SEG17 Á SEG16 SPL09A Á SEG15 F SEG14 SEG13 SEG12 SEG11 COM3 COM2 COM1 COM0 VDD2 CUP2 CUP1 VDD1 Bias option SEG10 SEGs [ 23:0 ] SEG9 APPLICATION NOTE LCD Module COMs [ 3:0 ] SPL09A application circuit Sunplus Technology Co., Ltd. SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 6 Rev.: 0.1 I/O 1999.11.24 Preliminary SPL09A DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. reference purposes only. Please note that application circuits illustrated in this document are for Sunplus Technology Co., Ltd. 7 Rev.: 0.1 1999.11.24