SSD1828Z

TABLE OF CONTENTS 1 2 GENERAL DESCRIPTION................................................................................................................. 1 FEATURES ........................................................................................................................................ 2 96x64 Graphic Display with a Icon Line .............................................................................................. 2 Programmable Multiplex ratio [16Mux - 65Mux] ................................................................................. 2 Single Supply Operation, 1.8 V - 3.3V .................................................................................................. 2 Low Current Sleep Mode ( VL5 > VL4 > VL3 > VL2 > VSS Relationship .............................................................................. 9 Table 5 -Modes of Operation ...................................................................................................................... 12 Table 6 - COMMAND TABLE...................................................................................................................... 17 Table 7 – Extended Command Table ......................................................................................................... 20 Table 8 - Read Status Byte ......................................................................................................................... 21 Table 9 - Address Increment Table............................................................................................................. 21 Table 10 - Commands Required for R/W (WR#) Actions on RAM ............................................................. 21 Table 11 - Maximum Ratings (Voltage Referenced to VSS) ........................................................................ 27 Table 12 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 1.8 to 3.3V, TA = -40 to 85°C).................................................................................................................................. 28 Table 13 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = VCI = 2.7V, TA = -40 to 85°C).................................................................................................................................. 30 Table 14 – Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) ................................. 31 Table 15 – Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7, VSS =0V).................................... 32 Table 16 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) .................................. 33 Table 17 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V) .................................. 34 Table 18 – Serial Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V) .................................... 35 Table 19 – Serial Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) .................................... 36 v SOLOMON SOLOMON SYSTECH LIMITED SEMICONDUCTOR TECHNICAL DATA SSD1828 Advanced Information LCD Segment / Common Driver with Controller CMOS 1 General Description SSD1828 is a single-chip CMOS LCD driver with controller for liquid crystal dot-matrix graphic display system. SSD1828 consists of 162 high voltage driving output pins for driving 96 Segments, 64 Commons and 1 icon driving with dual Common outputs. SSD1828 displays data directly from its internal 96x65 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from general MCU through hardware selectable 6800-/8080-series compatible Parallel Interface or 3/4 wires Serial Peripheral Interface. SSD1828 embeds a DC-DC Converter, a LCD Voltage Regulator, an On-Chip Bias Divider and an On-Chip Oscillator which reduce the number of external components. With the special design on minimizing power consumption and die layout, SSD1828 is suitable for any portable battery-driven applications requiring a long operation period and a compact size. This document contains information on a new product. Specification and information herein are subject to change without notice. Copyright  2002 SOLOMON Systech Limited Rev 1.10 07/2002 2 FEATURES 96x64 Graphic Display with a Icon Line Programmable Multiplex ratio [16Mux - 65Mux] Single Supply Operation, 1.8 V - 3.3V Maximum +12.0V LCD Driving Output Voltage Low Current Sleep Mode ( VL4 > VL3 > VL2 > VSS Table 4 - Vout > VL5 > VL4 > VL3 > VL2 > VSS Relationship 1 : a bias VL5 VL4 VL3 (a-1)/a * Vout (a-2)/a * Vout 2/a * Vout VL2 1/a * Vout a is equals to 9 at POR. 6.16 COM0 – COM63 These pins provide the row driving signal COM0 - COM63 to the LCD panel. See Figure 5 or Figure 7 about the COM signal mapping in different multiplex ratio N. 6.17 ICONS This pin is the special icons line COM signal output. 9 SSD1828 Rev 1.10 07/2002 SOLOMON 6.18 SEG0 – SEG95 These pins provide the LCD column driving signal. Their voltage level is VSS during sleep mode. 6.19 CL This pin is the external clock input for the device, which is enabled by using an extended command. Under normal operation, this pin should be left opened and internal oscillator will be used after power on reset. 6.20 MIO This pin is used for cascade purpose only. Under normal operation, it should be left open. 6.21 TEST0~13 These pins is used for internal only and should be left open, any connection is not allowed. 6.22 NOBUMP These pins are AL metal pads only, without any gold bump on the top. They should be left open, any connection is not allowed. 10 SSD1828 Rev 1.10 07/2002 SOLOMON 7 7.1 FUNCTIONAL BLOCK DESCRIPTIONS Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/C pin. If D/C is high, data is written to Graphic Display Data RAM (GDDRAM). If D/C is low, the input at D0 -D7 is interpreted as a Command and it will be decoded and written to the corresponding command register. Reset is of the same function as Power ON Reset (POR). Once RES# receives a negative reset pulse of about 1us, all internal circuitry will be back to its initial status. Refer to Command Description section for more information. 7.2 MPU Parallel 6800-series Interface The parallel interface consists of 8 bi-directional data pins (D0 - D7), R/W(WR#), D/C, E(RD#) and CS#. R/W(WR#) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. R/W(WR#) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/C input. The E(RD#) and CS# input serves as data latch signal (clock) when they are high and low respectively. Refer to Figure 10 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 3 below. R/W (WR) E(RD ) data bus N writ e column address dummy read n data read1 n+1 data read 2 n+2 data read 3 Figure 3 – Display Data Read with the insertion of Dummy Read 7.3 MPU Parallel 8080-series Interface The parallel interface consists of 8 bi-directional data pins (D0 - D7), R/W(WR#), E(RD#), D/C and CS#. The CS# input serves as data latch signal (clock) when it is low. Whether it is display data or status register read is controlled by D/C. R/W(WR#) and E(RD#) input indicates a write or read cycle when CS is low. Refer to Figure 12 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read. SSD1828 Rev 1.10 07/2002 SOLOMON 11 7.4 MPU Serial 4-wire Interface The serial interface consists of serial clock SCK, serial data SDA, D/C and CS#. SDA is shifted into a 8-bit shift register on every rising edge of SCK in the order of D7, D6, ... D0. D/C is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock. No extra clock or command is required to end the transmission. 7.5 MPU Serial 3-wire interface Operation is similar to 4-wire serial interface while D/C is not been used. The Display Data Length instruction is used to indicate that a specified number display data byte(s) (1-256) are to be transmitted. Next byte after the display data string is handled as a command. It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in the serial communication, a hardware reset pulse at RES# pin is required to initialize the chip for re-synchronization. Table 5 -Modes of Operation 6800 Parallel Data Read Data Write Command Read Command Write Yes Yes Status only Yes 8080 Parallel Yes Yes Status only Yes Serial No Yes No Yes 7.6 Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 96 x 65 = 6,240bits for SSD1828. Figure 5 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs are provided. For vertical scrolling of display, an internal register storing the display start line can be set to control the portion of the RAM data mapped to the display. Figure 5 shows the case in which the display start line register is set at 30H. For those GDDRAM out of the display common range, they could still be accessed, for either preparation of vertical scrolling data or even for the system usage. 7.7 Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator. 12 SSD1828 Rev 1.10 07/2002 SOLOMON Oscillator enable enable Oscillation Circuit enable Buffer (CL) Internal Resistor OSC1 OSC2 Figure 4 - Oscillator Circuitry 7.8 LCD Driving Voltage Generator and Regulator This module generates the LCD voltage needed for display output. It takes a single supply input and generates necessary bias voltages. It consists of: 1. 2X, 3X, 4X and 5X DC-DC voltage converter 2. Bias Divider If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block will divide the regulator output (Vout) to give the LCD driving levels (VL2 - VL5). The divider does not require external capacitors to reduce the external hardware and pin counts. 3. Contrast Control Software control of 64 voltage levels of LCD voltage. 4. Bias Ratio Selection circuitry Software control of 1/4 to 1/9 bias ratio to match the characteristic of LCD panel. 5. Self adjust temperature compensation circuitry Provide 4 different compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. Defaulted temperature coefficient (PTC3) value is -0.05%/°C. 7.9 161 Bit Latch A register carries the display signal information. In 96 X 65 display-mode, data will be fed to the HV-buffer Cell and level-shifted to the required level. 7.10 Level selector Level Selector is a control of the display synchronization. Display voltage can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform. 7.11 HV Buffer Cell (Level Shifter) HV Buffer Cell works as a level shifter, which translated the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock, which comes from the Display Timing Generator. The voltage levels are given by the level selector, which is synchronized with the internal M signal. SSD1828 Rev 1.10 07/2002 SOLOMON 13 7.12 Default Value after hardware reset W hen RES input is low, the chip is initialized to the following: Register Default Value Remarks: Page address 0 Column address 0 Display ON/OFF 0 Display OFF Display Start Line 0 GDDRAM page 0,D0 Display Offset 0 COM0 is mapped to ROW0 Mux Ratio 40H 64 Mux Normal/Reverse Display 0 Normal Display N-line Inversion 0 No N-line Inversion Entire Display 0 Entire Display is OFF DC-DC booster 3 2X booster is selected Internal Resistor Ratio 0 Gain = 2.3 (IR0) Contrast 20H LCD Bias Ratio 5 1/9 Bias Ratio Scan direction of COM 0 Normal Scan direction Segment Remap 0 Segment remap is disabled Internal oscillator 0 Internal oscillator is OFF o Temperature coefficient 2 PTC3 (-0.05%/ C) Icon display 0 Icon display line is OFF Frame frequency 2 Frame frequency = 75Hz Power control 0,0,0 Booster, regulator & divider are both disabled W hen RESET command is issued, the following parameters are initialized only: Register Default Value Remarks: Page address 0 Column address 0 Display Start Line 0 GDDRAM page 0,D0 Internal Resistor Ratio 0 Gain = 2.3 (IR0) Contrast 20H 7.13 LCD Panel Driving Waveform The following is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms shown in Figure 6and Figure 7 illustrate the desired multiplex scheme with N-line inversion feature is disabled (default). 14 SSD1828 Rev 1.10 07/2002 SOLOMON Page Address D3 D2 D2 D0 D D D D 0 D D D D D D D D 1 D D D D 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. Page 0 0 0 0 Page 1 0 0 0 Line Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Normal COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 Re-mapped COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 …………… …………… …………… …………… …………… …………… …………… Page 6 1 1 1 Page 7 1 1 1 Page 8 0 0 0 D D D D 0 D D D D D D D D 1 D D D D 0D 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 ICONS COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 ICONS SEG Re-map = 0 00 SEG Re-map = 1 5F SEG0 SEG Outputs 01 02 03 5E 5D 5C SEG1 SEG2 SEG3 5C 5D 5E 03 02 01 SEG92 SEG93 SEG94 5F 00 SEG95 Figure 5 - SSD1828 Graphic Display Data RAM (GDDRAM) Address Map (with vertical scroll value 30H) …………… NOMOLOS SSD1828 Rev 1.10 07/2002 15 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG 0 SEG 1 SEG 2 SEG 3 SEG 4 Figure 6 - LCD Display Example “0” TIME SLOT 123456789 .. . * N1 2 3 4 5 6 7 8 9 . .. * N123456789 .. . * N1 2 3 4 5 6 7 8 9 .. . * N V o ut V L5 COM0 V L4 V L3 V L2 VS S V o ut V L5 COM1 V L4 V L3 V L2 VS S V o ut V L5 SEG0 V L4 V L3 V L2 VS S V o ut V L5 SEG1 V L4 V L3 V L2 VS S M * Note : N is the number of multiplex ratio including Icon line if it is enabled, N is equal to 64 on POR . Figure 7 - LCD Driving Signal from SSD1828 16 SSD1828 Rev 1.10 07/2002 SOLOMON COMMAND TABLE Table 6 - COMMAND TABLE Bit Pattern 0000 C3C2C1C0 0001 0C6C5C4 0010 0R2R1R0 Command Set Column LSB Set Column MSB Set Internal Resistor Ratio Description Set the lower nibble of the column address pointer for RAM access. The pointer is reset to 0 after reset. Set the upper nibble of the column address pointer for RAM access. The pointer is reset to 0 after reset. The internal regulator gain (1+R2/R1) Vout increases as R2R1R0 is increased from 000b to 111b. The factor, 1+R2/R1, is given by: R2R1R0 = 000: 2.3 (POR) R2R1R0 = 001: 3.0 R2R1R0 = 010: 3.7 R2R1R0 = 011: 4.4 R2R1R0 = 100: 5.1 R2R1R0 = 101: 5.8 R2R1R0 = 110: Reserved R2R1R0 = 111: Reserved (Refer to 8.14) VC VR = 00: turn OFF the internal voltage booster & regulator (POR) VC VR = 01,10,11: turn ON the internal voltage booster & regulator VF=0: turn OFF the output op-amp buffer (POR) VF=1: turn ON the output op-amp buffer This command set the Temperature Coefficient T2T1T0: o 001: -0.035%/ C o 010: -0.035%/ C o 011: -0.05%/ C (POR) o 100: -0.083%/ C The second command specifies the row address pointer (0-63) of the RAM data to be displayed in COM0. This command has no effect on ICONS. The pointer is set to 0 after reset. The second command specifies the mapping of first display line (COM0) to one of ROW0~63. This command has no effect on ICONS. COM0 is mapped to ROW0 after reset. 0010 1VC VR VF Set Voltage Control 0011 1T2T1T0 Set TC value 0100 00XX XL6L5L4 L3L2L1L0 0100 01XX XXC5C4 C3C2C1C0 Set Initial Display Line Set Initial COM0 SSD1828 Rev 1.10 07/2002 SOLOMON 17 Bit Pattern 0100 10XX XD6D5D4 D3D2D1D0 Command Set Multiplex Ratio (partial display) Description The second command specifies the number of lines, excluding ICONS, to be displayed. With Icon is disabled (POR), 16~64 mux could be selected. With Icon enabled, the available mux are 17~ 65. Mux (Icon disable) Mux (Icon enable) D6 – D0 000000 … 0001111 0010000 0010001 … 1000000 1000001 1000010 64 invalid invalid 65 invalid invalid invalid 16 17 invalid 17 18 invalid invalid 0100 11XX XXXN4 N3N2N1N0 Set N-line Inversion 0101 0B2B1B0 Set LCD Bias 0110 01B1B0 Set Boost Level 1000 0001 XXC5C4 C3C2C1C0 1010 000S0 1010 001C0 1010 010E0 Set Contrast Level Set Segment Re-map Icon Control Register ON/OFF Entire Display Select 1010 011R0 Invert Display Select … 1111111 invalid invalid The second command sets the n-line inversion register from 3 to 33 lines to reduce display crosstalk. Register values from 00001b to 11111b are mapped to 3 lines to 33 lines respectively. Value 00000b disables the N-line inversion, which is the POR value. To avoid a fix polarity at some lines, it should be noted that the total number of mux (including the icon line) should NOT be a multiple of the lines of inversion (n). Sets the LCD bias from 1/4 ~ 1/9 according to B2B1B0: 000: 1/4 bias 001: 1/5 bias 010: 1/6 bias 011: 1/7 bias 100: 1/8 bias 101: 1/9 bias (POR) 110: 1/9 bias 111: 1/9 bias Set the DC-DC multiplying factor from 2X to 5X B1B0: 00: 3X 01: 4X 10: 5X 11: 2X (POR) The second command sets one of the 64 contrast levels. The darkness increase as the contrast level increase. S0=0: column address 00H is mapped to SEG0 (POR) S0=1: column address 5FH is mapped to SEG0 C0=0: Disable icon row (Mux = 16 to 64, POR) C0=1: Enable icon row (Mux = 17 to 65) E0=0: Normal display (display according to RAM contents, POR) E0=1: All pixels are ON regardless of the RAM contents *Note: This command will override the effect of “Set Normal/Invert Display” R0=0: Normal display (display according to RAM contents, POR) R0=1: Invert display (ON and OFF pixels are inverted) *Note: This command will not affect the display of the icon lines 18 SSD1828 Rev 1.10 07/2002 SOLOMON Bit Pattern 1010 1000 1010 1001 Command NOP Power Save Mode 1010 1011 1010 111D0 Start Internal Oscillator Display On/Off 1011 P3P2P1P0 1100 S0XXX 1101 1F2F1F0 Set Page Address Set COM Scan Direction Set Frame Frequency 1110 0001 1110 0010 1110 0100 1110 1000 D7D6D5D4 D3D2D1D0 Exit Power-save Mode Software Reset Release N-line Inversion Mode Display Data Length Description No operation Sleep Mode: Oscillator: OFF LCD Power Supply: OFF COM/SEG Outputs: VSS This command starts the internal oscillator. Note that the oscillator is OFF after reset, so this instruction must be executed for initialization Turn the display on and off without modifying the content of the RAM. (0: off, 1: on) This command has priority over Entire Display On/Off and Invert Display On/Off. Commands are accepted while the display is off, but the visual state of the display does not change. Set GDDRAM page address (0~8) using P3P2P1P0 for RAM access. The page address is sets to 0 after reset. Set the COM (row) scanning direction. (0: COM0 →COM63, 1: COM63 →COM0) This command is used to set the frame frequency. Frame Frequency F2F1F0 000 68 001 73 010 75 (POR) 011 80 100 80 101 86 110 90 111 100 DC-DC converter, regulator and divider status before entering the power-save mode is restored. At POR, Power-save Mode is released. Reset some functions of the driver/controller. See Reset Section below for more details. Release the driver/controller from N-line inversion mode. The frame will be inverted once per frame This command is used in 3-line SPI mode (without D/C line) to specify that the controller is about to send display data to the display RAM. Eight bits are used to specify the number of bytes to be sent (1 to 256 bytes). The second command received after the display data is transmitted is assumed to be command data. SSD1828 Rev 1.10 07/2002 SOLOMON 19 Table 7 – Extended Command Table Bit Pattern 1111 0010 0000 X0000 Other than above Command Comment Enable external oscillator input Select external oscillator input form CL pin. X0 = 0 : (POR) internal RC oscillator X0 = 1 : external square wave Reserved 20 SSD1828 Rev 1.10 07/2002 SOLOMON 7.14 Read Status Byte A 8 bits status byte will be placed to the data bus if a read operation is performed if D/C is low. The status byte is defined as follow. Table 8 - Read Status Byte Bit Pattern BUSY ON RES 0 1000 Command Read Status Comment BUSY=0: Chip is idle BUSY=1: Chip is executing instruction ON=0: Display is OFF ON=1: Display is ON RES=0: Chip is idle RES=1: Chip is executing reset 7.15 Data Read / Write To read data from the GDDRAM, input High to R/W(WR#) pin and D/C pin for 6800-series parallel mode. Low to E(RD#) pin and High to D/C pin for 8080-series parallel mode. No data read is provided for serial mode. In normal mode, GDDRAM column address pointer will be increased by one automatically after each data read. Also, a dummy read is required before the first data is read. See Figure 3 in Functional Description. To write data to the GDDRAM, input Low to R/W(WR#) pin and High to D/C pin for 6800-series parallel mode. For serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one automatically after each data write. The address will be reset to 0 in next data read/write operation is executed when it is 95. Table 9 - Address Increment Table D/C 0 0 1 1 R/W (WR) 0 1 0 1 Comment W rite Command Read Status W rite Data Read Data Address Increment No No Yes Yes Address Increment is done automatically after data read/write. The column address pointer of GDDRAM is also affected. It will be reset to 0 in next data read/write operation is executed when it is 95. Table 10 - Commands Required for R/W (WR#) Actions on RAM R/W (WR) Actions on RAMs Read/write Data from/to GDDRAM Commands Required Set GDDRAM Page Address Set GDDRAM Column Address Read/Write Data (1011X3X2X1X0)* (0001X3X2X1X0)* (0000X3X2X1X0)* (X7X6X5X4X3X2X1X0) * No need to resend the command again if it is set previously. The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content whether the target RAM content is being displayed or not. SSD1828 Rev 1.10 07/2002 SOLOMON 21 8 8.1 COMMAND DESCRIPTIONS Set Display On/Off This command turns the display on/off, by the value of the LSB. 8.2 Set Display Start Line This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0. The display start line values of 0 to 63 are assigned to Page 0 to 7. 8.3 Set Page Address This command positions the page address to 0 to 8 possible positions in GDDRAM. Refer to Figure 5. 8.4 Set Higher Column Address This command specifies the higher nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>95). 8.5 Set Lower Column Address This command specifies the lower nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>95). 8.6 Set Temperature Coefficient (TC) Value This command is to set 1 out of 4 different temperature coefficients in order to match various liquid crystal temperature grades. 8.7 Set Segment Re-map This commands changes the mapping between the display data column address and segment driver. It allows flexibility in layout during LCD module assembly. Refer to Figure 5. 8.8 Set Normal/Reverse Display This command sets the display to be either normal/reverse. In normal display, a RAM data of 1 indicates an “ON” pixel while in reverse display; a RAM data of 0 indicates an “ON” pixel. The icon line is not affected by this command. 8.9 Set Entire Display On/Off This command forces the entire display, including the icon row, to be “ON” regardless of the contents of the display data RAM. This command has priority over normal/reverse display. To execute this command, Set Display On command must be sent in advance. 8.10 Set LCD Bias This command selects a suitable bias ratio (1/4 to 1/9) required for driving the particular LCD panel in use. The POR is set to 1/9 bias. 22 SSD1828 Rev 1.10 07/2002 SOLOMON 8.11 Software Reset This command causes some of the internal status of the chip to be initialized: Register Default Value Remarks: Page address 0 Column address 0 Display Start Line 0 GDDRAM page 0,D0 Internal Resistor Ratio 0 Gain = 2.3 (IR0) Contrast 20H 8.12 Set COM Output Scan Direction This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly. 8.13 Set Power Control Register This command turns on/off the various power circuits associated with the chip. There are three power relating sub-circuits could be turned on/off by this command. Internal voltage booster is used to generate the highest positive voltage supply internally from the voltage input (VCI -VSS). Internal regulator is used to generate the LCD driving voltage. Output op-amp buffer is the internal divider for dividing the different voltage levels (VL2, VL3, VL4, VL5) from the internal regulator output, Vout. External voltage sources should be fed into this driver if this circuit is turned off. 8.14 Set Internal Regulator Resistors Ratio This command is to enable any one of the eight internal resistor (IRS) settings for different regulator gains when using internal regulator resistor network. The Contrast Control Voltage Range curves is referred to the following formula:  R Vout = 1 + 2  *Vcon  R 1   63 − α  Vcon = 1 −  * Vref 210   , where Vref = 2.1V SSD1828 Rev 1.10 07/2002 SOLOMON 23 Vout 16 Contrast Curve 14 12 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 10 8 6 4 2 Contrast[0~63] 0 0 10 20 30 40 50 60 70 Figure 8 - Contrast Control Voltage Range Curve (VDD=2.775V; VCI=3.5V; TC=-0.05%/ C) o 8.15 Set Contrast Control Register This command adjusts the contrast of the LCD panel by changing Vout of the LCD drive voltage provided by the On-Chip power circuits. Vout is set with 64 steps (6-bit) contrast control register. It is a compound commands: Set Contrast Control Register Contrast Level Data No Changes Complete? Yes Figure 9 - Contrast Control Flow Set Segment Re-map 24 SSD1828 Rev 1.10 07/2002 SOLOMON 8.16 Set Frame Frequency This command specifies the frame frequency so as to minimize the flickering due to the ac main frequency. The frequency is set to 75Hz at 64 mux after POR. 8.17 Set Multiplex Ratio This command switches default 64 multiplex modes to any multiplex from 16 to 64, if Icon is disabled (POR). When Icon is set enable, the corresponding multiplex ratio setting will be mapped to 17 to 65. The chip pads ROW0-ROW63 will be switched to corresponding COM signal output as specified in Table 2. 8.18 Set Power Save Mode Force the chip to enter Standby or Sleep Mode. LSB of the command will define which mode will be entered. 8.19 Exit Power Save Mode This command releases the chip from Sleep Mode and return to normal operation. 8.20 Set N-line Inversion Number of line inversion is set by this command for reducing crosstalk noise. 3 to 33-line inversion operations could be selected. At POR, this operation is disabled. It should be noted that the total number of mux (including the icon line) should NOT be a multiple of the inversion number (n). Or else, some lines will not change their polarity during frame change. 8.21 Exit N-line Inversion This command releases the chip from N-line inversion mode. The driving waveform will be inverted once per frame after issuing this command. 8.22 Set DC-DC Converter Factor Internal DC-DC converter factor is set by this command. For SSD1828, 2X to 5X multiplying factors could be selected. 2X to 5X factors are selected using this command. 8.23 Set Icon Enable This command enable/disable the Icon displays. 8.24 Start Internal Oscillator After POR, the internal oscillator is OFF. It should be turned ON by sending this command to the chip. 8.25 Set Display Data Length This two-bytes command only valid when 3-wire SPI configuration is set by H/W input (PS0=PS1=L). The second 8-bit is used to indicate that a specified number display data byte(s) (1-256) are to be transmitted. Next byte after the display data string is handled as a command. 8.26 Set Test Mode This command forces the driver chip into its test mode for internal testing of the chip. Under normal operation, user should NOT use this command. 25 SSD1828 Rev 1.10 07/2002 SOLOMON 8.27 Status Register Read This command is issued by setting D/C Low during a data read (refer to figure 1 and 2 parallel interface waveform). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode. EXTENDED COMMANDS These commands are used, in addition to basic commands, to trigger the enhanced features, on top of general ones, designed for the chip. 8.28 Enable external oscillator input. This command enables the external clock input from CL pin and expected external square wave is 58.5kHz. 26 SSD1828 Rev 1.10 07/2002 SOLOMON 9 MAXIMUM RATINGS Parameter Supply Voltage Booster Supply Voltage Input Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Range Value -0.3 to 5.5 VSS -0.3 to VSS +12.0 VDD to +5.5 VSS -0.3 to VDD +0.3 25 -40 to +85 -65 to +150 Unit V V V V mA °C °C Table 11 - Maximum Ratings (Voltage Referenced to VSS) Symbol VDD VCC VCI Vin I TA Tstg * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to range VSS < or = (Vin or Vout) < or = VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either VSS or VDD). Unused outputs must be open. This device may be light sensitive. Caution should be taken to avoid exposure of this device any light source during normal operation. This device is not radiation protected. SSD1828 Rev 1.10 07/2002 SOLOMON 27 10 DC CHARACTERISTICS Table 12 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 1.8 to 3.3V, TA = -40 to 85°C) Symbol VDD VCI IAC Parameter Logic Circuit Supply Voltage Range Booster Voltage Supply Pin Access Mode Supply Current Drain (VDD Pins) Test Condition (Absolute value referenced to VSS) (Absolute value referenced to VSS) VDD = 2.7V, Voltage Generator On, 4X DC-DC Converter Enabled, Write accessing, Tcyc =3.3MHz, Osc. Freq.=58.5kHz, Display On. VDD =VCI = 2.7V, Voltage Generator off, external Vout Divider Enable. Read/Write Halt, Osc. Freq. = 58.5kHz, Display On, Vout = 10.0V. VDD = 1.8V, VCI = 2.5V, Voltage Generator ON, 5x DC-DC Converter Enabled, Internal Vout Divider Enable. Read/Write Halt, Osc Freq. = 58.5kHz, Display On, Vout = 10.0V, no panel loading. VDD = 2.7V, LCD Driving Waveform Off, Oscillator Off, Read/Write halt. Display On, Voltage Generator Enabled, DC/DC Converter Enabled, Regulator Enabled, Osc. Freq. = 58.5kHz, Min 1.8 VDD Typ 2.7 600 Max 3.3 3.6 800 Unit V V uA IDP1 Display Mode Supply Current Drain (VDD & VCI Pins) Display Mode Supply Current Drain (VDD &VCI Pins) - 20 40 µA IDP2 - 100 150 µA ISLEEP Vout Sleep Mode Supply Current Drain (VDD Pins) LCD Driving Voltage Generator Output (Vout Pin) 4.0 0.5 - 1 12.0 µA V VLCD VOH1 VOL1 Vout Vout VIH1 VIL1 Vout VL5 VL4 DC-DC Converter Efficiency (Without loading) LCD Driving Voltage Input (Vout Pin) Output High Voltage (D0-D7) Out Low Voltage (D0-D7) LCD Driving Voltage Source (Vout Pin) LCD Driving Voltage Source (Vout Pin) Input high voltage (/RES, PS0, PS1, /CS, D/C, R/W, D0-D7) Input low voltage (/RES, PS0, PS1, /CS, D/C, R/W, D0-D7) LCD Display Voltage Output (Vout, VL5, VL4, VL3, VL2 Pins)\ Voltage Generator Disabled Iout = +500µA Iout = -500µA Regulator Enabled (Vout voltage depends on Internal contrast Control) Regulator Disable 4.0 0.8*VDD 0 VDD 0.8*VDD 0 Bias Divider Enabled, 1:a bias ratio - 95 Floating Vout (a-1)/a*Vout (a-2)/a*Vout 12.0 VDD 0.2*VDD 12.0 VDD 0.2*VDD - % V VLCD V V V V V V V V 28 SSD1828 Rev 1.10 07/2002 SOLOMON Symbol VL3 VL2 Vout VL5 VL4 VL3 VL2 IOH IOL IOZ IIL /IIH CIN ∆Vout Parameter Test Condition Min VL5 VL4 VL3 VL2 VSS 50 -1 -1 - Typ 2/a* Vout 1/a* Vout 5 ±1 2.1 2.15 2.05 Max - Unit V V V LCD Display Voltage Input (Vout, VL5, VL4, VL3, VL2 Pins) Voltage reference to VSS, External Voltage Generator, Bias Diver Disabled Output High Current Source (D0-D7) Output Low Current Drain (D0-D7) Output Tri-state Current Source (D0-D7) Input Current (RES , PS0, PS1, CS , E, D/C, R/W, D0-D7 Input Capacitance (all logic pins) Variation of Vout Output (1.8V < VDD < 3.3V) Reference Voltage (T= 25ºC) Reference Voltage (T= 20ºC) Reference Voltage (T= 70ºC) Temperature Coefficient Compensation Temperature Coefficient 1* Temperature Coefficient 2* Temperature Coefficient 3*(POR) Temperature Coefficient 4* Output Voltage=V DD -0.4V Output Voltage = 0.4V Vout VL5 VL4 VL3 -50 1 1 7.5 2.16 2.21 2.11 V V V V µA µA µA µA PF % V V V Regulator Enabled, Internal Contrast Control Enabled, Set Contrast Control Register = 0 2.04 2.09 1.99 Vref PTC1 PTC2 PTC3 PTC4 Voltage Regulator Enabled Voltage Regulator Enabled Voltage Regulator Enabled Voltage Regulator Enabled 0 -0.025 -0.04 -0.07 -0.01 -0.035 -0.05 -0.083 -0.02 -0.045 -0.06 -0.096 %/ C o %/ C o %/ C %/ C o o * The formula for the temperature coefficient is: TC(%)= Vout 50ºC – Vout at 0ºC 50ºC – 0ºC X 1 X100% Vout at 25ºC SSD1828 Rev 1.10 07/2002 SOLOMON 29 11 AC CHARACTERISTICS Table 13 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = VCI = 2.7V, TA = -40 to 85°C) Symbol Fosc FFRM Parameter Oscillator frequency Frame Frequency Test Condition Display ON, Set 96 x 64 Graphic Display Mode, Icon Line Disabled Display ON, Set 96 x 64 Graphic Display Mode, Icon Line Disabled Min 50.7 65 Typ 58.5 75 Max 78 100 Unit kHz Hz 30 SSD1828 Rev 1.10 07/2002 SOLOMON Table 14 – Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time W rite Data Setup Time W rite Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 200 0 0 40 10 10 15 15 500 500 100 200 200 - Typ 1000 - Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns R/ W D/C tA S E t cycle tAH PW CSL CS tF tDSW D0 -D7 (Write data to driv er) tA CC D 0-D 7 (Read data f rom driv er) Valid Data PW CSH tR tDHW t DHR Valid Data tOH Figure 10 – Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H) SSD1828 Rev 1.10 07/2002 SOLOMON 31 Table 15 – Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7, VSS =0V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time W rite Data Setup Time W rite Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 100 0 0 30 5 10 15 15 250 250 50 100 100 - Typ 500 - Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns R/ W D/C tA S E t cycle tAH PW CSL CS tF tDSW D0 -D7 (Write data to driv er) tA CC D 0-D 7 (Read data f rom driv er) Valid Data PW CSH tR tDHW t DHR Valid Data tOH Figure 11 – Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H) 32 SSD1828 Rev 1.10 07/2002 SOLOMON Table 16 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time W rite Data Setup Time W rite Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 200 0 0 40 10 10 15 15 500 500 100 200 200 - Typ 1000 - Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns D/C tAH tAS WR ( R/W ) RD ( E) tcycl e PWCSL CS tF tD SW D0-D7 (Write dat a to driver) tAC C D0 -D7 (Read data from driver) Valid Data PW CSH tR t DH W t D HR Valid Data tOH Figure 12 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L) SSD1828 Rev 1.10 07/2002 SOLOMON 33 Table 17 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time W rite Data Setup Time W rite Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 100 0 0 30 5 10 15 15 250 250 50 100 100 - Typ 500 - Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns D/C tAH tAS WR ( R/W ) RD ( E) tcycl e PWCSL CS tF tD SW D0-D7 (Write dat a to driver) tAC C D0 -D7 (Read data from driver) Valid Data PW CSH tR t DH W t D HR Valid Data tOH Figure 13 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L) 34 SSD1828 Rev 1.10 07/2002 SOLOMON Table 18 – Serial Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V) Symbol Parameter Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time W rite Data Setup Time W rite Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time tcycle tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH tR tF Min 58.8 10 5 30 29.4 30 30 29.4 29.4 - Typ - Max 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns D/C (Required if PS1 = H) tAS CS tCSS t c ycle tC L KH tAH tCS H tC LK L SCK tF tDSW SDA Valid Data tR tDHW CS SCK SDA D7 D6 D5 D4 D3 D2 D1 D0 Figure 14- Serial Timing Characteristics (PS0 = L) SSD1828 Rev 1.10 07/2002 SOLOMON 35 Table 19 – Serial Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) Symbol Parameter Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time W rite Data Setup Time W rite Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time tcycle tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH tR tF Min 111 15 10 60 55.5 60 60 55.5 55.5 - Typ - Max 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns D/C (Required if PS1 = H) tAS CS tCSS t c ycle tC L KH tAH tCS H tC LK L SCK tF tDSW SDA Valid Data tR tDHW CS SCK SDA D7 D6 D5 D4 D3 D2 D1 D0 Figure 15 - Serial Timing Characteristics (PS0 = L) 36 SSD1828 Rev 1.10 07/2002 SOLOMON 12 APPLICATION EXAMPLES ICONS COM0 : : COM10 COM11 : : COM30 COM31 DISPLAY PANEL SIZE 96 X 64 + 1 ICON LINE COM32 COM33 : : : : : COM63 ICONS Remapped COM SCAN Direction [Command: C8] Remapped COM SCAN Direction [Command: C8 SEG95…………………………………………….………….SEG0 : : : : COM33 COM32 : : : : COM0 ICONS SEG95………………………………………………………………………SEG0 Remapped COM SCAN Direction [Command: C8 : : : : COM62 COM63 ICONS SSD1828 IC 64 MUX (DIE FACE IP) : : : : : COM30 COM31 Remapped COM SCAN Direction [Command: C8 C1 C2 SDA SCK VCI D/C /RES /CS VDD VOUT VSS where VDD&VCI=2.775V; C1 = 1uF ~ 2uF C2 = 0.22uF ~ 2.2uF Logic pin connections not specified above: Pins connected to VDD: E(#RD), R/W, D0~D5, PS1 Pins connected to VSS: PS0, CVSS, RVSS Figure 16 - Typical Application (4-wires SPI mode) SSD1828 Rev 1.10 07/2002 SOLOMON 37 Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part. 38 SSD1828 Rev 1.10 07/2002 SOLOMON