U62256

U62256 Standard 32K x 8 SRAM Features F 32768x8 bit static CMOS RAM F Access times 70 ns, 100 ns F Common data inputs and Description The U62256 is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a MIXMOS cell. The circuit is activated by the falling edge of E. The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0-DQ7. After the address change, the data outputs go High-Z until the new information read is available. The data outputs have not preferred state. The Read cycle is finished by the falling edge of W, or by the rising edge of E, respectively. Data retention is guaranteed down to 2 V. With the exception of E, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. data outputs F Three-state outputs F Typ. operating supply current 70 ns: 50 mA 100 ns: 40 mA F TTL/CMOS-compatible F Automatical reduction of power dissipation in long Read Cycles F Power supply voltage 5 V + 10 % F Operating temperature ranges 0 to 70 °C -40 to 85 °C F CECC 90000 Quality Standard F ESD protection > 2000 V (MIL STD 883C M3015.7) F Latch-up immunity >100 mA F Package: SOP28 (330 mil) Pin Configuration Pin Description A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 Signal Name A0 - A14 DQ0 - DQ7 E G W VCC VSS Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground SOP Top View November 01, 2001 1 U62256 Block Diagram A6 A7 A8 A9 A10 A11 A12 A13 A14 Row Address Inputs Row Decoder Memory Cell Array 512 Rows x 64 x 8 Columns Common Data I/O A0 A1 A2 A3 A4 A5 Column Address Inputs Column Decoder DQ0 Sense Amplifier/ Write Control Logic DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Address Change Detector Clock Generator Truth Table Operating Mode Standby/not selected Internal Read Read Write * H or L VCC VSS E W G E H L L L W * H H L G * H L * DQ0 - DQ7 High-Z High-Z Data Outputs Low-Z Data Inputs High-Z Characteristics All voltages are referenced to V SS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage. Maximum Ratings a Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Output Short-Circuit Current at VCC = 5 V and V O = 0 V c a Symbol VCC VI VO PD C-Type K-Type Ta Tstg | IOS | Min. -0.5 -0.5 -0.5 0 -40 -65 Max. 7 VCC + 0.5 b VCC + 0.5 b 1 70 85 125 200 Unit V V V W °C °C mA Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability b Maximum voltage is 7 V c Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. 2 November 01, 2001 U62256 Recommended Operating Conditions Power Supply Voltage Input Low Voltage d Symbol VCC VIL VIH Conditions Min. 4.5 -0.3 2.2 Max. 5.5 0.8 VCC + 0.3 Unit V V V Input High Voltage d -2 V at Pulse Width 30 ns Electrical Characteristics Supply Current - Operating Mode Symbol ICC(OP) VCC VIL VIH tcW tcW VCC VE VCC VE VCC IOH VCC IOL VCC VIH VCC VIL VCC VOH VCC VOL VCC VOH VCC VOL Conditions = = = = = 5.5 V 0.8 V 2.2 V 70 ns 100 ns Min. Max. Unit 70 65 50 mA mA µA Supply Current - Standby Mode (CMOS level) Supply Current - Standby Mode (TTL level) Output High Voltage Output Low Voltage Input High Leakage Current Input Low Leakage Current Output High Current Output Low Current Output Leakage Current High at Three-State Outputs Low at Three-State Outputs ICC(SB) = 5.5 V = VCC - 0.2 V = 5.5 V = 2.2 V = 4.5 V = -1.0 mA = 4.5 V = 3.2 mA = 5.5 V = 5.5 V = 5.5 V = 0V = = = = 4.5 V 2.4 V 4.5 V 0.4 V 2.4 ICC(SB)1 10 mA VOH VOL IIH IIL IOH IOL V 0.4 2 V µA µA -1 mA mA -2 3,2 IOHZ IOLZ = 5.5 V = 5.5 V = 5.5 V = 0V 2 -2 µA µA November 01, 2001 3 U62256 Switching Characteristics Read Cycle Read Cycle Time Address Access Time to Data Valid Chip Enable Access Time to Data Valid Output Enable Access Time to Data Valid E HIGH to Output in High-Z G HIGH to Output in High-Z E LOW to Output in Low-Z G LOW to Output in Low-Z Output Hold Time from Address Change Symbol Alt. tRC tAA tACE tOE tHZCE tHZOE tLZCE tLZOE tOH IEC tcR ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) 5 0 5 Min. 70 70 70 35 25 25 5 0 5 07 Max. Min. 100 100 100 45 35 35 10 Unit Max. ns ns ns ns ns ns ns ns ns Switching Characteristics Write Cycle Write Cycle Time Write Pulse Width Write Pulse Width Setup Time Address Setup Time Address Valid to End of Write Chip Enable Setup Time Pulse Width Chip Enable to End of Write Data Setup Time Data Hold Time Address Hold from End of Write W LOW to Output in High-Z G HIGH to Output in High-Z W HIGH to Output in Low-Z G LOW to Output in Low-Z Symbol Alt. tWC tWP tWP tAS tAW tCW tCW tDS tDH tAH tHZWE tHZOE tLZWE tLZOE IEC tcW tw(W) tsu(W) tsu(A) tsu(A-WH) tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) tdis(G) ten(W) ten(G) 0 0 Min. 70 55 55 0 65 65 65 30 0 0 07 Max. Min. 100 70 70 0 80 80 80 35 0 0 25 25 0 0 10 Unit Max. ns ns ns ns ns ns ns ns ns ns 35 35 ns ns ns ns 4 November 01, 2001 U62256 Data Retention Mode E-Controlled VCC VCC(DR) ≥ 2 V 2.2 V tDR 0V Data Retention trec 2.2 V E 4.5 V VCC(DR) - 0.2 V ≤ V E(DR) ≤ VCC(DR) + 0.3 V Data Retention Characteristics Data Retention Supply Voltage Data Retention Supply Current Data Retention Setup Time Operating Recovery Time Symbol Alt. IEC VCC(DR) ICC(DR) tCDR tR tsu(DR) trec Conditions Min. 2 Typ. Max. 5.5 30 Unit V µA ns ns VCC(DR) = 3 V VE = VCC(DR)-0.2V See Data Retention Waveforms (above) 0 tcR Test Configuration for Functional Check 5V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 VCC Simultaneous measurement of all 8 output pins Input level according to the VIH VIL relevant test measurement DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 960 VO 30 pF1) E W G VSS 510 1) In measurement of tdis(E), tdis(W), tdis(G), ten(E), ten(W), ten(G) the capacitance is 5 pF. November 01, 2001 5 U62256 Capacitance Input Capacitance Output Capacitance Conditions VCC VI f Ta = 5.0 V = VSS = 1 MHz = 25 °C Symbol CI CO Min. - Max. 7 7 Unit pF pF All pins not under test must be connected with ground by capacitors. IC Code Numbers Example Type U62256 S K 07 Package S = SOP28 (330 mil) Access Time 07 = 70 ns 10 = 100 ns Operating Temperature Ranges C = 0 to 70 °C K = -40 to 85 °C The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week. 6 November 01, 2001 U62256 Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH) tcR Ai DQi Output Previous Data Valid tv(A) Address Valid ta(A) Output Data Valid Read Cycle 2: G-, E-controlled (during Read Cycle: W = VIH) tcR Ai E G DQi Output High-Z tsu(A) ten(E) Address Valid ta(E) ta(G) ten(G) tdis(E) tdis(G) Output Data Valid November 01, 2001 7 U62256 Write Cycle1: W-controlled tcW Ai E W DQi Input tdis(W) tsu(A) Address Valid tsu(E) tsu(A-WH) tw(W) tsu(D) th(D) th(A) DQi Output Input Data Valid ten(W) High-Z G Write Cycle 2: E-controlled tcW Ai tsu(A) Address Valid th(A) tw(E) tsu(W) E W tsu(D) th(D) Input Data Valid DQi Input ten(E) tdis(W) High-Z tdis(G) DQi Output G undefined L- to H-level H- to L-level The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved. 8 November 01, 2001 U62256 LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. November 01, 2001 Zentrum Mikroelektronik Dresden AG Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: sales@zmd.de • http://www.zmd.de