U631H16BS1C25

U631H16 SoftStore 2K x 8 nvSRAM Features F Packages: F High-performance CMOS nonvolatile static RAM 2048 x 8 bits F 25, 35 and 45 ns Access Times F 12, 20 and 25 ns Output Enable Access Times F Software STORE Initiation (STORE Cycle Time < 10 ms) F Automatic STORE Timing F 10 STORE cycles to EEPROM F 10 years data retention in EEPROM F Automatic RECALL on Power Up F Software RECALL Initiation (RECALL Cycle Time < 20 µs) F Unlimited RECALL cycles from EEPROM F Unlimited Read and Write to SRAM F Single 5 V ± 10 % Operation F Operating temperature ranges: 5 PDIP28 (300 mil) PDIP28 (600 mil) SOP28 (300 mil) SOP24 (300 mil) Description The U631H16 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U631H16 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. F F F 0 to 70 °C -40 to 85 °C C ECC 90000 Quality Standard E SD characterization according MIL STD 883C M3015.7-HBM (classification see IC Code Numbers) Data transfers from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL ) operation) are initiated through software sequences. The U631H16 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Pin Configuration Pin Description n.c. n.c. A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 VCC W n.c. A8 A9 n.c. G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 SOP 19 24 18 17 16 15 14 13 VCC A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 Signal Name A0 - A10 DQ0 - DQ7 E G W VCC VSS Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground PDIP 22 SOP 21 28 20 19 18 17 16 15 Top View Top View 1 December 12, 1997 U631H16 Block Diagram EEPROM Array 32 x (64 x 8) STORE Row Decoder A5 A6 A7 A8 A9 SRAM Array 32 Rows x 64 x 8 Columns Store/ Recall Control VCC VSS RECALL VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Input Buffers Column I/O Column Decoder Software Detect A0 - A10 A0 A1 A2 A3 A4 A10 G E W Truth Table for SRAM Operations Operating Mode Standby/not selected Internal Read Read Write *H or L E H L L L W * H H L G * H L * DQ0 - DQ7 High-Z High-Z Data Outputs Low-Z Data Inputs High-Z Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the t dis-times and t en-times, in which cases transition is measured ± 200 mV from steady-state voltage. Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature C-Type K-Type Symbol VCC VI VO PD Ta Tstg Min. -0.5 -0.3 -0.3 Max. 7 VCC+0.5 VCC+0.5 1 Unit V V V W °C °C °C 0 -40 -65 70 85 150 a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 December 12, 1997 U631H16 Recommended Operation Conditions Power Supply Voltage Input Low Voltage Input High Voltage Symbol VCC V IL V IH -2 V at Pulse Width 10 ns permitted Conditions Min. 4.5 -0.3 2.2 Max. 5.5 0.8 VCC+0.3 Unit V V V C-Type DC Characteristics Operating Supply Currentb Symbol ICC1 VCC VIL VIH tc tc tc Average Supply Current during STOREc ICC2 VCC E W VIL VIH VCC E tc tc tc Average Supply Current at tcR = 200 nsb (Cycling CMOS Input Levels) Standby Supply Currentd (Stable CMOS Input Levels) ICC3 VCC W VIL VIH VCC E VIL VIH Conditions Min. = 5.5 V = 0.8 V = 2.2 V = 25 ns = 35 ns = 45 ns = 5.5 V ≥ VCC-0.2 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V = 5.5 V ≥ VIH = 25 ns = 35 ns = 45 ns = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 30 23 20 15 90 80 75 6 Max. K-Type Unit Min. Max. 95 85 80 7 mA mA mA mA Standby Supply Currentd (Cycling TTL Input Levels) ICC(SB)1 34 27 23 15 mA mA mA mA ICC(SB) 1 1 mA b: ICC1 a nd ICC3 a re dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. The current ICC1 is measured for WRITE/READ - ratio of 1/2. c: I CC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time). d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2. December 12, 1997 3 U631H16 C-Type DC Characteristics Symbol VCC IOH IOL VCC VOH VOL VCC High Low Output Leakage Current High at Three-State- Output Low at Three-State- Output IOHZ IOLZ IIH IIL VIH VIL VCC VOH VOL Conditions Min. Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current VOH VOL IOH IOL = 4.5 V =-4 mA = 8 mA = 4.5 V = 2.4 V = 0.4 V = 5.5 V = 5.5 V = 0V = 5.5 V = 5.5 V = 0V 1 -1 -1 1 µA µA 1 -1 -1 1 µA µA 2.4 0.4 -4 8 8 Max. Min. 2.4 0.4 -4 Max. V V mA mA K-Type Unit SRAM MEMORY OPERATIONS Symbol Alt. tAVAV Validg tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX Changeg tAXQX tELICCH tEHICCL IEC tcR ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) 5 0 3 0 25 Min. 25 25 25 12 13 13 5 0 3 0 35 25 Max. Min. 35 35 35 20 17 17 5 0 3 0 45 35 Max. 45 Unit Min. 45 45 45 25 20 20 Max. ns ns ns ns ns ns ns ns ns ns ns No. 1 2 3 4 5 6 7 8 9 Switching Characteristics Read Cycle Read Cycle Timef Address Access Time to Data Chip Enable Access Time to Data Valid Output Enable Access Time to Data Valid E HIGH to Output in G HIGH to Output in High-Z h High-Zh E L OW to Output in Low-Z G LOW to Output in Low-Z Output Hold Time after Addr. 19 Chip Enable to Power 11 Chip Disable to Power Activee Standbyd, e e: f: g: h: Parameter guaranteed but not tested. Device is continuously selected with E a nd G both LOW. Address valid prior to or at the same time with E transition LOW. Measured ± 200 mV from steady state output voltage. 4 December 12, 1997 U631H16 Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f 1 tcR Ai Address Valid 2 ta(A ) DQi Output Previous Data Valid 9 tv(A) AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA Output Data Valid Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g 1 tcR Ai Address Valid 2 ta(A ) 11 tPD 5 tdis(E) 3 E 7 ta(E) G DQi Output High Impedance 10 tPU ten(E) 4 ta(G) 8 ten(G) 6 tdis(G) AAAAAAAAAAA Output Data AAAAAAAAAAA AAAAAAAAAAA Valid AAAAAAAAAAA ICC ACTIVE STANDBY No. Switching Characteristics Write Cycle 12 Write Cycle Time 13 Write Pulse Width 14 Write Pulse Width Setup Time 15 Address Setup Time 16 Address Valid to End of Write 17 Chip Enable Setup Time 18 Chip Enable to End of Write 19 Data Setup Time to End of Write 20 Data Hold Time after End of Write 21 Address Hold after End of Write 22 W L OW to Output in High-Zh, i Symbol Alt. #1 Alt. #2 IEC 25 Min. Max. 35 Min. Max. 45 Unit Min. Max. t AVAV tWLWH tAVAV tcW tw(W) 25 20 20 0 20 20 20 12 0 0 10 5 35 30 30 0 30 30 30 18 0 0 13 5 45 35 35 0 35 35 35 20 0 0 15 5 ns ns ns ns ns ns ns ns ns ns ns ns tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL tAVEH tsu(W) tsu(A) tsu(A-WH) tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W) 23 W HIGH to Output in Low-Z December 12, 1997 5 U631H16 Write Cycle #1: W-controlledj 12 tcW Ai Address Valid 21 th(A ) E AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA 15 tsu(A ) 17 tsu(E) 16 tsu(A -WH) 13 tw(W) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA W DQi Input 19 tsu(D) Input Data Valid 20 th(D) DQi Output Previous Data 22 tdis(W) 23 ten(W) High Impedance AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA Write Cycle #2: E-controlledj 12 tcW Ai tsu(A ) 15 Address Valid 21 th(A) 18 tw(E) E W AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA 14 tsu(W) 19 tsu(D) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 20 th(D) Input Data Valid DQi Input DQi Output High Impedance AAAAAAAAAAAAA AAAAAAAAAAAAA undefined AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA L- to H-level AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA H- to L-level AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA i: j: If W is LOW and when E goes LOW, the outputs remain in the high impedance state. E o r W must be > VIH during address transitions. 6 December 12, 1997 U631H16 NONVOLATILE MEMORY OPERATIONS Symbol Min. Alt. tRESTORE VSWITCH 4.0 IEC 650 4.5 µs V Max. Unit No. STORE CYCLE INHIBIT and AUTOMATIC POWER UP RECALL 24 Power Up RECALL Durationk, e Low Voltage Trigger Level k: tRESTORE starts from the time V CC rises above VSWITCH. STORE CYCLE INHIBIT and AUTOMATIC POWER UP RECALL VCC 5.0 V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A VSWITCH A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA t STORE inhibit Power Up RECALL 24 tRESTORE SOFTWARE MODE SELECTION A10 - A0 (hex) 000 555 2AA 7FF 0F0 70F 000 555 2AA 7FF 0F0 70E E L W H Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Active Notes l, l, l, l, l, l, l, l, l, l, m m m m m l m m m m m l ICC2 Active L H l: The six consecutive addresses must be in order listed (000, 555, 2AA, 7FF, 0F0, 70F) for a Store cycle or (000, 555, 2AA, 7FF, 0F0, 70E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. The following six-address sequence is used for testing purposes and should not be used: 000, 555, 2AA, 7FF, 0F0, 39C. m: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G . December 12, 1997 7 U631H16 Symbol 25 Min. Max. Min. 35 Max. Min. 45 Unit Max. No. Software Controlled STORE/RECALL Cyclel, n 25 STORE/RECALL Initiation Time 26 Chip Enable to Output Inactiveo 27 STORE Cycle Timep 28 RECALL Cycle Timeq Alt. IEC tAVAV tELQZ tELQXS tELQXR tAVELN tELEHN tEHAXN tcR tdis(E)SR td(E)S td(E)R tsu(A)SR tw(E)SR th(A)SR 25 600 10 20 0 20 0 35 600 10 20 0 25 0 45 600 10 20 0 35 0 ns ns ms µs ns ns ns 29 Address Setup to Chip Enabler 30 Chip Enable Pulse Widthr, s 31 Chip Disable to Address Changer n: o: p: q: r: s: The software sequence is clocked with E c ontrolled READs. Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. Note that STORE cycles (but not RECALL) are aborted by V CC < VSWITCH (STORE inhibit). An automatic RECALL also takes place at power up, starting when V CC e xceeds VSWITCH and takes tRESTORE . VCC m ust not drop below VSWI TCH o nce it has been exceeded for the RECALL to function properly. Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence. If the Chip Enable Pulse Width is less than t a(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated. SOFTWARE CONTROLLED STORE/RECALL CYCLEr, s, t, u (E = H IGH after STORE initiation) AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA 25 tcR ADDRESS 1 25 tcR ADDRESS 6 Ai 30 30 31 th(A)SR 29 tsu(A)SR tw(E)SR 31 th(A)SR 5 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA 27 / 28 td(E)S / td(E)R E 29 tsu(A)SR High Impedance tw(E)SR t dis(E) DQi Output VALID VALID 26 tdis(E)SR AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA SOFTWARE CONTROLLED STORE/RECALL CYCLEr, s, t, u (E = LOW after STORE initiation) 25 tcR ADDRESS 1 30 tw(E)SR ADDRESS 6 31 th(A)SR 27 / 28 td(E)S / td(E)R Ai AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA E 29 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA 31 th(A )SR 29 tsu(A )SR t su(A)SR DQi Output High Impedance VALID VALID 26 tdis(E)SR W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U631H16 performs a STORE or RECALL. u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles. t: 8 December 12, 1997 U631H16 Test Configuration for Functional Check 5V VCCw A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 relevant test measurement Input level according to the Simultaneous measure- ment of all 8 output pins DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 480 VIH VIL VO 30 pF v 255 E W G VSS v: In measurement of tdis-times and ten-times the capacitance is 5 pF. w: Between VCC a nd VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances. Capacitancee Input Capacitance Output Capacitance Conditions VCC VI f Ta = 5.0 V = VSS = 1MHz = 25 °C Symbol CI CO Min. Max. 8 7 Unit pF pF All pins not under test must be connected with ground by capacitors. IC Code Numbers Example U631H16 Type ESD Class blank > 2000 Vx B > 1000 V Package D = PDIP28 (300 mil) D1= PDIP28 (600 mil) S = SOP28 (300 mil) S1= SOP24 (300 mil) Operating Temperature Range C = 0 to 70 °C K = -40 to 85 °C The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week. x: ESD protection > 2000 V under development B D C 25 Access Time 25 = 25 ns 35 = 35 ns (on special request) 45 = 45 ns (on special request) December 12, 1997 9 U631H16 Device Operation The U631H16 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. SRAM READ The U631H16 performs a READ cycle whenever E and G are LOW while W is HIGH. The address specified on pins A0 - A10 determines which of the 2048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E o r G, the outputs will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until ei-ther E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. NOISE CONSIDERATION The U631H16 is a high speed memory and therefore it must have a high frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal carefull routing of power, ground and signals will help prevent noise problems. SOFTWARE NONVOLATILE STORE The U631H16 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the U631H16 implements nonvolatile operation while remaining compatible with standard 2K x 8 SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 000 555 2AA 7FF 0F0 70F (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE parallel programming of all nonvolatile elements. Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the STORE cycle the following READ sequence must be performed: Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that G is LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SOFTWARE NONVOLATILE RECALL A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 000 555 2AA 7FF 0F0 70E (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. AUTOMATIC POWER UP RECALL On power up, once VCC exceeds the sense voltage of V SWITCH, a RECALL cycle is automatically initiated. The voltage on the VCC pin must not frop belwo VSWITCH once it has risen above it in order for the RECALL to operate properly. Due to this automatic RECALL, SRAM operation cannot commence until tRESTORE after VCC e xceeds VSWITCH. 10 December 12, 1997 U631H16 If the U631H16 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 KΩ resistor should be connected between W a nd VCC. HARDWARE PROTECTION The U631H16 offers hardware protection against inadvertent STORE operation through VCC sense. For VCC < V SWITCH the software initiated STORE operation will be inhibited. LOW AVERAGE ACTIVE POWER The U631H16 has been designed to draw significantly less power when E is LOW (chip enabled) but the access cycle time is longer than 55 ns. When E is HIGH the chip consumes only standby current. The overall average current drawn by the part depends on the following items: 1. CMOS or TTL input levels 2. the time during which the chip is disabled (E HIGH) 3. the cycle time for accesses (E LOW) 4. the ratio of READs to WRITEs 5. the operating temperature 6. the VCC level December 12, 1997 11 Memory Products 1998 SoftStore 2K x 8 nvSRAM U631H16 LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intend for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Zentrum Mikroelektronik Dresden GmbH Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Email: sales@zmd.de Internet Web Site: http://www.zmd.de