VT6516

VIA Technologies, Inc. Preliminary VT6516 Datasheet VT6516 16/12-PORT 10/100BASE-T/TX ETHERNET SWITCH CONTROLLER REVISION ‘E’ DATASHEET (Preliminary) ISSUE 1: July 31, 1999 VIA Technologies, Inc. 1 VIA Technologies, Inc. Preliminary VT6516 Datasheet PRELIMINARY RELEASE Please contact VIA Technologies for the latest documentation. Copyright Notice: Copyright © 1995, VIA Technologies Incorporated. Printed in Taiwan. ALL RIGHTS RESERVED. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. The VT86C100P may only be used to identify products of VIA Technologies. All trademarks are the properties of their respective owners. Disclaimer Notice: No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable to the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change. Offices: 1045 Mission Court Fremont, CA 94539 USA Tel: Fax: (510) 683-3300 (510) 683-3301 8th Floor, No. 533 Chung-Cheng Rd., Hsin-Tien Taipei, Taiwan ROC Tel: Fax: (886-2) 2218-5452 (886-2) 2218-5453 Online Services: BBS : 886-2-2186408 FTP : FTP.VIA.COM.TW HTTP:WWW.VIA.COM.TW –or- WWW.VIATECH.COM 2 VIA Technologies, Inc. Preliminary VT6516 Datasheet TABLE OF CONTENTS TABLE OF CONTENTS ................................................................................................................................ 3 FIGURES AND TABLES ............................................................................................................................... 4 REVERSION HISTORY ................................................................................................................................ 5 FEATURES ................................................................................................................................................ 6 BLOCK DIAGRAM...................................................................................................................................... 9 BALL OUT DIAGRAM ............................................................................................................................... 11 RMII-mode Ball out Diagram ........................................................................................................... 11 MII-mode Ballout Diagram............................................................................................................... 12 LOGIC SYMBOL ...................................................................................................................................... 13 PIN DESCRIPTIONS .................................................................................................................................. 14 JUMPER STRAPPING................................................................................................................................. 18 SECTION I FUNCTIONAL DESCRIPTIONS...................................................................................... 19 1. GENERAL DESCRIPTION ...................................................................................................................... 19 2. THE VIA ETHER SWITCH ARCHITECTURE ............................................................................................ 19 2.1 Switch initialization procedures .................................................................................................. 19 ù! ¥¼¸®ÑÒ 2.2 Packet receiving and forwarding follow .......................................¿ » ~ © | © w q Å ¡ C 3. INTERFACE DESCRIPTIONS................................................................................................................... 20 3.1 Buffer Memory (SDRAM) Interface and Table (SRAM) interface..¿ » ~ © | © w q Å ¡ C ù! ¥¼¸®ÑÒ 4. FUNCTIONAL DESCRIPTION ................................................................................................................. 33 4.1 Packet Reception and Address recognition.................................................................................. 33 4.2 Packet Forwarding and VLAN..................................................................................................... 33 4.3 Network Management Features................................................................................................... 34 SECTION II REGISTER MAP............................................................................................................... 36 1. REGISTER TABLES ............................................................................................................................. 36 2 CPU INTERFACE REGISTERS MAP ......................................................................................................... 36 3 SWITCH INTERNAL REGISTERS MAP ..................................................................................................... 37 4. DETAIL OF SWITCH REGISTER.............................................................................................................. 44 4.1 Registers of SDRAM Control Module......................................................................................... 44 4.2 Registers of SRAM Control Module............................................................................................ 46 4.4 Registers of Buffer Control Module............................................................................................. 48 4.5 Registers of Forwarding Control Module ................................................................................... 49 4.6 Registers of PHY Control Module .............................................................................................. 53 4.7 Registers of EEPROM Control Module ....................................................................................... 55 4.8 Registers of CPU Interface Module............................................................................................. 56 4.9 Registers of MAC/IO Control Module ......................................................................................... 59 4.10 Registers of CPU IO Control Module....................................................................................... 63 SECTION III ELECTRICAL SPECIFICATIONS................................................................................. 65 ABSOLUTE MAXIMUM RATINGS............................................................................................................... 65 DC CHARACTERISTICS............................................................................................................................ 65 AC CHARACTERISTICS............................................................................................................................ 65 PACKAGE MECHANICAL SPECIFICATIONS ................................................................................................. 73 3 VIA Technologies, Inc. Preliminary VT6516 Datasheet FIGURES AND TABLES Figure 1: Block Diagram .............................................................................................9 Figure 3-3 .................................................................................................................22 Figure 3-6: Algorithm of Initialization of Free Link Lists. ..........................................22 Figure 3-1 SRAM......................................................................................................26 Figure 3-2 Free buffer link structure ..........................................................................27 Table 1-0 Free buffer link structure............................................................................27 Figure 3-5 The Address table entries structure +........................................................27 Table 1-1 Address table structure ..............................................................................28 Table 3-1 RMII interface signals................................................................................30 Figure 3-1 RMII timing diagram................................................................................30 Table 3-2 MII interface signals ..................................................................................31 Figure 3-2 MII timing diagram ..................................................................................31 4 VIA Technologies, Inc. Preliminary VT6516 Datasheet REVERSION HISTORY Reversion V0.90 V0.91 V0.92 V0.93 Date 2/18/1999 6/2/1999 8/23/1999 9/9/1999 Reason for change First release version Add D version silicon features modification Add E version silicon features modification Revision according to Weipin’s, Kevin’s, and Ruth’s comments By JeffreyChang JeffreyChang MurphyChen MurphyChen 5 VIA Technologies, Inc. Preliminary VT6516 Datasheet FEATURES l l l l l l l l l l l Single chip 16/12 ports 10/100M Ethernet switch controller - Highly integrated single chip shared memory switch engine - With option for 16 RMII (Reduced Media Independent Interface) ports or 12 MII (Media Independent Interface) ports - Non-blocking layer 2 switch, 148,810 packets/sec on each 100Mbps Ethernet port Media Access Control (MAC) - Dual 192-bytes FIFO’s of receive and transmit for each port - CRC generator for outgoing packets from CPU port - IEEE 802.3X compliant flow control for full duplex ports - Backpressure for half duplex ports Two switching mechanisms - Supports ‘store and forward’ switching without forwarding CRC-bad packets - Supports ‘cut through’ switching subject to long packets of length over 290 bytes for 100Mbps ports or of length over 98 bytes for 10Mbps ports Packet buffering - Glueless 64-bit interface to SDRAM as a packet buffer pool with size from 2M bytes (SGRAM) to 512 M bytes - 1536 bytes for each packet buffer External 32 bits SSRAM interface for forwarding table and memory link table - Link list structure initialized by software - 2K up to 32K unicast/multicast addresses table entries with VLAN information - Supports static entries for upper-layer multicast protocols, e.g. IGMP Advanced address recognition - Layer 2 MAC address recognition engine to enable wire-speed forwarding rate - Self learning mechanism - Supports multiple MAC address per-port from 2K up to 32K unicast/multicast addresses Switch management support - Supports port mirroring (Sniffer feature) - Supports spanning tree algorithm - Supports CPU direct access to SDRAM and SSRAM - Supports five statistical counters in each port Supports I2C EEPROM interface for customized configuration Support port-grouping VLAN - Configurable server ports belonging to multiple VLAN groups Support port-based trunking - Three types of trunk grouping: one trunk group with 2 or 4 ports, two trunk groups each with 2 ports - Load balance according to MAC address and port number CPU interface VIA 8/16 bits ISA-like interface 6 VIA Technologies, Inc. Preliminary VT6516 Datasheet l l l l l Chip initialization, auto-aging and spanning tree algorithm support by firmware Auto-sensing 10/100M media speed, duplex mode, and flow-control capability by firmware 50MHz internal reference clock rate 50~100MHz SDRAM clock rate, typically 83MHz 50~100MHz SSRAM clock rate, typically 83MHz Single +3.3V supply, 0.3µm standard CMOS technology 476 ball BGA package - 7 VIA Technologies, Inc. Preliminary VT6516 Datarsheet BLOCK DIAGRAM SRAM control CPU interface forwarding control buffer control queue control scheduler input control output control SDRAM control RMAC TMAC Figure 1: Block Diagram 99/12/09 9 VIA Technologies, Inc. Preliminary VT6516 Datarsheet BALL OUT DIAGRAM RMII-mode Ball out Diagram A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 CSDV2 CRS.D V1 RXD1.2 TXD1.2 TXEN2 RXD0.2 TXD1.3 CSDV3 RXD0.3 TXD0.3 RXD1.4 TXD0.4 RXD0.5 TXD1.5 TXD0.6 CSDV6 RXD1.7 CSRV7 RXD1.8 TXD0.8 TXD1.9 RXD0.9 RXD1.1 0 RXD0.1 1 TXD1.1 1 TXD0.1 2 CSDV1 2 RXD1.1 3 CSDV1 3 RXD1.1 4 RXD0.1 4 TXEN1 4 CSDV4 RXD1.5 RXD0.6 TXD1.6 TXD0.7 TXD1.7 TXD1.8 RXD0.8 RXD1.9 RXD0.1 0 TXD1.1 0 TXD0.1 1 CSDV1 1 RXD1.1 2 RXD0.1 3 TXEN1 3 CSDV1 4 TXD0.1 4 CSDV1 5 TXD1.1 5 3 4 5 6 7 RXD1.1 TXEN1 TXD1.0 RXD0.0 MD1 TXD1.1 TXD0.2 TXEN3 RXD1.3 RXD0.4 TXD1.4 TXD0.5 CSDV5 RXD1.6 RXD0.7 TXEN7 CSDV8 CSDV9 TXD0.9 TXD0.1 0 CSDV1 0 RXD1.1 1 RXD0.1 2 TXD1.1 2 TXD0.1 3 TXD1.1 3 TXD1.1 4 RXD1.1 5 TXD0.1 5 RXD0.1 5 RXD0.1 TXD0.1 NC NC TXEN4 CSDV0 TXEN0 NC VDDI RCLK5 0 VDD VDD VDD NC GND GND NC NC VDD VDD TXD0.0 RXD1.0 NC GNDI VDDI GND VDD MD32 MD0 MD33 GND GND 8 MD3 MD34 MD2 GND MD35 NC 9 MD5 MD36 MD4 MD37 VDD 10 MD7 MD38 MD6 MD39 VDD 11 MD9 MD40 MD8 MD41 VDD 12 MD11 MD42 MD10 MD43 MD12 13 MD45 MD14 MD46 MD13 MD44 14 MD47 CAS1 CAS0 MD15 GND 15 RAS0 MA0 MA1 RAS1 GND 16 MA3 MA4 MA5 MA2 GND 17 MA7 MA8 MA9 MA6 VDD 18 MA11 BA0 BA1 MA10 VDD 19 DCS2 DCS1 DCS0 DCS3 VDD NC 20 DWE0 DWE1 MD16 MD48 MD17 GND 21 MD49 MD18 MD50 MD19 MD51 GNDI GND NC 22 MD20 MD52 MD21 MD53 GNDI VDDI SCLK SD23 VDD VDD VDD SA10 SA15 GND GND SD11 VPP VPP GND GNDI VDDI VDD NC NC NC NC VDD VDD NC NC NC NC VDD NC NC NC NC NC VPP NC NC NC NC VPP NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND NC NC NC NC GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC VPP NC NC NC NC VPP NC GND VPP GND GND GNDI GND 23 MD22 MD54 MD23 MD55 DCLK MD63 SD19 SD24 SD31 SA4 SA3 SA11 SA16 SD0 SD4 SD12 24 MD24 MD56 MD25 MD60 MD30 SD16 SD20 SD25 SD28 SA6 SA2 SA12 SA17 SD3 SD7 SD10 25 MD57 MD26 MD59 MD29 MD62 SD17 SD21 SD26 SD29 SA7 SA13 SA13 SA9 SD2 SD6 SD9 SD14 26 MD58 MD27 MD28 MD61 MD31 SD18 SD22 SD27 SD30 SA5 SA0 SA14 SA8 SD18 SD5 SD8 SD13 TXEN5 NC NC TXEN6 NC NC TXEN8 TXEN9 NC TXEN1 0 NC VDD TXEN1 VDD 1 TXEN1 NC 2 NC GND NC NC NC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SADS# SD15 SOE# SCS1# SCS0# SWE# HCS# SCS4# HA2 IOR# HD14 HD12 HD10 HD7 SCS3# SCS2# HA0 HCLK GNDI GND HD15 HD1 HD3 INTRQ HA1 HD0 HD13 HD11 IOW# HD2 HD4 HD6 GNDI VDDI EEC TEST12 VDDI TEST7 TEST11 TEST16 TEST17 HD5 TXEN1 EEIO 5 MDC NC MDIO NC TEST3 TEST6 TEST10 TEST15 TEST20 TEST23 HD9 TEST2 TEST5 TEST9 TEST1 TEST4 TEST8 TEST14 TEST19 TEST22 TEST25 HD8 TEST13 TEST18 TEST21 TEST24 TEST26 RESET # 99/12/09 11 VIA Technologies, Inc. Preliminary VT6516 Datarsheet MII-mode Ballout Diagram A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 CRS1 2 3 RXD3_ COL0 0 RXD1_ RXDV0 TXD3_ 1 0 TXEN1 TXD1_ TXD0_ 1 1 TXD3_ RXD0_ COL1 1 1 RXD2_ RXDV1 RXD3_ 1 1 RXD1_ TXD2_ RXD0_ 2 1 2 RXD2_ TXD0_ TXD1_ 2 2 2 TXD3_ CRS2 TXD2_ 2 2 TXD0_ RXD3_ RXDV2 3 2 RXD0_ CRS3 TXD1_ 3 3 RXD3_ TXD2_ RXD2_ 3 3 3 RXDV3 TXD3_ COL3 3 TXD0_ RXD1_ TXD1_ 4 4 4 TXD3_ RXD0_ RXDV4 4 4 RXD2_ RXD3_ TXD2_ 4 4 4 RXD1_ RXD0_ TXD0_ 5 5 5 RXD2_ TXD1_ CRS5 5 5 TXD3_ TXD2_ RXD3_ 5 5 5 TXD0_ RXDV5 RXD0_ 6 6 CRS6 RXD1_ TXD1_ 6 6 RXD3_ RXD2_ TXD2_ 6 6 6 RXDV6 COL6 TXD3_ 6 RXD1_ CRS7 TXD1_ 7 7 RXD0_ TXD0_ RXD3_ 7 7 7 TXEN7 RXDV7 TXD2_ 7 TXD3_ RXD2_ MDIO 7 7 4 TXD1_ 0 RXD2_ 0 TXD2_ 0 NC NC 5 6 RXD0_ MD1 0 CRS0 TXD0_ 0 TXEN0 RXD1_ 0 NC NC VDD GND 7 MD32 MD0 MD33 MD3 VSS VSS 8 MD34 MD2 MD35 VSS MD5 NC 9 MD36 MD4 MD37 MD7 VCC 10 MD38 MD6 MD39 MD9 VCC 11 MD40 MD8 MD41 MD11 VCC 12 MD42 MD10 MD43 MD12 MD45 13 MD14 MD46 MD13 MD44 MD47 14 15 CAS1# MA0 CAS0# MA1 MD15 16 MA4 MA5 17 MA8 MA9 MA6 MA11 VCC 18 BA0 BA1 MA10 19 20 21 DCS1# DWE1# MD18 DCS0# MD16 DCS3# MD48 MD50 MD19 MD51 NC GND VSS NC 22 MD20 MD52 MD21 MD53 GND VDD SCLK SD23 VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC SA10 SA15 VSS VSS SD11 VCC VCC VSS GND VCC VCC VCC NC VCC RXD2_ 9 RXD1_ 9 RXD0_ 9 RXDV9 VCC RCLK9 TXEN9 TXD0_ 9 TXD1_ 9 TCLK9 RXD3_ 10 TXD2_ RXD2_ 9 10 TXD3_ RXD1_ 9 10 COL9 RXD0_ 10 CRS9 RXDV1 0 VSS RCLK1 0 TXEN1 0 TXD0_ 10 TXD1_ 10 VSS TCLK1 0 TXD2_ 10 TXD3_ 10 COL10 CRS10 RCLK1 1 RXD3_ RXDV1 11 1 RXD2_ TXEN1 11 1 RXD1_ TXD0_ 11 11 RXD0_ TXD1_ 11 11 VCC TCLK1 1 TXD2_ 11 TXD3_ 11 COL11 VCC VSS VCC VSS VSS 23 MD22 MD54 MD23 MD55 DCLK MD63 SD19 SD24 SD31 SA4 SA3 SA11 SA16 SD0 SD4 SD12 24 MD24 MD56 MD25 MD60 MD30 SD16 SD20 SD25 SD28 SA6 SA2 SA12 SA17 SD3 SD7 SD10 25 MD57 MD26 MD59 MD29 MD62 SD17 SD21 SD26 SD29 SA7 SA1 SA13 SA9 SD2 SD6 SD9 SD14 26 MD58 MD27 MD28 MD61 MD31 SD18 SD22 SD27 SD30 SA5 SA0 SA14 SA8 SD1 SD5 SD8 SD13 RAS1# MA2 MA7 VSS RAS0# MA3 VSS VSS DCS2# DWE0# MD17 VCC VCC NC MD49 VSS TXEN2 RCLK5 VDD 0 COL2 VCC VSS RCLK2 VCC TCLK2 VCC RXD1_ TXEN3 3 RCLK3 VSS TCLK3 VSS CRS4 COL4 TXEN4 RCLK4 VCC TCLK4 VCC TXEN5 VCC TCLK5 VCC COL5 VCC SADS# SD15 SOE# SCS1# SCS0# SWE# HCS# SCS4# HA2 IOR# HD14 HD12 HD10 HD7 TXEN6 RCLK5 VSS TCLK6 VSS RCLK6 GND TCLK7 VDD RCLK7 EEC COL7 GND VDD VCC SCS3# SCS2# HA0 HCLK GND VSS HD15 HD1 HD3 INTRQ HA1 # HD0 IOW# HD13 HD11 HD2 HD4 HD6 TEST12 VDD RCLK8 TCLK8 RXD3_ 9 RXD0_ TXD0_ TXD3_ 8 8 8 MDC RXD2_ RXDV8 TXD1_ COL8 8 8 RXD3_ RXD1_ TXEN8 TXD2_ CRS8 8 8 8 EEIO CRS11 TEST7 TEST11 TEST16 TEST17 HD5 TEST3 TEST6 TEST10 TEST15 TEST20 TEST23 HD9 TEST2 TEST5 TEST9 TEST1 TEST4 TEST8 TEST14 TEST19 TEST22 TEST25 HD8 TEST13 TEST18 TEST21 TEST24 TEST26 RESET # 99/12/09 12 VIA Technologies, Inc. Preliminary VT6516 Datarsheet LOGIC SYMBOL HA[2:0] HD[15:0] HCS IOR IOW INTRQ TCLK[11:0] TXD0[11:0] TXD1[11:0] TXD2[11:0] TXD3[11:0] TXEN[11:0] COL[11:0] CRS[11:0] RXD0[11:0] RXD1[11:0] RXD2[11:0] RXD3[11:0] RCLK[11:0] RXDV[11:0] 3 16 VT6516 HOST Interface SDRAM Interface 64 12 2 2 2 2 4 MD[63:0] MA[11:0] BA[1:0] RAS[1:0] CAS[1:0] DWE[1:0] DCS[3:0] SD[31:0] SA[17:0] SCS[4:0] SADS SOE SWE EEC EEIO 12 12 12 12 12 12 12 12 12 12 12 12 12 12 32 18 SRAM Interface MII Interface 5 Miscellaneous Interface MDC MDIO RCLK50 DCLK SCLK HCLK RESET 26 CRS_DV[15:0] RXD0[15:0] RXD1[15:0] 16 16 16 RMII Interface TEST[26:1] TXEN[15:0] TXD0[15:0] TXD1[15:0] 16 16 16 -13- VIA Technologies, Inc. Preliminary VT6516 Datarsheet PIN DESCRIPTIONS No. See Ball Table See Ball Table See Ball Table See Ball Table See Ball Table See Ball Table See Ball Table Name MD[63:0] Type SDRAM Interface I/O SDRAM Data: 64-bit SDRAM data bus. These signals connect directly to the data input/output pins of the SDRAM devices. SDRAM Address Bus: 12-bit SDRAM data bus. These signals connect directly to the address input of the SDRAM devices. Bank Identifier for Bank 0 and 1: Row Address Strobes for Bank 0 and 1: DRAM row address strobes. RAS [0] is used for Bank 0. RAS [1] is used for Bank 1. CAS [1:0] Description MA[11:0] O BA[1:0] RAS [1:0] O O O Column Address Strobes for Bank 0 and 1: DRAM column address strobes. CAS [0] is used for Bank 0. CAS [1] is used for Bank 1. DWE [1:0] DCS [3:0] O O DRAM Write Enable for Bank 0 and 1: DRAM Chip Select: VT-3061A supports at most 4 SDRAM DIMM modules. SRAM Interface SRAM Data: 32-bit SRAM data bus. These signals connect directly to the data input/output pins of the SRAM devices. SRAM Address Bus: 18-bit SDRAM data bus. These signals connect directly to the address input of the SDRAM devices. SRAM Chip Select: SRAM Type Chip Select Pins ------------------------------------32KBx32 SCS[0] & SA[15] 64KBx32 SCS[0] & SA[16] 128KBx32 SCS[0] & SA[17] 256KBx32 SCS[0] Synchronous Processor Address Status Output Enable SRAM Write Enable: Miscellaneous Interface Address Pins -----------------SA[14:0] SA[15:0] SA[16:0] SA[17:0] See Ball Table See Ball Table See Ball Table SD[31:0] I/O SA[17:0] O SCS [4:0] O See Ball Table See Ball Table See Ball Table SADS [1:0] SOE [1:0] SWE [1:0] O O O -14- VIA Technologies, Inc. See Ball Table EEC O Preliminary VT6516 Datarsheet Serial EEPROM Interface Clock Output: EEPROM Device Addressing in the demo board: PAGE 0 (EEPROM): Device Address = 1010 000 XXXXXXXX PAGE 1 (EEPROM): Device Address = 1010 001 XXXXXXXX PAGE 2 (EEPROM): Device Address = 1010 010 XXXXXXXX PAGE 3 (EEPROM): Device Address = 1010 011 XXXXXXXX PAGE 4 (SDRAM BANK-0): Device Address = 1010 100 XXXXXXXX PAGE 5 (SDRAM BANK-1): Device Address = 1010 101 XXXXXXXX Serial EEPROM Interface Data I/O Management Interface (MI) Clock Output Management Interface (MI) Data I/O Main Reference Clock: SDRAM Reference Clock: SRAM Reference Clock HOST Reference Clock HCLK is determined by the strapping pins in SYSLED[3:1], i.e. the jump selection of J1[5-6, 3-4, 1-2]: J1[OFF,OFF,OFF] => 8MHz J1[ OFF,OFF, ON] => 16MHz J1[OFF, ON, OFF] => 25MHz J1[OFF, ON, ON] => 4MHz J1[ ON,OFF,OFF] => 33MHz SYSTEM RESET SYSTEM Output Pins for LED: SYSLED[8:0] are connected to pull-up IO PADs for strapping. SYSLED[25:9] are connected to IO PADs without pull up/down. All SYSLED[25:0] are HOST Interface See Ball Table See Ball Table See Ball Table See Ball Table See Ball Table See Ball Table See Ball Table EEIO MDC MDIO RCLK50 DCLK SCLK HCLK I/O O I/O I I I O See Ball Table See Ball Table RESET I O SYSLED[26:0 ] -15- VIA Technologies, Inc. See Ball Table HA[2:0] I Preliminary VT6516 Datarsheet HOST IDE-Interface Address Bus: 3’b000: command the switch that the whole 16-bit data in the HOST data bus HD[15:0] is valid for packet-data read/write. 3’b001: command the switch that only the 8-bit data in the HOST data bus HD[15:0] is valid for internal registers read/write. 3’b010: command the switch to write the low byte in the HOST data bus HD[15:0] into the low byte of the 16-bit switch address register for internal registers reference. 3’b011: command the switch to write the low byte in the HOST data bus HD[15:0] into the high byte of the 16-bit switch address register for internal registers reference. 3’b1xx: bus-idle command. Keep this address bus to be 3’b111 as the HOST has no access to VT-3061A. HOST IDE-Interface Data Bus: The whole 16-bit data bus is valid for packet data read/write. However, only the 8-bit data bus is valid for internal registers read/write. HOST Chip Select: Active LOW. HCS must be asserted during the access of HOST IDE interface. See Ball Table See Ball Table See Ball Table See Ball Table See Ball Table HD[15:0] I/O HCS I IOR I IO READ: High-to-Low Edge Trigger. IOR must be asserted from high to low to begin the read cycle of HOST IDE interface. IOW I IO READ: High-to-Low Edge Trigger. IOW must be asserted from high to low to begin the write cycle of HOST IDE interface. INTRQ O Interrupt Request: Connected to the HOST external interrupt pin. It is asserted as the following four interrupt events happen: (1) MII Management Registers read/write command done (2) EEPROM read/write command done (3) Receiving a packet destined to HOST (4) Finishing transmission of a packet issued by HOST The interrupt cause is recorded in register IRQSTS[3:0] in address 2000H. To clear the individual interrupt, The corresponding register has to be written: (1) register CLR_PHY_INT in 1806H for PHY interrupt. (2) register CLR_EE_INT in 1C04H for EEPROM interrupt. (3) register CLR_RCV_INT in 6403H for packet-receiving interrupt. l register CLR_SENT_INT in 6411H for packet-sent interrupt. MII Interface See Ball TCLK[11:0] Table I Transmit Clock for Port 0-11: TCLK is driven by the PHY device. TCLK is a continuous clock that provides the timing reference for the transfer of the TXEN and TXD signals to the PHY. A PHY operating at 100Mbps must provide a TCLK frequency of 25MHz and a PHY operating at 10Mbps must provide a TCLK frequency of 2.5MHz. -16- VIA Technologies, Inc. See Ball Table TXD[11: 0] O Preliminary VT6516 Datarsheet Transmit Data for Port 0-11: TXD is a bundle of 4 data signals (TXD) that shall transition to the TCLK. For each TCLK period in which TXEN is asserted, TXD are accepted for transmission by the PHY. TXD is the least significant bit. While TXEN is de-asserted, TXD shall have no effect upon the PHY, and the value of TXD is unspecified. Transmit Enable for Port 0-11: TXEN shall transition synchronous to the TCLK. TXEN indicates the nibbles presenting on the MII for transmission. It shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all nibbles to be transmitted are presented to the MII. Collision Detected for Port 0-11: COL shall be asserted by the PHY asynchronously upon detection of a collision on the medium, and shall remain asserted while the collision condition persists. Carrier Sense for Port 0-11: CRS shall be asserted by the PHY asynchronously upon detection of a non-idle medium or while TX_EN is asserted. CRS shall be de-asserted by the PHY asynchronously upon detection of idle conditions on both transmit and receive media. The PHY shall ensure that CRS remains asserted throughout the duration of a collision condition. Receive Data for Port 0-11: RXD is a bundle of 4 data signals (RXD) that shall transition to the RCLK. For each RCLK period in which RXDV is asserted, RXD from the PHY are accepted by the switch’s MAC. RXD is the least significant bit. While RXDV is de-asserted, RXD shall have no effect upon the switch’s MAC, and the value of RXD is unspecified. Receive Clock for Port 0-11: RCLK is sourced from the PHY. RCLK is a continuous clock that provides the timing reference for the transfer of the RXDV and RXD signals from the PHY. A PHY operating at 100Mbps must provide a RCLK frequency of 25MHz and a PHY operating at 10Mbps must provide a RCLK frequency of 2.5MHz. Receive Data Valid for Port 0-11: RXDV is driven by the PHY to indicate the nibbles presenting on the MII for receiving. RXDV shall transition synchronous to the RCLK. It shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all nibbles to be received are presented to the MII. See Ball Table TXEN[11:0] O See Ball Table COL[11:0] I See Ball Table CRS[11:0] I See Ball Table RXD[11 :0] I See Ball Table RCLK[11:0] I See Ball Table RXDV[11:0] I Note: Some flat MII input pin when the VT6516 under the RMII application, please use 22 ohm resister pull down, refer to Table XXXX -17- VIA Technologies, Inc. RMII interface See Ball CRS_DV[15:0 Table ] See Ball RXD0[15:0] Table See Ball RXD1[15:0] Table See Ball TXEN[15:0] Table See Ball TXD0[15:0] Table See Ball TXD1[15:0] Table Power Supply & Ground See Ball VDD, VDDA Table See Ball VSS, VSSA Table Preliminary VT6516 Datarsheet I I I O O O Carries sense and data valid from port 15 to port 0 : Receive data zero from port 15 to port 0 : Receive data one from port 15 to port 0 : Transmit enable from port 15 to port 0 : Transmit data zero from port 15 to port 0 : Transmit data one from port 15 to port 0 : P G Positive 3.3V Supply: Supply power to Internal digital logic, Digital I/O pads, and TD, TX pads. Double bonding may be required. Negative Supply: digital ground. Multiple bonding pads are required to separate core and I/O pads ground. JUMPER STRAPPING Jumper Pin Description HOST Clock J1 [5-6], [3-4], [1- SYSLED[3: HOST Clock (HCLK) Rate Selection: 2] 1] J1[OFF,OFF,OFF] (SYSLED[3:1]==3’b111) => 8MHz J1[ OFF,OFF, ON] (SYSLED[3:1]==3’b110) => 16MHz J1[OFF, ON, OFF] (SYSLED[3:1]==3’b101) => 25MHz J1[OFF, ON, ON] (SYSLED[3:1]==3’b100) => 4MHz J1[ ON,OFF,OFF] (SYSLED[3:1]==3’b011) => 33MHz PHY Mode J1 [7-8] SYSLED[4] PHY Device Selection: J1[OFF] (SYSLED[4]==1’b1) => RMII PHY J1[ ON] (SYSLED[3:1]==1’b0) => MII PHY SRAM Type J1 [11-12,9-10] SYSLED[6: SRAM Device Type Selection: 5] J1[OFF,OFF] (SYSLED[6:5]==2’b11) => 64K x 32 SRAM J1[OFF,ON] (SYSLED[6:5]==2’b10) => 128K x 32 SRAM J1[ON,OFF] (SYSLED[6:5]==2’b01) => 32K x 32 SRAM -18- VIA Technologies, Inc. Preliminary VT6516 Datarsheet SECTION I FUNCTIONAL DESCRIPTIONS 1. GENERAL DESCRIPTION The VT6516 is a switch engine chip implementation of a 16 ports 10/100M Ethernet switch system for IEEE 802.3 and IEEE 802.3u network. Each of individual port can be either auto-sensing or manually selected to run at 10Mbps or 100Mbps speed rate and under full or half duplex mode. There are sixteen independent MACs within the VT6516 chip. The MAC controller controls the receiving, transmitting, and deferring of each individual port, and the MAC controller also provides framing, FCS checking, error handling, status indication and flow control function. The VT6516 10/100M N-way switch port IC is wire-speed performance and low-cost packet switch; it can forward up to 148,810 packets/sec on each Ethernet port. The VT6516 support 12 ports MII or 16 ports RMII (reduce MII) interface for network interface, The VT6516 used the simple 8/16 bits ISA-like interface to support initiation, expansion and management. The system CPU can access various registers inside VT6516 through a simple ISA-like CPU interface. The CPU can configure the switch by writing into the appropriate registers, or retrieve the status of the switch by reading the corresponding registers. The CPU can also access the register of external transceiver (PHY) device through the CPU interface. The VT6516 supports new features including port based VLAN , 802.3X flow control, and the VT6516 also support the sniffer function to monitor network traffic in special ports. 2. THE VIA ETHER SWITCH ARCHITECTURE The VT6516 switch engine uses the shared memory architecture. In order to improve the packet latency, VT6516 provides two methods for packet switching, one is cut-through, another is store-and-forwarding. A typical packet flow for Ethernet switch is described as follows in 4.5. 2.1 Switch initialization procedures 1. Test all of the on board components except the switch chip or access VIA the switch chip, including UART, LED, etc. 2. Switch SDRAM test --- switch chip SDRAM control hardware initialization, configuration, SDRAM size determination (VIA embedded EEPROM in SDRAM module) and read write test. 3. Switch SRAM test --- switch chip SDRAM control hardware initialization and read write test. Note that the SRAM size determination is VIA strapping. 4. Switch IO registers read write test. 5. Ethernet PHY registers read write test ---- the CPU read/write to PHY devices will go through PHY control in switch chip. Although they are outside components, but we test them as part of the switch chip. 6. Determine link table size; reset free buffer list pointers of bank 0 and 1; initialize free memory block counter. Note that permanent buffer management is controlled by allocating bit mask. They will be cleared automatically in the hardware reset or software reset. 2.2 Packet Switching Flow 1. After the switch microprocessor activates a port during initialization, the input control of that port preallocates one packet buffer from buffer pool. In the beginning, the buffer allocated will be from private buffer pool, but subsequent buffers may come from either private or public buffer pools. -19- VIA Technologies, Inc. Preliminary VT6516 Datarsheet 2. When receive MAC (RMAC) receives a packet data from the network interface – either through MII or reduced MII (RMII) – it packs the data into 16-bit word then passes it to input control. If RMAC detects any error, it also notifies input control to stop forwarding process. 3. Input control extracts the destination MAC address from incoming data, passes it along to forwarding table control for forwarding decision. In the mean while, it packs 16-bit words into 64-bit quad-words, and saves it to an input FIFO before storing the packet data to SDRAM. 4. If the switch is configured to “store and forward” mode, input control queues the packet to the output queue of the destination port after input control is informed by RMAC that this is a good packet and it stores all packet data to SDRAM. If the switch is configured to “cut-through” mode, the input control queues the packet to the output queue of the destination port after enough amount of packet is stored in SDRAM to prevent output FIFO under-run. 5. After the whole packet is received and FCS is correct, input control pass the source MAC address of the packet to forwarding table control for address learning. 6. Output control of the outbound port de-queue the packet from output queue, and fetch packet data from SDRAM and save it into output FIFO. Then it notifies the transmit MAC (TMAC) of the new packet to transmit. 7. TMAC grabs 16-bit at a time from output control, adds preamble and SFD to the beginning of the packet, then send them out. Proper deferring is done if necessary to conform to 802.3 standard. 8. After the packet is successfully transmitted, TMAC notifies output control of the successful transmission. Output control then returns the packet to buffer pool. 3. INTERFACE DESCRIPTIONS BUFFER MEMORY (SDRAM) INTERFACE AND TABLE (SSRAM) INTERFACE VT6516 provides a 64-bit SDRAM/SGRAM interface for packet buffering and a 32-bit synchronous SRAM (SSRAM) interface for maintaining address table and various link lists. VT6516 uses SDRAM as packet buffers. Each packet buffer is a 1536-byte contiguous memory block in SDRAM, and corresponds to a 12-byte link node data structure in SSRAM. Except the first 128 link nodes, each link node can be part of an output queue, a free buffer link list, or held in input or output control. The first 128 link nodes are divided into 16 groups, each pre-assigned to a specific input control, and bit-mapped inside buffer control for faster allocate/free operation and reduce SSRAM usage. Initially, each input port control would request one packet buffer from its private buffer pool. Each time when a packet buffer is consumed by an incoming packet, the input port control will request another packet buffer to prepare for next packet. The common shared packet memory will be allocated only when there’s no free permanent packet memory for that port. See Figure 3-4. -20- VIA Technologies, Inc. SRAM 12 bytes/entry Preliminary VT6516 Datarsheet DRAM 1.5 K/Packet 128 entries Permanent Buffer Table ... 1.5 K/Packet 128 blocks 12 bytes/entry Free List Link Table Address Table Entriers -21- VIA Technologies, Inc. Preliminary VT6516 Datarsheet Link/ Frame 128/0 List 0 List 1 129/0 Memory Bank 2K Links/ List 128/0 Bank 0 Bank 1 List 0 129/0 130/0 131/1 Memory Bank Bank 0 4K Bank 1 2K 130/1 131/0 132/1 133/1 2K 134/0 135/1 136/0 2K 2K List 1 4K 2K 132/1 133/1 134/0 135/0 136/1 137/1 4K 4K 2K 16MBits SDRAM 64MBits SDRAM Figure 3-3 Following as the listing and figure 3-6 is the algorithm of initialization procedures for 2 bank free list of SDRAM. For 16 Mbit SDRAM as following, -- Bank0 free link list: 128, 129, 131, 134, 136, 137, 139, 142, 144, 145, 147, 150, 152, 153, 155, 158, 160,... -- Bank1 free link list: 130, 132, 133, 135, 138, 140, 141, 143, 146, 148, 149, 151, 154, 156, 157, 159, 162, 164, ... For 64 Mbit SDRAM as following, -- Bank0 free link list: 128 , 129 , 130 , 134 , 135 , 139 , 140 , 141 , 144 , 145 , 146 , 150 , 151 , 155 , 156 , 157 , 160 , ... --Bank1 free link list: 131 , 132 , 133 , 136 , 137 , 138 , 142 , 143 , 147 , 148 , 149 , 152 , 153 , 154 , 158 , 159 , 163 , … Figure 3-6: Algorithm of Initialization of Free Link Lists. #define SRAM_ADDR_REG0 0x2001 #define SRAM_ADDR_REG1 0x2002 #define SRAM_ADDR_REG2 0x2003 #define SRAM_DATA_REG0 0x2004 #define SRAM_DATA_REG1 0x2005 #define SRAM_DATA_REG2 0x2006 #define SRAM_DATA_REG3 0x2007 #define SRAM_CMD_REG 0x2008 #define SRAM_STATUS_REG 0x2009 #define SRAM_ACCESS_IDLE 0x01 #define NULL_PTR 0x7FFFF void writeLinkEntry(int entryID, int nextID) { reg_byte_write (SRAM_ADDR_REG0, entryID*3 & 0x0FF); reg_byte_cont_write (((entryID*3) >> 8) & 0x0FF); reg_byte_cont_write (((entryID*3) >> 16) & 0x0FF); -22- VIA Technologies, Inc. reg_byte_cont_write (nextID & 0x0FF); // data bits [7:0] reg_byte_cont_write ((nextID >> 8) & 0x0FF); // data bits [15:8] reg_byte_cont_write ((nextID >> 16) & 0x0FF); // data bits [23:16] reg_byte_cont_write (0); // data bits [31:24] reg_byte_cont_write (0x02); // SRAM-write command while (reg_byte_read(SRAM_STATUS_REG) != SRAM_ACCESS_IDLE) {} } void initFreeList16Mb(int maxLinkEntryNo) { // note: for 16Mb SDRAM, // Bank0 free list head pointer = 128 // Bank1 free list head pointer = 130 int k; // k: current free entry id int b0, b1; // b0, b1: bank0/1 free list head entry id for(b0=b1= NULL_PTR, k= maxLinkEntryNo; k 8) & 0x0FF); reg_byte_cont_write (((entryID*3+1) >> 16) & 0x0FF); reg_byte_cont_write (nextID & 0x0FF); entry bits [32] reg_byte_cont_write ((nextID >> 8) & 0x0FF); reg_byte_cont_write ((nextID >> 16) & 0x0FF); reg_byte_cont_write ((nextID >> 16) & 0x0FF); reg_byte_cont_write (0x02); // SRAM-write command while (reg_byte_read(SRAM_STATUS_REG) != SRAM_ACCESS_IDLE) {} } 3.1.3 CPU interface The VT6516 support one ISA-like CPU interface, this CPU interface can cooperate with one simple microprocessor like 8031 or 8051. The CPU will access the switch control and status register to perform initialization and configurations. By the CPU interface, the frames of CPU port can be read/written from/into the buffer. The CPU interface can also be used to access the internal registers. The CPU interface also used to access the external PHY devices through the PHY control module. The CPU firmware will perform following tasks, - Read the configuration from switch register or from the EEPROM contains - Initialize the switch followed by the configuration, those task including * DRAM initialization * SRAM initialization and link list construction * Program for each network ports for users manual setting or read the auto-negotiation result - start switch to receive frames and forward frames - decrease the learning address aging count - polling the network port change event and change the switch MAC negotiation mode. -28- VIA Technologies, Inc. Preliminary VT6516 Datarsheet - Receiving the STP defined BPDU packets - Blocking or re-start port due to STP - Access the network management counter of each port For a management switch the CPU also perform the management function like receiving and transmitting the SNMP frame. -29- VIA Technologies, Inc. Preliminary VT6516 Datarsheet 3.1.4 Network interface The VT6516 directly connect to 16 port RMII PHY or 12 port MII PHY device which compliant with IEEE standard (Please see IEEE 802.3u Fast Ethernet standard) . Each Fast Ethernet port has following characteristics: - Capable of supporting both 10MBps and 100MBps data rates in half and full duplex modes. - Provide a simple management interface (SMI) for port status - Perform all functions of the IEEE 802.3 protocol such as frame formatting, frame stripping, collision handling, deferred, etc. - Adjustable preamble ,SFD and inter frame gap (IFG). - IEEE 802.3X flow control supported - IEEE 802.1D spanning tree protocol support, and all port state of listen and block configurable 3.1.4.1 RMII interface The VT6516 communicates with the external 10/100M Ethernet transceiver through the reduced MII (RMII) interface. The signals of RMII interface are described in Table-3-1 Table 3-1 RMII interface signals Name CRSDV RXD[0-1] TXEN TXD[0-1] Type I I O O Description Carrier sense and Data valid Receive data bit 0 to 1 , data rate with 50MHz Transmit Enable Transmit Data bit 0 to 1 Figure 3-1 RMII timing diagram (omitted) -30- VIA Technologies, Inc. Preliminary VT6516 Datarsheet 3.1.4.2 MII interface The VT6516 communicates with the external 10/100M Ethernet transceiver through standard MII interface, in this mode the VT6516 became 12 ports MII port due to the MII signal multiplexed with RMII signal. But the ports number of internal remained as 16 ports. The signals of MII interface are described in Table-3-2: Table 3-2 MII interface signals Name TCLK TXD[3:0] TXEN COL CRS RXD[3:0] RCLK RXDV Type I O O I I I I I Description Transmit Clock Transmit Data for. Transmit Collision Detected Carrier Sense Receive Data Receive Clock Receive Data Figure 3-2 MII timing diagram (omitted) 3.1.4.3 Flow control Under full-duplex mode operation, if the buffer utilization of whole switch has exceeded the upper threshold and the permanent buffer has been used up, a pause frame with a pause time interval will be send to the sending port to stop it from sending new frame. If register- FMFCT not enable at this switch, the public buffer will used until no more buffers. Then further incoming frames will be dropped. The unit in pause time field of the flow control frame is slot time (512 bits). The max possible waiting time should be the max packet memory size divided by lowest port speed, for example if 512MB is the max packet buffer size and 10Mb is the lowest speed, the 512M * 8 bits * 100ns = 409.6 seconds (8M slot time) is the max possible waiting time. The congestion factor is the max possible waiting time at current link load. The pause timer value is half of the max possible waiting time. If it is greater than the feasible max pause time, use all 1’s in pause time value. If the utilization of the public buffer of the switch drops below the lower threshold, a pause-frame with minimum frame interval of 0 will be sent to the linking ports the enable new frame transmission. Under half duplex operation, if the buffer utilization of whole switch has exceeded the upper threshold and the permanent buffer has been used up, the port will perform back-pressure based flow control by sending a jam pattern on each incoming frame. If backpressure flow control of the port is not enable, the frame will be dropped. The flow control pause time is calculated by maintained the configuration of port speed of each port and the buffer size. With input of the free memory block count and congestion factor, it determines flow control on or off on an output port. If flow control is on, any new queue request from a input port to this output port will trigger a flow control frame sent to that request port by the output MAC that is notified by the packet flow control unit. -31- VIA Technologies, Inc. Preliminary VT6516 Datarsheet The flow control activity is triggered when the buffer utilization exceeds certain thresholds specified by the dedicated register FMFCT, Register- FMFCT is used to specify the upper and lower thresholds of reserved buffer slot for whole switch. 3.1.4.4 SMI interface The VT6516 communicates with the external 10/100M PHY and access the PHY register through MDC, MDIO 3.1.4.5 Auto negotiation The VT6516 communicates with the external 10/100M PHY and access the PHY register through MDC, MDIO 3.1.5 Serial EEPROM interface -32- VIA Technologies, Inc. Preliminary VT6516 Datarsheet 4. FUNCTIONAL DESCRIPTION 4.1 Packet Reception and Address recognition When VT6516 received frames from network, the input control module will receive packet from input MAC module, then get the output port mask from forwarding table control module, request packet buffer from buffer control, write packet from input FIFO to packet buffer scheduled by scheduler module, queue packet to the output queue through queue control module. And update the forwarding table by the source address of the received good packet. Usually the source MAC address will be learned and stored to forwarding table. If VLAN is configured by user, the frame tag type and VLAN ID will also be learned. The source MAC address bit 47~11 and VLAN ID will be record in the forwarding table entry indexed by source MAC address bit 10~0 or 14~0. The on chip multicast forwarding configuration registers mainly are for well-known addresses which are listened by CPU. External multicast addresses are for dynamically assigned. Also some static Mac addresses/port mask registers can be configured by CPU, these addresses will also be checked before look up the forward table. 4.2 Packet Forwarding and VLAN The VT6516’s queue control maintains all head and tail pointers for all output ports. Accept the request to queue and dequeue packets from input and output control. Both queue and dequeue operations take only 1 SRAM access (3 words = 96 bits), because the tail node is stored in the internal register of the queue control Usually, queue and dequeue operations to a specific output queue can be performed simultaneously. However, mutual exclusion is applied while only one node in this queue Each port will maintain a packet counter, it increments when packet gets queued through the tail pointer, it decrements when packet de-queued through head pointer. The congestion factor is the queued packet count divided by port media speed. The congestion factor will be used for flow control and multicast, congestion factor should be roughly equal to the time it takes to transmit all the queued packets. For multicast packet, based on congestion factor, the least congested output port will be queued first. The output control will queue the packet to next least congested output port when it is transmitted, the CPU port will always be last port to be transmitted if the corresponding CPU bit is set in the port mask. The port speed will be used for cut through forwarding decision. If the packet length is 7ff, it implies the input control try to cut through, queue control will accept or reject by looking whether the input port speed is equal to the output port speed and the output don’t have queued packets and any pending transmission. The faster output port (than input port speed) and CPU port is not able to cut through Broadcast packet, multicast and look up miss packet will forward(multicast) to those ports which is configured by software, but default(dump switching hub) will be all ports(or all ports in that VLAN if VLAN is implemented) except CPU port. Broadcast, multicast packet will check the on chip broadcast forwarding configuration register and multicast forwarding configuration registers first, if multicast address not match any of the multicast forwarding configuration registers then it will look up the external SRAM forwarding table. -33- VIA Technologies, Inc. Preliminary VT6516 Datarsheet When request transfer to or from SDRAM through scheduler, the input control need to derive each burst starting address to bank0 or bank1 information for scheduler to utilize SDRAM bandwidth efficiently. When input FIFO is filled to 12x64 or page boundary or end of frame, the input port control will request DRAM access to write packet. Input FIFO size is 64 bits by 24. After receiving the grant of queueing (cut-through or store-and-forward), even the bad packet has to be forwarded. While cut-through, the input control will request the grant of cut-through counter bus for passing the cut through packet count from input port to output port as the whole packet has received. 4.2.1 Cross VLAN Server Port support The VT6516 support Cross VLAN server port configuration, the following illation show the sample of server ports configuration by set the register of server port mask(14A0H~14A1H), and server ports only enable after the VLAN enabled. The multicast or broadcast frames received from one VLAN group will forward to any server ports and only forward to the ports with same VID. 4.3 Network Management Features Flow control The flow control activity is triggered when the buffer utilization exceeds certain thresholds specified by the dedicated register XXXX, Register-XXXX is used to specify the upper and lower thresholds of reserved buffer slot for whole switch. Under full-duplex mode operation, if the buffer utilization of whole switch has exceeded the upper threshold and the permanent buffer has been used up, a flow control with a predefined pause time value will be sent to the source port to stop the input traffic. If flow control mechanism is not enabled, the public buffer will exhausted so that the further incoming frames will be dropped. Under half duplex operation, if the buffer utilization of whole switch has exceeded the upper threshold and the permanent buffer has been used up, the port will perform back-pressure based flow control by sending a jam pattern on each incoming frame. If backpressure flow control of the port is not enable, the frame will be dropped. Sniffer port The VT6516 support sniffer function for user to monitor the network traffic. The Sniffer port enable can be set for any individual port of sixteen ports. And each sniffer port can set to monitor the traffic coming from any others fifteen port(monitor port). Any packets sent to the monitor ports or transmitted out of monitor port will be forwarded to sniffer port. Spanning tree support The VT6516 support the spanning tree protocol (STP). When spanning tree protocol support is enabled, frames from the CPU port having a DA value equal to reserved Bridge Management Group Address for BPDU will be forwarded to the port specified by the CPU. Frames from other port with a DA equal to reserved Bridge Management Group Address for BPDU will be forwarded to the CPU port. -34- VIA Technologies, Inc. Preliminary VT6516 Datarsheet Every port of the VT6516 can be set to block and listen mode through the CPU interface. In the mode, incoming frames with DA value equal to the reserved Group address for BPDU will be forward to CPU port and other incoming frames with other DA value will be dropped. Outgoing frames with any DA value will be filtered expect DA equal to BPDU. -35- VIA Technologies, Inc. Preliminary VT6516 Datarsheet SECTION II REGISTER MAP 1. REGISTER TABLES The VT6516 incorporates the required command/status registers and various counters for management purposes. Although the default values of the control registers are predefined in the usual way, there is still a requirement for CPU intervention. All registers are defined as 8 bits so that long registers have to be divided into pieces of 8 bits with the Little-Endian principle, i.e. the lower byte in the lower address. There are only eight registers that are directly accessible for CPU, called the CPU interface registers. They are located with memory mapping in the range of 8000H ~ 8007H for the microprocessor 8031 in the evaluation board. The other registers are called the internal registers that are referenced indirectly by the 16-bit address register with offset 02H ~ 03H in the CPU interface address table. While the 16-bit address register is set to reference to the specific 8-bit internal register, the following read or write operation to the 8-bit data register with offset 01H in the CPU interface address table will cause the specified internal register to be read or written indirectly. Besides, the address register will increase by one automatically to facilitate the successive read/write operation. If the internal register is of size less than 8 bits, the value 0’s is always returned for the vacant register space and any write operations to them take no effect. 2 CPU INTERFACE REGISTERS MAP *Note: register table base = 8000H for the evaluation board. Description Type Offset Function Packet Data Register R/W 0H According to the strapping mode of packet [15:0] read/write data bus, two types are defined for 8bit and 16-bit data bus, respectively. For 8-bit CPU, only the low byte of the Packet Data Register is used for packet read/write. For 16-bit CPU, the whole 16-bit Packet Data Register is used for packet read/write. Data Register [7:0] R/W 1H The read or write operation to the 8-bit data register will cause the specified internal register (referenced by the Address Register) to be read or written indirectly. Besides, after the read/write operation, the Address Register will increase by one automatically to facilitate the successive read/write operation. Address Register [7:0] R/W 2H The low-byte address register for the reference to an internal register with 16-bit address. Address Register [15:8] R/W 3H The high-byte address register for the reference to an internal register. TEST Register 0 [7:0] W/O 4H see the description in TEST Register 3 TEST Register 1 [7:0] W/O 5H see the description in TEST Register 3 TEST Register 2 [7:0] W/O 6H see the description in TEST Register 3 TEST Register 3 [7:0] W/O 7H -36- VIA Technologies, Inc. Preliminary VT6516 Datarsheet 3 SWITCH INTERNAL REGISTERS MAP Address Register Description (base/offse t) 0000H SDRAM 00H SDRAM TYPE 01H 02H 03H 04H 05H 06H 07H 08H 0800H Name Bits Default R/ Value W SDRAMTYPE [0] CL RSDM END0A END1A END2A END3A 0 CAS Latency SDRAM Operation Mode DIM-Bank 0 Ending Address [1:0] 2 [3:0] 5 [4:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 DIM-Bank 1 Ending Address DIM-Bank 2 Ending Address DIM-Bank 3 Ending Address SDRAM Command Drive Strength Configure SDRAM Bank Interleaving Disable SRAM SRAM Read Command Interleave Disable SDRAM_DR_C [2:0] 0 FG BK_IL_DIS [0] 0 R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/O 00H 0C00H SRAM_READ_IL_D IS [0] 0 Queue control Free Memory Flow Control Threshold register FMFCT 00-02H 03H 04H 10-13H 14-17H 18-1BH 1C-1FH 20-23H Cut Through Enable CPU Port Speed Configuration Congestion Factor of Output Port 0 Congestion Factor of Output Port 1 Congestion Factor of Output Port 2 Congestion Factor of Output Port 3 Congestion Factor of Output Port 4 [18:0 0 ] CUT_THROU [0] 0 GH_EN CPU_SPD_CF [2:0] 0 G CONGEST_FC [25:0 0 T0 ] CONGEST_FC [25:0 0 T1 ] CONGEST_FC [25:0 0 T2 ] CONGEST_FC [25:0 0 T3 ] CONGEST_FC [25:0 0 T4 ] R/O R/O R/O R/O -37- VIA Technologies, Inc. 24-27H 28-2BH 2C-2FH 30-33H 34-37H 38-3BH 3C-3FH 40-43H 44-47H 48-4BH 4C-4FH 50-53H 1000H 00-02H 03-05H Preliminary VT6516 Datarsheet CONGEST_FC T5 CONGEST_FC T6 CONGEST_FC T7 CONGEST_FC T8 CONGEST_FC T9 CONGEST_FC T10 CONGEST_FC T11 CONGEST_FC T12 CONGEST_FC T13 CONGEST_FC T14 CONGEST_FC T15 CONGEST_FC T16 FREE0_PT FREE1_PT FREEMCNT CFP [25:0 ] [25:0 ] [25:0 ] [25:0 ] [25:0 ] [25:0 ] [25:0 ] [25:0 ] [25:0 ] [25:0 ] [25:0 ] [25:0 ] [18:0 ] [18:0 ] [18:0 ] [0] 0 0 0 0 0 0 0 0 0 0 0 0 R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O Congestion Factor of Output Port 5 Congestion Factor of Output Port 6 Congestion Factor of Output Port 7 Congestion Factor of Output Port 8 Congestion Factor of Output Port 9 Congestion Factor of Output Port 10 Congestion Factor of Output Port 11 Congestion Factor of Output Port 12 Congestion Factor of Output Port 13 Congestion Factor of Output Port 14 Congestion Factor of Output Port 15 Congestion Factor of Output Port 16 (CPU port) Buffer control Bank 0 Free Pointer Bank 1 Free Pointer Free Memory Block Count CLEAR All Free Pointers (reset the free buffer pointers according to the SDRAM TYPE) PRIVATE MEMORY ALLOCATION BIT MASK for PORT 0 PRIVATE MEMORY ALLOCATION BIT MASK for PORT 1 PRIVATE MEMORY ALLOCATION BIT MASK for PORT 2 PRIVATE MEMORY ALLOCATION BIT MASK for PORT 3 PRIVATE MEMORY ALLOCATION BIT MASK for PORT 4 PRIVATE MEMORY ALLOCATION BIT MASK for PORT 5 PRIVATE MEMORY ALLOCATION BIT MASK for PORT 6 PRIVATE MEMORY ALLOCATION BIT MASK for PORT 7 R/O R/O R/ W W/ O R/O R/O R/O R/O R/O R/O R/O R/O 06-08H 09H 10H 11H 12H 13H 14H 15H 16H 17H PORT0_MASK [7:0] 0 PORT1_MASK [7:0] 0 PORT2_MASK [7:0] 0 PORT3_MASK [7:0] 0 PORT4_MASK [7:0] 0 PORT5_MASK [7:0] 0 PORT6_MASK [7:0] 0 PORT7_MASK [7:0] 0 -38- VIA Technologies, Inc. 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 1400H 00H PRIVATE MEMORY ALLOCATION BIT MASK for PORT 8 PRIVATE MEMORY ALLOCATION BIT MASK for PORT 9 PRIVATE MEMORY ALLOCATION BIT MASK for PORT 10 Preliminary VT6516 Datarsheet PORT8_MASK [7:0] 0 PORT9_MASK [7:0] 0 [7:0] 0 [7:0] 0 [7:0] 0 [7:0] 0 [7:0] 0 [7:0] 0 R/O R/O R/O R/O R/O R/O R/O R/O PORT10_MAS K PRIVATE MEMORY ALLOCATION BIT MASK for PORT11_MAS PORT 11 K PRIVATE MEMORY ALLOCATION BIT MASK for PORT12_MAS PORT 12 K PRIVATE MEMORY ALLOCATION BIT MASK for PORT13_MAS PORT 13 K PRIVATE MEMORY ALLOCATION BIT MASK for PORT14_MAS PORT 14 K PRIVATE MEMORY ALLOCATION BIT MASK for PORT15_MAS PORT 15 K Forwarding table control bits of MAC address used as index for forwarding HASH_BITS table starting SRAM address register for forwarding table base user configured forwarding mode user configured port mask port mask for packets sent by CPU [2:0] 0 [18:0 0 ] [1:0] 0 01-03H 04H 05-07H 08-09H 0AH 0BH 0C-0EH TBL_BASE FWD_MODE USER_PM CPU port related forwarding configuration. port id of sniffer port. monitor port mask [16:0 0 ] CPU_PM [15:0 0 ] CPU_FWD_CF [2:0] 0 G SNIFFER_PID [3:0] 0 MONITOR_PM [16:0 0 ] AGE_MAC [6:0] 0 [7:0] 0 [0] 0 10H 11H 12H 20H 21H 22H 23H high byte [14:8] of the MAC hash address to be aged low byte [7:0] of the MAC hash address AGE_MAC to be aged. aging status AGING_STAT US spanning tree state for PORT 0 PORT0_STP_S TATE spanning tree state for PORT 1 PORT1_STP_S TATE spanning tree state for PORT 2 PORT2_STP_S TATE spanning tree state for PORT 3 PORT3_STP_S TATE -39- R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/O R/ W R/ W R/ W R/ W [1:0] 0 [1:0] 0 [1:0] 0 [1:0] 0 VIA Technologies, Inc. 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 80H 82H 84H 86H 88H 8AH 8CH 8EH 90H 92H 94H spanning tree state for PORT 4 spanning tree state for PORT 5 spanning tree state for PORT 6 spanning tree state for PORT 7 spanning tree state for PORT 8 spanning tree state for PORT 9 spanning tree state for PORT 10 spanning tree state for PORT 11 spanning tree state for PORT 12 spanning tree state for PORT 13 spanning tree state for PORT 14 spanning tree state for PORT 15 port 0 VLAN ID port 1 VLAN ID port 2 VLAN ID port 3 VLAN ID port 4 VLAN ID port 5 VLAN ID port 6 VLAN ID port 7 VLAN ID port 8 VLAN ID port 9 VLAN ID port 10 VLAN ID Preliminary VT6516 Datarsheet PORT4_STP_S TATE PORT5_STP_S TATE PORT6_STP_S TATE PORT7_STP_S TATE PORT8_STP_S TATE PORT9_STP_S TATE PORT10_STP_ STATE PORT11_STP_ STATE PORT12_STP_ STATE PORT13_STP_ STATE PORT14_STP_ STATE PORT15_STP_ STATE PORT0_VID PORT1_VID PORT2_VID PORT3_VID PORT4_VID PORT5_VID PORT6_VID PORT7_VID PORT8_VID PORT9_VID PORT10_VID [1:0] 0 [1:0] 0 [1:0] 0 [1:0] 0 [1:0] 0 [1:0] 0 [1:0] 0 [1:0] 0 [1:0] 0 [1:0] 0 [1:0] 0 [1:0] 0 [5:0] 0 [5:0] 0 [5:0] 0 [5:0] 0 [5:0] 0 [5:0] 0 [5:0] 0 [5:0] 0 [5:0] 0 [5:0] 0 [5:0] 0 R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W -40- VIA Technologies, Inc. 96H 98H 9AH 9CH 9EH port 11 VLAN ID port 12 VLAN ID port 13 VLAN ID port 14 VLAN ID port 15 VLAN ID Preliminary VT6516 Datarsheet PORT11_VID PORT12_VID PORT13_VID PORT14_VID PORT15_VID SRV_PM [5:0] 0 [5:0] 0 [5:0] 0 [5:0] 0 [5:0] 0 R/ W R/ W R/ W R/ W R/ W R/ W R/ W W/ O W/ O R/ W W/ O R/O R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W A0-A1H Server port mask A2H 1800H 00H 01H 02-03H 04H 05H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH [15:0 0 ] VLAN related forwarding configuration VLAN_FWD_C [0] 0 FG PHY control PHY ID PHYID [3:0] 0 PHY register address PHY data register PHY command register PHY status register PORT0 PHY Device Address PORT1 PHY Device Address PORT2 PHY Device Address PORT3 PHY Device Address PORT4 PHY Device Address PORT5 PHY Device Address PORT6 PHY Device Address PORT7 PHY Device Address PORT8 PHY Device Address PORT9 PHY Device Address PORT10 PHY Device Address PHY_REG_AD [4:0] 0 DR PHYDATA [15:0 ] PHYCMD [0] PHYSTS PORT0_PHY_ ADDR PORT1_PHY_ ADDR PORT2_PHY_ ADDR PORT3_PHY_ ADDR PORT4_PHY_ ADDR PORT5_PHY_ ADDR PORT6_PHY_ ADDR PORT7_PHY_ ADDR PORT8_PHY_ ADDR PORT9_PHY_ ADDR PORT10_PHY_ ADDR -41[1:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 VIA Technologies, Inc. 1BH 1CH 1DH 1EH 1FH 1C00H 00H 01H 02H 03H 2000H 00H PORT11 PHY Device Address PORT12 PHY Device Address PORT13 PHY Device Address PORT14 PHY Device Address PORT15 PHY Device Address EEPROM control EEPROM word address EEPROM data EEPROM device address EEPROM status register CPU interface interrupt status register Preliminary VT6516 Datarsheet PORT11_PHY_ ADDR PORT12_PHY_ ADDR PORT13_PHY_ ADDR PORT14_PHY_ ADDR PORT15_PHY_ ADDR EEWDADDR EEDATA [4:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 [4:0] 0 R/ W R/ W R/ W R/ W R/ W W/ O R/ W W/ O R/O R/ W R/ W R/ W R/ W R/O R/ W R/ W R/ W R/O W/ O W/ O R/ W R/ W R/ W [7:0] [7:0] EEDEVADDR [7:0] EESTS IRQSTS SRAMADDR SRAMDATA SRAMCMD [2:0] [3:0] 0 [18:0 ] [31:0 ] [1:0] 01H-03H SRAM address register 04H-07H SRAM data register 08H SRAM command register 09H SRAM status register 10H-13H SDRAM address register 14H-1BH SDRAM data register 1CH 1DH 20H 21H 30H 31H 32H SDRAM command register SDRAM status register Write packet command Packet Abort SRAMSTS [1:0] 0 SDRAMADDR [23:0 ] SDRAMDATA [63:0 ] SDRAMCMD [1:0] SDRAMSTS [1:0] 0 WR_PKT_CM [2:0] D ERR_ABORT [0] bits [47:40] of switch base MAC address SWITCH_MA [7:0] 0 [47:0] C_BASE bits [39:32] of switch base MAC address SWITCH_MA [7:0] 0 [47:0] C_BASE bits [31:24] of switch base MAC address SWITCH_MA [7:0] 0 [47:0] C_BASE -42- VIA Technologies, Inc. 33H 34H 35H 40H 50H 51H 2400H 00H 01H 02H 03H 04H 10H-13H 14H-17H 18H-1BH 1CH-1FH 20H-23H 2800H 2C00H 3000H 3400H 3800H 3C00H 4000H 4400H 4800H 4C00H Preliminary VT6516 Datarsheet R/ W 0 R/ W 0 R/ W 4’b1111 R/ W 1 R/ W 0 R/O 0 bits [23:16] of switch base MAC address SWITCH_MA [7:0] [47:0] C_BASE bits [15:8] of switch base MAC address SWITCH_MA [7:0] [47:0] C_BASE bits [7:4] of switch base MAC address SWITCH_MA [7:4] [47:0] C_BASE interrupt mask register IRQSTS_MAS [3:0] K CPU Soft Reset for the whole switch chip CPU_SOFT_R [0] reset ESET Revision Control Register REVISION_CT [7:0] L MAC & I/O Control Module of Port 0 configurable preamble bytes PREAM_CFG [2:0] R/ W configurable frame gap in di bits for 1st IFG_CFG [5:0] 32 R/ interval W Backoff configuration BOFFCFG [4:0] 5’b100 R/ 00 W MAC media type configuration MACCFG [3:0] 0 R/ W IO port enable IO_CFG [1:0] 0 R/ W received good packet count RCV_GOOD_P [31:0 0 R/O KT ] received bad packet count RCV_BAD_PK [31:0 0 R/O T ] drop packet counter DROP_PKT [31:0 0 R/O ] sent good packet count XMT_GOOD_ [31:0 0 R/O PKT ] sent bad packet counter XMT_BAD_PK [31:0 0 R/O T ] MAC & I/O Control Module of Port 1 as same as Port 0 MAC & I/O Control Module of Port 2 as same as Port 0 MAC & I/O Control Module of Port 3 as same as Port 0 MAC & I/O Control Module of Port 4 as same as Port 0 MAC & I/O Control Module of Port 5 as same as Port 0 MAC & I/O Control Module of Port 6 as same as Port 0 MAC & I/O Control Module of Port 7 as same as Port 0 MAC & I/O Control Module of Port 8 as same as Port 0 MAC & I/O Control Module of Port 9 as same as Port 0 MAC & I/O Control Module of Port as same as Port 0 10 7 -43- VIA Technologies, Inc. 5000H 5400H 5800H 5C00H 6000H 6400H 00H 01H 02H 03H 04H 10H MAC & I/O Control Module of Port 11 MAC & I/O Control Module of Port 12 MAC & I/O Control Module of Port 13 MAC & I/O Control Module of Port 14 MAC & I/O Control Module of Port 15 CPU IO Control Module CPU packet read byte count register bits [7:0] CPU packet read byte count register bits [10:8] CPU packet read status register Packet source port ID CPU IO port configuration register CPU packet write status register Preliminary VT6516 Datarsheet as same as Port 0 as same as Port 0 as same as Port 0 as same as Port 0 as same as Port 0 PKT_BYTE_C NT PKT_BYTE_C NT RD_PKT_STA TUS PKT_SRC_PO RT CPUIO_CFG [7:0] 0 [10:8 0 ] [1:0] 0 [3:0] 0 [1:0] 0 R/O R/O R/O R/O R/ W R/O WR_PKT_STA [2:0] 0 TUS 4. DETAIL OF SWITCH REGISTER 4.1 Registers of SDRAM Control Module * Base Address: 0000H Addres Function s (offset ) 00H SDRAM TYPE: Register Name Bits Defau R/ lt W Value 0 R/W SDRAMTYPE [0] 0: 16Mbit SDRAM chip (default) 1: 64Mbit This register has to be specified before initialization of the buffer control because the Bank 1 free buffer pointer should have initial value 130 for 16Mbit SDRAM, or, initial value 131 for 64Mbit SDRAM. CAS Latency for read operation: CL 2’b00: latency 1 2’b01: latency 2 2’b10: latency 3 (default) This latency specifies the required delay between the CAS cycle and the first read cycle. Note that the CAS latency has to be specified before using RSDM in SDRAM initialization. 01H [1:0] 2 R/W -44- VIA Technologies, Inc. 02H SDRAM Operation Mode: For the bits [2:0], the operation modes are defined as follows: 3’b000: Normal SDRAM Mode 3’b001: NOP Command Enable 3’b010: Precharge All Banks 3’b011: MSR Enable (Mode Register Set Enable) 3’b100: CBR Refresh Cycle Enable others: idle for power-up For the bit [3], it is called REFRESH_EN, defined as follows: 0: turn off hardware refresh cycle (default) 1: turn on hardware refresh cycle Preliminary VT6516 Datarsheet RSDM [3:0] 5 R/W After the last refresh operation issued by software in the initialization cycle, software should enable the bit “REFRESH_EN” immediately to notify SDRAM control module ‘sdramctl’ to start generating refresh cycle periodically. The initialization of SDRAM control module is illustrated as follows: SDRAMTYPE ß 0 : 16Mb CL ß 1 : read latency = 2 (3) delay 1 s (4) RSDM ß 1 : NOP (5) delay 1 s (6) RSDM ß 2 : Precharge (7) delay 1 s (8) loop 7 times RSDM ß 4 : Refresh delay 1 s RSDM ß 1 : NOP delay 1 s (9) RSDM ß 0CH : Refresh & turn on hardware refresh (10) delay 1 s (11) RSDM ß 0BH : Mode Register Set Enable (12) delay 1 s (13) RSDM ß 08H : Normal SDRAM Mode (14) END0A ß 0x04 : DIM bank 0 ending address = 32MB (15) END1A ß 0x08 : DIM bank 1 ending address = 64MB (16) END2A ß 0x0C : DIM bank 2 ending address = 96MB (17) END3A ß 0x10 : DIM bank 3 ending address = 128MB Bits [27:23] of DIMM Bank 0 Ending Address 03H END0A [4:0] 0 R/W 04H 05H 06H For the case that there are two 32MB SDRAM modules plugged in DIMM slot 0 and two 16MB SDRAM modules plugged in DIMM slot 1, assign the registers as follows END0A = 04H to indicate the ending address of DIMM Bank 0 is at 2^25 (32MB) END1A = 08H to indicate the ending address of DIMM Bank 1 is at 2^26 (64MB) END2A = 0AH to indicate the ending address of DIMM Bank 0 is at 2^26+2^24 (80MB) END3A = 0CH to indicate the ending address of DIMM Bank 0 is at 2^26+2^25 (96MB) Bits [27:23] of DIMM Bank 1 Ending Address END1A (see END0A) Bits [27:23] of DIMM Bank 2 Ending Address END2A (see END0A) Bits [27:23] of DIMM Bank 3 Ending Address END3A (see END0A) [4:0] [4:0] [4:0] 0 0 0 R/W R/W R/W -45- VIA Technologies, Inc. 07H SDRAM Command Drive Strength Configure bit0: RDCSDV --- SDRAM Chip Select Drive Strength bit1: RMADV --- SDRAM MA drive strength (including RAS,CAS,WE,MA,BA) bit2: RMDDV --- SDRAM MD drive strength SDRAM Bank Interleaving Disable 0: enable interleaving (default) 1: disable interleaving Preliminary VT6516 Datarsheet SDRAM_DR_ [2:0] CFG 0 R/W 08H BK_IL_DIS [0] 0 R/W 4.2 Registers of SRAM Control Module * Base Address: 0800H Addres Function s (offset ) 00H SRAM Read Command Interleave Disable 0: enable interleaving (default) 1: disable interleaving Register Name Bits Defau R/ W lt Value 0 R/W SRAM_READ [0] _IL_DIS 4.3 Registers of Queue Control Module * Base Address: 0C00H Addres Function s (offset ) Free Memory Flow Control Threshold register 0002H As FREEMCNT(a register in buffer control) < FMFCT, the Register Name Bits Defau R/ lt W Value R/ W FMFCT [18:0 0 ] 03H congestion control function will be triggered to command the TMAC module of the source port, destined to a congested port, to send out a flow control frame for full duplex mode, or to make back-pressure for half duplex mode. See the context about congestion control for details. Larger the threshold value more sensitive the congestion control mechanism, i.e. maybe poor utilization for packet buffers but larger packet loss rate. Smaller the threshold value less sensitive the congestion control mechanism, i.e. maybe good utilization for packet buffers but smaller packet loss rate. It depends on the network configuration and traffic pattern. The recommended threshold value is 256. Cut Through Enable CUT_THROU [0] 0: Disable Cut Through (default) GH_EN 1: Enable Cut Through Note: REMEMBER to enable the cut-through function to improve the switching latency. For 100Mbps input port, the smallest latency for cut-through is 288 bytes time (288x8x10 ns). For 10Mbps input port, the smallest latency for cut-through is 96 bytes time (96x8x100 ns). 0 R/W -46- VIA Technologies, Inc. 04H CPU Port Speed Configuration 3’b000: 1 Mbit (default) 3’b001: 5 Mbit 3’b010: 10 Mbit 3’b011: 20 Mbit 3’b100: 40 Mbit 3’b101: 50 Mbit 3’b110: 80 Mbit 3’b111: 100 Mbit Preliminary VT6516 Datarsheet CPU_SPD_CF [2:0] G 0 R/W 1013H 1417H 181BH 1C1FH 2023H 2427H 282BH 2C2FH 3033H 3437H 383BH 3C3FH 4043H 4447H 484BH This register is used to calculate the congestion factor of the CPU port, that is the quotient of the accumulated byte count of the CPU output queue to the specified CPU port speed. While the congestion control is triggered, the output ports with congestion factor larger than the average will enter into the congestion control mode. Congestion Factor of Output Port 0 CONGEST_F [25:0] CT0 The congestion factor, i.e. the quotient of the accumulated byte count of the output queue to the port speed, for each of 16 Ethernet ports is calculated by the flow control module. While the congestion control is triggered, the output ports with congestion factor larger than the average will enter into the congestion control mode. Congestion Factor of Output Port 1 CONGEST_F [25:0] CT1 Congestion Factor of Output Port 2 Congestion Factor of Output Port 3 Congestion Factor of Output Port 4 Congestion Factor of Output Port 5 Congestion Factor of Output Port 6 Congestion Factor of Output Port 7 Congestion Factor of Output Port 8 Congestion Factor of Output Port 9 Congestion Factor of Output Port 10 Congestion Factor of Output Port 11 Congestion Factor of Output Port 12 Congestion Factor of Output Port 13 Congestion Factor of Output Port 14 CONGEST_F [25:0] CT2 CONGEST_F [25:0] CT3 CONGEST_F [25:0] CT4 CONGEST_F [25:0] CT5 CONGEST_F [25:0] CT6 CONGEST_F [25:0] CT7 CONGEST_F [25:0] CT8 CONGEST_F [25:0] CT9 CONGEST_F [25:0] CT10 CONGEST_F [25:0] CT11 CONGEST_F [25:0] CT12 CONGEST_F [25:0] CT13 CONGEST_F [25:0] CT14 0 R/O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O -47- VIA Technologies, Inc. 4C4FH 5053H Congestion Factor of Output Port 15 Congestion Factor of Output Port 16 (CPU port) Preliminary VT6516 Datarsheet CONGEST_F [25:0] CT15 CONGEST_F [25:0] CT16 0 0 R/O R/O There are 11 bits are used for reading FREEMCNT. Only 15 bits are used as CPU port’s congestion factor. The read sequence of CONGEST_FCT16[14:0] is as follows: 1. Read 0C50H to get the lowest byte. CONGEST16[7:0] = HD[7:0] 2. Read 0C51H to get the other 7 bits. CONGEST16[14:8] = HD[6:0] 4.4 Registers of Buffer Control Module * Base Address: 1000H Addres Function s (offset ) 00-02H Bank 0 Free Pointer Register Name Bits Defau R/ lt W Value R/O This register is initialized according to SDRAMTYPE while the CFP is written. For 16/64Mbit SDRAM, its value is always 128 because the bank 0 free list follows the private buffer pool of buffer entries 0~127. The free buffers with starting address at the SDRAM even bank should be linked into this free list to improve the SDRAM bandwidth utilization. However, if the free buffers are misplaced, they will returned to the adequate free lists after their first release by the output port control. Internally, the free pointer refers to the ID of the 1st free buffer, rather than its physical address in SRAM (that is equal to ID*3). 03-05H Bank 1 Free Pointer FREE1_PT This register is initialized according to SDRAMTYPE while the CFP is written. For 16Mbit SDRAM, its value is 130. For 64Mbit SDRAM, its value is 131. The fixed buffer size is 1536 bytes. Because the page size is 2KB for 16Mbit SDRAM, the first public buffer of bank 1 is the 130th entry located at page 1. Because the page size is 4KB for 64Mbit SDRAM, the first public buffer of bank 1 is the 131st entry located at page 1. Free Memory Block Count FREEMC It is an integer value