VV5300

VV5300 Sensor Integrated CMOS Image Sensor with on-chip ADC. DISTINCTIVE CHARACTERISTICS • • • • • • Standard image format: 160 x 120 164 x 124 pixel array • Variable frame rate (2 fps - 60 fps) • On-chip 8-bit A/D convertor • 8-bit and 4-bit conversion modes • 8-wire and 4-wire parallel data output modes Options selectable via serial interface Automatic black level calibration Automatic exposure and gain controller 2 serial data output modes • Reduced flicker operation with 50Hz and 60Hz mains frequencies GENERAL DESCRIPTION VV5300 is a highly-integrated CMOS image sensing device. In addition to a 160 x 120 pixel image sensor array, the device includes on-chip circuitry to drive and sense the array. The primary image size is 160 x 120 but border pixels/lines can be enabled to give an effective image size of 164 x 124. BLOCK DIAGRAM Pr Pixel Resolution Pixel Size SDA SCL el im DIGITAL CONTROL LOGIC D[7:0] IMAGE FORMAT SIN FST QCK The output stage of the sensor contains a successive approximation circuit which performs analogue-todigital conversion of the photodiode array to produce 8-bit or 4-bit pixel data. in VV5300 features electronic exposure and gain control over a wide range, enabling the use of a single fixed-aperture lens. A bi-directional 2-wire serial communications interface allows the device to be configured and its operating status monitored. The status information may also be multiplexed onto the digital output bus. ar Array Size Power Supply Min.illumination Power S/N Temperature y VERTICAL SHIFT REGISTER 160 x 120 12µm x 12µm 1.92mm x 1.44mm 5v +/-10% 0.1 Lux 175 mW (Typ.) 36 dB (Typ.) Automatic (25000:1) -20oC to +70oC PHOTO DIODE ARRAY CLKI CLKO CLOCK CIRCUIT SAMPLE & HOLD VBLTW VRT VCM VREF2V5 VPED/VBG VCDS ANALOG VOLTAGE REFS. HORIZONTAL SHIFT REGISTER Exposure control A/D CONVERTOR cd34011-b.fm 17/10/97 1 VV5300 Sensor Main Features On-chip 8-bit successive approximation analogue-to-digital convertor with 8-wire, 4-wire parallel and two serial data output modes. The default image format is 160x 120. Extra border pixel/lines can be enabled to give an image size of 164 x 124. Digital pixel data coding assigns 10H as black and F0H as white. Other codes specify line sync and frame sync periods. The VV5300 frame rates can be integer multiples of the mains supply frequencies used worldwide, i.e. 50Hz and 60Hz. This ensures reduced flicker operation of the sensor All VV5300 operating modes and system status information can be accessed via a two wire bidirectional serial interface. VV5300 features an automatic electronic exposure algorithm that enables the use of a single fixed-aperture lens. Automatic gain control enhances operation under low light conditions. Automatic black level control ensures consistent picture quality across the whole range of operating conditions. Extensive use of automated operation and on chip references means that only a small number of passive components are needed to realise a complete video camera. On-chip voltage references simplifies the support circuitry and maintains device stability over a wide range of operating conditions. This device is also available with bayer pattern colour filters (VV6300), see seperate datasheet. With automatic exposure control selected VV5300 uses a complex algorithm to automatically set the exposure value for the current scene. When combined with clock control and gain control the VV5300 can operate over a very wide range of illumination levels. Where direct control of the exposure is required the exposure value can be directly selected by writing to the appropriate registers via the serial interface. The system clock can be divided down internally to extend the operating range of VV5300 by allowing longer exposure times. The clock divisor can be varied from 2 to 16 in times two steps i.e there are 4 different values. Note: changing the system clock divisor modifies the pixel and frame rate. Gain Control If the image is to dark and the exposure is already close to its maximum, VV5300 will increase the system gain. Gain can be varied from x1 to x8 in times two steps i.e there are 4 different gain settings. If the scene is too dark and integration period has almost reached its maximum value the gain value is incremented by one step (i.e. doubled). If the gain setting changes the exposure value is automatically set to half the maximum integration period. The exposure controller then increases the exposure value as necessary. Similarly if the image is too bright and the integration period is short then gain will be reduced by one step (i.e. divide by two). As before, the exposure value is set to half the maximum integration period. The exposure controller can then adjust the exposure value as necessary to provide a correctly exposed image. cd34011-b.fm Pr Clock Control el im Exposure Control 17/10/97 in ar y 2 VV5300 Sensor Device Pinout VDD 30 29 28 27 26 25 24 23 22 21 20 19 CLKI 31 CLKO 32 SDA 33 SCL 34 VSS 35 DVSS 36 AUTOLOADB 37 CE 38 NC 39 VREG 40 NC 41 NC 42 43 44 45 46 47 48 1 NC VBLOOM VBLTW VBG VREF2V7 VRT NC 2 3 4 5 VV5300 VDD 18 NC 17 QCK 16 FST 15 SIN 14 VDD 13 DVDD 12 NC 11 NC 10 NC 9 AVDD 8 NC VSS VSS D[6] D[7] D[0] D[1] D[2] D[3] D[4] D[5] Viewed from above Pad List Pin Name el im Type GND PWR PWR PWR PWR GND GND PWR GND GND Power Power Ground Ground Power Ground Ground IA POWER SUPPLIES 9 13 14 19 20 29 30 35 36 Pr AVDD DVDD VDD VDD VSS VSS VDD VSS DVSS VRT 6 AVSS Analogue ground Analogue power Digital power ANALOGUE OUTPUTS 1 Pixel reset voltage cd34011-b.fm 17/10/97 in Description ar VCDS TEST HPIX NC AVSS y 7 NC 6 3 VV5300 Sensor Pin 2 3 40 44 45 46 47 Name VCDS TEST VREG VBLOOM VBLTW VBG VREF2V5 Type IA IA ΙΑ ΟΑ IA OA ΟΑ Voltage reference Analogue test Description Reference voltage input Internal reference voltage Bitline test white reference Internally generated bangap reference voltage 1.22V Internally generated reference voltage 2.5V DIGITAL OUTPUTS 16 17 25-28 21-24 FST QCK D[3:0] D[7:4] OD OD BI↓ OD↓ Parallel 4-bit databus. D[0] serial data bus. DIGITAL CONTROL SIGNALS 33 37 38 4 15 SDA AUTOLO ADB CE HPIX SIN Pr CLKI CLKO 31 32 OA - Analogue output OD - Digital output BI - Bidirectional OD↓ − Digital output with internal pull-down el im BI↑ ID↓ ID↑ ID↓ ID↓ ID OD 34 SCL BI↑ Serial bus clock (bidirectional, open drain) Serial bus data (bidirectional, open drain) Enable autoload from EEPROM Chip enable Hold pixel value. Frame Timing reset(Soft reset) SYSTEM CLOCKS Oscillator input. Oscillator output. cd34011-b.fm 17/10/97 in Parallel 4-bit databus. ar Pixel sample clock. Qualifies video output for external image capture. A - Analogue input D - Digital input ID↑ − Digital input with internal pull-up y Frame start. Synchronises external image capture. 4 VV5300 Sensor SPECIFICATIONS Package Details 0.51 1.56 0.55 0.53 13.7 Glass Lid Die Base 0.5 0.86 Viewed from side The optical array is centred within the package to a tolerance of ± 0.2 mm, and rotated no more than ± 0.5o Tolerances on package dimensions ±10% 2.16 PIN 1 1.016 PITCH 14.22 All dimensions in millimetres +/- Viewed from below Spectral Response Normalised Response 1.0 0.8 0.6 0.4 0.2 0 Pr 400 el im 1000 500 600 700 800 900 Wavelength nm in 17/10/97 1100 cd34011-b.fm ar Glass lid placement is controlled so that no package overhang exists. y 5 VV5300 Sensor Absolute Maximum Ratings Parameter Supply Voltage Voltage on other input pins Temperature under bias Storage Temperature Maximum DC TTL output Current Magnitude -0.5 to +7.0 volts -0.5 to VDD + 0.5 volts -15oC to 85oC -30oC to 125oC 10mA (per o/p, one at a time, 1sec. duration) Value Note: Stresses exceeding the Absolute Maximum Ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. DC Operating Conditions Symbol VDD VIH VIL TA Parameter Operating supply voltage Input Voltage Logic “1” Input Voltage Logic “0” Ambient Operating Temperature Min. 4.75 2.4 Typ. ar 5.0 5.25 0.8 70 Typ. 14.318 100 Typ. 10 25 Max. y Max. Units Volts Volts Volts o Notes in -0.5 0 Min. Min. VDD+0.5 el im C Still air AC Operating Conditions Symbol CKIN SCL Parameter Max. Units MHz KHz Notes 1 2 1. Pixel Clock = CKIN/2 2. Serial Interface clock must be generated by host processor. Electrical Characteristics Symbol Pr Crystal frequency Serial Data Clock Parameter Units mA mA Notes 1 1 IDCC IADD Digital supply current Analog supply current Typical conditions, VDD = 5.0 V, TA = 27oC cd34011-b.fm 17/10/97 6 VV5300 Sensor Symbol Parameter Min. Typ. 35 2.700 1.22 Max. Units mA Volts Volts Volts Notes 1 IDD VREF2V7 VBG VOH VOL Overall supply current Internal voltage reference Internal bandgap reference Output Voltage Logic “1” Output Voltage Logic “0” 2.4 IOH = 2mA IOL = -2mA 0.6 -1 1 Volts µA µA IILK Input Leakage current VIH on input VIL on input Typical conditions, VDD = 5.0 V, TA = 27oC 1. Digital and Analogue outputs unloaded - add output current. cd34011-b.fm Pr 17/10/97 el im in 7 ar y VV5300 Sensor Operating Characteristics Parameter Dark Current Signal min. typ. 50 max. units mV/Sec Note Modal pixel voltage due to photodiode leakage under zero illumination with Gain=1 (Vdark = (Vt1 - Vt2)/(t1-t2), calculated over two different frames VAve/Lux·10ms, where Lux gives 50% saturation with Gain=1 and Exposure=10ms Standard CCIR clock Variance of Vave over eight equal blocks at 66% saturation level illumination RMS variance of all pixels, at 66% saturation, over four frames Sensitivity Min. Illumination Shading Random Noise Smear 6 0.1 TBA -36 TBA V/Lux·Sec Lux % dB % Flicker Lag TBA TBA % % Blooming el im TBA All voltage (VA, Vave, Vsat, Vxx%) measurements are referenced to the black level, Vblack, and spot blemishes are excluded (see Blemish Specification below). Vxx% refers to the output that is xx% of saturation, that is peak white Test Conditions Illumination Colour Temp. 3200o K 14.318MHz Maximum x1 Off The sensor is tested using the example support circuit illustrated later in this document. Standard imaging conditions used for optical tests employ a tungsten halogen lamp to uniformly illuminate the sensor (to better than 0.5%), or to illuminate specific areas. A neutral density filter is used to control the level of illumination where required. Pr Note: Devices are normally not 100% tested for the above characterisation parameters, other than Dark Current Signal (see Blemish Specification below). cd34011-b.fm 17/10/97 in ar Exposure Gain Ratio of Vave of the area outside a rectangle 25 lines high illuminated at 500xV50% level to VAve of the rectangle Variation of Vave of one line from field to field at 66% saturation level illumination Average residual signal with no illumination in the field following one field of 66% sat. illumination Ratio of spot illumination level that produces 0.1xVsat output from immediately around the spot to the Vsat spot illumination level (pinhole target) Clock Frequency Auto. Gain Control (AGC) y 8 VV5300 Sensor Blemish Specification A Blemish is an area of pixels that produces output significantly different from its surrounding pixels for the same illumination level. The definition of a Blemish Pixel varies according to testing conditions as follows: Test 1 - Black Frame 2 - Dark Current 3 - Pixel Variation Exposure Minimum Maximum Mid range Illumination Black Black 66% Sat. Blemish Pixel output definition Differing more than ± 100 mV. from modal value. Output more than three times the modal value (see Dark Current Signal above). Differing more than ±35mV from modal value. Note: The mode of pixel values must be within ±70 mV of 66% of Vsat for all devices. Note: Gain is set to Minimum and Correction set to Linear for all tests; measurement of blemishes for Test 3 is conducted under standard illumination (see above), set to produce average output of 66% saturation level. The blemish specification is then defined as follows: Max. No. of Blemishes 4 1 el im Unconnected single pixels Of up to four connected pixels (2x2 max.) cd34011-b.fm Pr NB, pixel blemishes may occur anywhere on the array. 17/10/97 in Notes ar y 9 VV5300 Sensor System Clock Generation VV5300 generates a system clock when a quartz crystal or ceramic resonator circuit is connected to the CLKI and CLKO pins. The device can also be driven directly from an external clock source driving CLKI. CLK CLK CLOCK DIVISION CLOCK DIVISION VV5300 VV5300 CKIN C1=C2=47pF R1=1MΩ R2=510Ω X1= 14.318MHz (up to 60fps) 17.73MHz (up to 50fps) C1 31 R1 CKOUT 32 CKIN 31 CKOUT 32 R2 C2 Camera Clock Source el im Divisor 2 4 8 16 0 1 0 1 For greater flexibility the input frequency can be divided by 2, 4, 8 or 16 to select the pixel clock frequency. Two bits in the clock division register in the serial interface select the input clock frequency divisor. The table below gives the different frame rates that can be selected, when CLKI = 14.318MHz, for each divisor. The default clock divisor setting is a divide by 2. To achieve maximum frame rates data is converted at 4 bit resolution. in Pixel Freq. (kHz) 1790 895 448 224 CLKI (MHz) 14.318 14.318 14.318 14.318 1. ar Frame rate1 (fps) 59.98 29.99 15.01 7.5 Comments default 10 X1 CMOS Driver Approximate frame rate. Assumes 160 x 120 image format, parallel data output and 4 bit data conversion cd34011-b.fm Pr 0 1 1 0 Clock Division (60Hz Video Mode) 17/10/97 y Clock Source VV5300 Sensor Image Format VV5300 has a single output image size, 160 x 120 pixel. The image size can be modified by asserting the “enable borders” serial interface register bit, (Setup1, [001_00012]). The extended image size is 164 x 124 pixels. The default image format is 160 pixels by 120 lines. Enable borders 0 1 Image size (column x row) 160 x 120 164 x 124 Image Format Selection Comment default The diagram below shows the relationship between the default 160 x 120 pixel image and the extended 164 x 124 pixel format. A border, 2 pixels wide is enabled around the basic array. 164 160 in cd34011-b.fm 120 Pr el im Output Image Dimensions 17/10/97 124 ar 11 y VV5300 Sensor Frame Timing The VV5300 frame rate depends upon: (i) (ii) (ii) the frequency of the clock input (CLKI) the ADC conversion accuracy the internal clock divisor chosen. Users can set their own values for CLKI, the ADC conversion rate and also the clock divisor setting, subject to achieving a frame rate up to 60 frames/sec. The frame rate is determined in the following way: An example is given with a clock input of 14.318MHz, 160 x120 image format, 8 bit ADC conversion rate and a clock divisor of 4. 1. 2. Determine clock input (CLKI) frequency - 14.318MHz Pixel period = (Divisor x 8) / CLKI Example: 3. Pixel period = (4 x 8) / 14.318MHz Line period = (no. of active pixels + line overhead) * pixel period The number of active pixels per line is either 160 or 164. The interline pixel period overhead (including the 4 border pixels that can be enabled to qualify extra video information) is mode dependent, 43 pixel periods for 60fps or 135 pixel periods for 50fps. Refer to figure * for more information. el im Example: 4. Line period = (160 + 43) x 2.235µs Frame period = (no. of active lines + frame overhead) * line period Pr Frame period Frame rate For the purposes of calculating the effective frame rate the number of active lines is assumed to be fixed at 120. The frame overhead (which includes the 4 border lines that can be enabled to qualify extra video information) has a constant value of 27 line periods. Refer to table * for more information. Example: = (120 + 27) x 453.705µs = 1 / frame period = 66.694ms = 15 frames per second cd34011-b.fm 17/10/97 in ar = 2.235µs = 453.705µs y 12 VV5300 Sensor Digital Data Output Modes VV5300 provides several different output modes. The different data formats are selected via the appropriate register in the serial interface, Setup0, [001_00002], bits 5 and 6. 8-bit or 4-bit pixel data conversion is also selected via the serial interface, Setup1, [001_00012]. If 4-bit pixel data conversion is selected as well as 8Wire parallel output format then 2 consecutive pixel nibbles may be packed into a single output byte therefore increasing the effective frame rate. Setup Bit 6 0 0 1 1 Setup Bit 5 0 1 0 1 Description 8-Wire Parallel 4-Wire Parallel Serial Serial UART Comment default Frame Level Formatting FST Black Lines (BK) Line BL ST BK BK BL el im BL BL BL Frame Start in BL BL BL BL BL BL BL FE BL BL VL VL BL BL BL FE The frame level format for each mode is common and is given below. FST can be used for frame synchronisation. The FST pulse is exactly one line period in length and the rising edge occurs just before the status line start sequence (see line level formatting) is output. BL ar VL VL BL ST VL VL BL ST y Visible Lines (VL) VL VL VL VL VL VL 120 Visible Lines BL BL BL BL BL BL Frame Period = 147 Lines Visible Lines (VL) VL VL VL VL VL VL 124 Visible Lines BL BL BL BL BL BL Frame Period = 147 Lines Data Output Modes BL Start / Status Line (ST) Blank Lines (BL) Line VL BL BL Pr BL BL BL BL Frame Start BL BL BL BL BL BL BL FST BL BL BL Frame End (FE) Frame Format (160 x 120 mode) FST Black Lines (BK) Line BL ST BK BK BL BL BL Start / Status Line (ST) Blank Lines (BL) FST Line VL VL VL BL BL BL Frame End (FE) Frame Format (164 x 124 mode) cd34011-b.fm 17/10/97 13 VV5300 Sensor Line Level Formatting Each line type (black, blank, visible) has a specific format associated with it independent of the data output format selected. Each line begins with a start sequence of FFH FFH 00H followed by XYH where XYH indicates the line type. The next two bytes provide supplementary data (specifically the line number within the current frame). Following this data are two guaranteed blank bytes (07 H 07Hfor 8 bit modes, 01H01H for 4 bit modes). If the border lines/pixels have been enabled the next 2 bytes will be visible pixels otherwise they shall appear as blank bytes. The next part of the line is reserved for the 160 visible pixels. The 4 bytes following the visible pixels are formatted in the same way as the 4 bytes preceeding the 160 visible pixels. At the end of each line, an end of line sequence is produced, (FFH FFH 00H 80H). If the line is within the visible part of the frame, (lines 11 to 134 if the border lines are enabled otherwise lines 13 to 132), the end of line sequence is immediately followed by 2 bytes containing the mean values for the central 128 pixels. The first byte contains the mean value for the first 64 pixels of the middle 128 pixels and the second byte contains the mean value for the latter 64 pixels of the middle 128 pixels. The 128 pixels comprise the standard 120 visible pixels, the 4 border pixels and an extra 4 border pixels that are never enabled as visible pixels but are used for exposure control and hence contribute to the mean pixel value for the line. If the line type is not visible then the two bytes following the end of line sequence will contain 07H 07H. For the remainder of the interline period the data output is always FFH. Sensor status and configuration information is output during the frame start line, (line 0), each data byte is separated by a blank value (07H) to avoid possible false line start conditions being generated. The information output during the status line reflects, if the sensor is operating in 8bit ADC mode, the first 64 locations in the serial interface register map. If the sensor is operating in 4 bit mode less data can be output during the status line. All the serial interface registers are 8bit values therefore 2, 4bit pixel periods are required to output a single serial interface location. Note that the serial interface data is only output during the visible monochrome pixels of the status line. This allows for one quarter of the serial interface address space to be output during any status line. It is possible to select the remaining registers in the serial interface for output, (see serial interface register setup 2, bits 7:6). The “end of frame” line, it is actually 2 lines prior to the status line will output the 4 exposure control bin averages during the first 4, (or 8 if operating in 4bit modes), monochrome pixels. Again the data is separated by mode dependent padding data. cd34011-b.fm Pr 17/10/97 el im in ar y 14 VV5300 Sensor Escape/Sync Sequence 8-wire output mode 4-wire output mode Command (Line Code) 1 C2 C1 C0 P3 P2 P1 P0 Nibble XH Nibble YH FFH FFH 00H XYH D3D2 D1D0 FH FH FH FH 0H 0H XH YH D3 D2 D1 D0 Supplementary Data (i) Line Number (L11 MSB) 0 L11 L10 L9 L8 L7 L6 P Nibble D3 Nibble D2 or (ii) If Line Code = End of Line then 0 L5 L4 L3 L2 L1 L0 P Nibble D1 Nibble D0 Mean Pixel Value for second half of the line Odd word parity Line Code End of Line Blank Line (BL) Black line (BK) el im Nibble XH [1 C2 C1 C0] 10002 (8H) 10012 (9H) in 10102 (AH) 10112 (BH) Visible Line (VL) Start of Frame (SOF) End of Frame (EOF) Reserved Reserved Pr 11002 (CH) 11012 (DH) 11102 (EH) 11112 (FH) Line Level Formatting cd34011-b.fm 17/10/97 ar Mean Pixel Value for first half of the line N7 N6 N 5 N4 N3 N2 N 1 N0 y M7 M6 M5 M4 M3 M2 M1 M0 Nibble YH [P3P2P1P0] 00002 (0H) 11012 (DH) 10112 (BH) 01102 (6H) 01112 (7H) 10102 (AH) 11002 (CH) 00012 (1H) 15 VV5300 Sensor Line Start Sequence FFH FFH 00H C7H LN LN 07H 07H 07H 07H SD 07H Sensor Status Data SD 07H SD 07H SD 07H SD 07H SD 07H FRAME START Line Start Line Type Line Number Line End Sequence Inter-Line Period 07H FFH FFH FFH FFH FFH Next Line Start FFH FFH 00H SD 07H SD 07H 07H 07H 07H 07H FFH FFH 00H 80H 07H Line End Line Start Sequence Black Level Pixel Values (Nominally - 10H) LN 07H 07H 07H 07H PV PV PV PV PV PV PV PV PV PV PV PV BLACK FFH FFH 00H ABH LN Line Start Line Type Line Number Line End Sequence Inter-Line Period 07H FFH FFH FFH FFH FFH Next Line Start FFH FFH 00H PV PV PV PV Line End Line Start Sequence Blank Level (07H) LN 07H 07H 07H 07H 07H 07H 07H 07H 07H BLANK ar 07H 07H 07H FFH FFH FFH 160 Visible Pixels PV PV PV PV MN FFH FFH FFH 07H MN 07H 07H FFH FFH FFH y 07H Inter-Line Period PV Inter-Line Period MN Inter-Line Period 07H 07H 07H 07H FFH FFH 00H 80H 07H Line Start Line Type Line Number Line End Sequence 07H 07H 07H 07H 07H 07H in 80H 07H PV PV 80H MN Line Mean Values 07H MN 80H 07H FFH FFH 00H 9DH LN 07H 07H 07H 07H Next Line Start FFH FFH FFH FFH 00H el im 07H 07H FFH FFH 00H Line End 07H 07H PV Line Start Sequence Black = 10H - White = F0H PV PV PV PV VISIBLE FFH FFH 00H B6H LN LN 07H 07H Line Start Line Type Pr Line Number Line End Sequence FFH FFH 00H Next Line Start FFH FFH FFH FFH 00H PV PV PV PV 07H 07H 07H 07H Line End Line Start Sequence FFH FFH 00H DAH LN LN 07H 07H 07H 07H 07H MN Frame Mean Values 07H 07H 07H 07H FRAME END Line Start Line Type Line Number Line End Sequence Next Line Start FFH FFH FFH FFH 00H 07H 07H 07H 07H 07H 07H 07H 07H FFH FFH 00H Line End Line Coding cd34011-b.fm 17/10/97 16 VV5300 Sensor 8-Wire Parallel Mode 8-Wire parallel mode is selected when the appropriate bits are set via the serial interface. When 8-bit conversion mode is selected the 8-bit pixel data is output on pins DATA[7:0]. The start of a frame is indicated by a pulse on FST. The data is valid on the falling edge of the pixel sample clock fast QCK (QCKF) or on each edge of the slow QCK (QCKS). Line Start Line Type Line No. DATA[7:0] QCKF QCKS Line End DATA[7:0] P117 P118 P119 P120 07H QCKF QCKS 07H 07H 07H FFH FFH 00H 80H FFH FFH FFH 00H B6H LN LN 07H 07H 07H 07H P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Line Mean MN MN FFH y FFH FFH P12 P13 P14 P15 P16 P17 FFH FFH FFH FFH 00H 8-Wire Parallel Mode (8-bit Pixel Data) Line Start Line Type Line No. DATA[7:4] DATA[3:0] QCKF QCKS FH FH FH FH FH FH 0H 0H BH 6H LN LN LN LN el im 1H 1H P0 P1 P2 P3 When 4-bit conversion mode is selected the 4-bit pixel data is output two bytes at a time on the DATA[7:0] pins. The first pixel is mapped onto DATA[7:4] and the second pixel is output on DATA[3:0]. This effectively doubles the pixel rate (and halves the frame period). in P4 P5 P6 P7 P8 P9 ar 1H P10 P11 P18 P19 P20 P21 P22 P23 P24 P25 Pr 1H Line End DATA[7:4] P102 P104 P106 P108 P110 P112 P114 P116 P118 1H DATA[3:0] QCKF QCKS P103 P105 P107 P109 P111 P113 P115 P117 P119 1H 1H 1H FH FH FH FH 0H 0H 8H 0H Line Mean MN MN MN MN FH FH FH FH FH FH FH FH 0H 0H 8-Wire Parallel Mode (4-bit Pixel Data) cd34011-b.fm 17/10/97 17 VV5300 Sensor 4-Wire Parallel Mode 4-Wire parallel mode is selected when the appropriate bits are set via the serial interface. When 8-bit data conversion mode is selected (CONV8 = 1) the 8-bit pixel data is output on pins DATA[7:4] in two 4-bit nibbles. The start of a frame is indicated by a pulse on FST. A QCK sample edge is generated for each nibble. Line Start DATA[7:4] QCKF QCKS FH FH FH FH FH 0H 0H Line Type BH 6H LN Line No. LN LN LN 0H 7H 0H 7H 0H 7H 0H 7H P0 Line End DATA[7:4] P115 P116 P117 P118 P119 QCKF QCKS 0H 7H 0H 7H 0H 7H 0H 7H FH FH FH FH 0H 0H 8H 0H MN MN DATA[7:4] MN QCKF QCKS MN FH ar FH FH FH 0H LN 1H 1H 1H y FH FH FH FH FH FH FH FH 0H BH 6H LN LN LN LN 4-Wire Parallel Mode (8-bit Pixel Data) When 4-bit data conversion mode is selected (CONV8 = 0) the 4-bit pixel data is output on pins DATA[7:4]. Line Start DATA[7:4] QCKF QCKS FH FH FH FH FH el im Line Type BH 6H LN LN in Line No. LN 1H P0 P1 P2 P3 P4 Pr 0H 0H Line End DATA[7:4] QCKF QCKS P113 P114 P115 P116 P117 P118 P119 1H 1H 1H 1H FH FH FH FH 0H 0H 8H 0H MN MN FH FH DATA[7:4] FH QCKF QCKS FH FH FH FH FH FH FH FH FH FH FH FH FH 0H 0H BH 6H LN LN LN LN 4-Wire Parallel Mode (4-bit Pixel Data) cd34011-b.fm 17/10/97 18 VV5300 Sensor Serial Mode Serial mode is selected when the appropriate bits are set via the serial interface. When 8-bit data conversion mode is selected the 8-bit pixel data is output on pin DATA[0] least significant bit first. Line Start Line Type Line No. DATA[0] QCK FFH FFH FFH 00H B6H LN LN 07H 07H 07H 07H P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Line End DATA[0] QCK P116 P117 P118 P119 07H 07H 07H 07H FFH FFH 00H 80H MN MN FFH FFH FFH FFH FFH FFH FFH 00H Pixel_0 DATA[0] QCKF QCKS 0 1 2 3 4 5 6 7 0 1 2 3 Pixel_1 Pixel_2 5 6 7 0 1 2 3 Line Start DATA[0] QCK FH FH FH FH FH el im Line Type BH 6H LN LN When 4-bit data conversion mode is selected (CONV8 = 0) the 4-bit pixel data is output on pin DATA[0] least significant bit first. Line No. LN LN 1H 1H 1H 1H P2 P3 P4 P5 P6 0H 0H in 1H 1H 1H FH FH FH FH FH Serial Mode (8-bit Pixel Data) DATA[0] P111 P112 P113 P114 P115 P116 P117 P118 P119 QCK Pr ar Line End FH FH FH 0H 0H 8H 0H MN MN FH 0H 0H BH 6H LN LN LN LN 1H DATA[0] FH QCK FH FH FH FH FH FH FH FH Pixel_0 DATA[0] QCKF QCKS 0 1 2 3 0 y 4 Pixel_3 0 1 2 Pixel_1 1 2 3 0 Pixel_2 1 2 3 Pixel_4 3 0 1 2 3 Serial Mode (4-bit Pixel Data) cd34011-b.fm 17/10/97 19 VV5300 Sensor Serial UART Mode Serial UART mode is selected when the appropriate bits are set via the serial interface. When 8-bit data conversion mode is selected the 8-bit pixel data is output on pin DATA[0] least significant bit first. Each pixel is preceded by a start bit and followed by an additional data bit and two stop bits. Line Start Line Type Line No. DATA[0] FFH FFH FFH 00H B6H LN LN 07H 07H 07H 07H P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Line End DATA[0] P116 P117 P118 P119 07H 07H 07H 07H FFH FFH 00H 80H MN MN FFH FFH FFH FFH FFH FFH FFH 00H Pixel_0 DATA[0] Pixel_1 5 6 7 0 1 2 3 4 0 y 1 2 3 1H 1H 1H P0 4 5 6 7 Start Bit Unused Data Bit Two Stop Bits Serial UART Mode (8-bit Pixel Data) Line Start DATA[0] FH FH FH FH FH el im Line Type 0H 8H LN LN When 4-bit data conversion mode is selected the 4-bit pixel data is output two pixels at a time on pin DATA[0] least significant bit first. Each pixel is preceded by a start bit and followed by an additional data bit and two stop bits. in Line No. LN LN 1H 1H 1H FH FH FH FH ar 1H P1 P2 P3 P4 Least Significant Bit First 0H 0H DATA[0] Pr Line End FH FH FH 0H 0H 0H EH MN MN P111 P112 P113 P114 P115 P116 P117 P118 P119 1H DATA[0] MN MN FH FH FH FH FH FH FH FH FH 0H 0H 0H 8H LN LN LN LN Pixel_0 DATA[0] 0 1 2 3 0 Pixel_1 1 2 3 0 1 Pixel_2 2 3 0 Pixel_3 1 2 3 Least Significant Bit First Start Bit Unused Data Bit Two Stop Bits Serial UART Mode (4-bit Pixel Data) cd34011-b.fm 17/10/97 20 VV5300 Sensor Qualifying the Output Data Data is output from VV5300 in a continuous stream. By utilising signals, like FST, and key events, like the start of a line or the end of line, the user can sample and display the image data. QCK is used to sample the data, as described in the previous section. By default the falling edge of QCK will sample the data, however it is possible to use both the rising and falling edges of a slow QCK QCKS to sample the data. Different sections of the frame can be enabled by QCK. The options, which are selected via setup register4 in the serial interface, are as follows, firstly the QCK can be disabled, therefore no data will be qualified. This is the default option. The second option is to have the QCK free running where all the data is qualified. The third option is to only qualify the image data, which also includes the 2 black calibration monitor lines, lines 1 and 2 in the frame. This option is further complicated in that extra black lines and the extra border pixels/lines can be enabled giving the following 4 options: 1. Black lines (1-2) plus image (160 pixels by 120 lines) 2. Black lines (1-8) plus image (160 pixels by 120 lines) 3. Black lines (1-2) plus image (164 pixels by 124 lines) 4. Black lines (1-8) plus image (164 pixels by 124 lines) QCK Exceptions The output data from VV5300 can be formatted in many ways, as detailed in an earlier section of this document. Under certain operating conditions the relationship between QCK and the output data is compromised. It is vital that the phase relationship between the output data stream and the QCK must be maintained from line to line, for example ensuring that, if enabled, the line code byte is always qualified by the same edge of the QCK, clearly only applicable when considering slow QCK qualification. It is known that there are an odd number of pixel periods in each line of the frame. If the slow QCK is selected then clearly two pixels are qualified during each QCK cycle resulting in the following modes of operation requiring special care: 4 bit ADC 8 wire output, 8 bit ADC 8 wire output and 4 bit ADC 4 wire output. During the interline period, when the data bus is outputting data fixed at FF (8bit ADC) or F (4bit ADC), the phase of the QCK is toggled, this will occur during every interline period. For the 8bit 8wire or 4bit 4 wire options this change is a simple inversion. The 4bit 8wire option is not quite as straightforward. During the interline period the QCK signal is changed from its former state to 1 of 3 other states. In addition 2 out of the 4 possible states are video timing mode dependent. Please note that the number of nibbles/bytes qualified by the clocks described above, during the free running QCK mode, will differ from the expected value, as follows: cd34011-b.fm Pr el im The final option is to qualify the embedded frame control sequences as well as the image data. These control sequences are the 6 bytes at the start and at the end of each image line, where an image line is defined above. The frame start or status line, image and control sequence pixels, will also be qualified during this mode. 17/10/97 in ar y 21 VV5300 Sensor QCK Exception Details Number of pixels qualified 50 frames per second QCKF 4bit 4wire 4bit 8wire 8bit 8wire 203 202 203 QCKS 202 198 202 Number of pixels qualified 60 frames per second QCKF 301 300 301 QCKS 300 298 300 Operating Mode Pixel qualification exceptions Serial Interface - Exposure Control Handshake The process of writing timed exposure, clock division or gain settings to VV5300 using the serial interface requires special attention. These timed parameters can be written to the serial interface at any point within the frame timing but will only be transferred from shadow registers to their active registers at a specific point within the frame timing, see diagram below. Please note that writing immediate clock division or gain parameters are treated as a “normal” serial interface write messages. odd frame flag old_exp el im old_gain old_clock_div in new_exp new_clock_div new_gain Pr cd34011-b.fm 1 frame period Since the new external exposure, clock division or gain settings are written to shadow registers the user continues to have full read/write access to the serial interface. A handshake system has been implemented between the exposure controller and the serial interface to avoid the user writing, for example, a second external timed gain value while the exposure controller has yet to transfer the first external timed gain value from the shadow register to the active register. If an external timed gain message has been written a special flag will be raised to indicate that it has yet to be transferred to the active register. This flag is available to the user via reading the status 0 register in the serial interface. Until the flag is lowered the user knows that it is not safe to write a further external gain value. Identical handshake protocols are used to implement timed external exposure and clock division writes. 17/10/97 ar y 22 VV5300 Sensor Auto Black Calibration Black calibration is used to remove voltage offsets that cause shifts in the black level of the video signal. VV5300 is equipped with an automatic function that continually monitors the output black level and calibrates if it has moved out of range. Black calibration can be split into two stages, monitor (1 cycle) and update (3 cycles). During the monitor phase the current black level is compared against two threshold values. If the current value falls outside the threshold window then an update cycle is triggered. The update cycle can also be triggered by a change in the gain applied to sensor core or via the serial interface. Serial Interface In order to be controlled and configured by its host, VV5300 can receive and transmit data via a two-wire serial interface. Serial Communication Protocol The host must perform the role of a communications master and the camera acts as either a slave receiver or transmitter.The communication from host to camera takes the form of 8-bit data with a maximum serial clock frequency of up to 100kHz. Since the serial clock is generated by the host it determines the data transfer rate. The bus address for VV5300 is 20H. Data transfer protocol on the bus is shown below. Start condition SDA MSB SCL S Read/Write bit Acknowledge from receiver el im 2 7 8 in 9 1 2 3-8 9 ACK P ACK 1 ar A DATA[7:0] DATA[7:0] Data Transfer Protocol A message contains at least two bytes preceded by a start condition and followed by either a stop or repeated start followed by another message. The first byte contains the device address byte which includes the data direction read/write bit. The device address is 3210 Write, 3310 Read. The 5 msbs of the address byte are fixed as 0010_02. The lsb of the address byte indicates the direction of the message. An even address causes the addressed slave to receive information from the master (write), an odd address indicates message read by the master. Sensor acknowledges valid address S address[7:1] 0010000 R/ W bit Pr Data format Acknowledge from slave A [0] A INC INDEX[6:0] y Stop condition A P Data Format After the read/write bit is sampled, the data direction cannot be changed, until the read/write bit next message is received. The next byte contains the location of the first data byte (also referred to as the index).There may be up to 128 such locations. If the msb of the second byte is set the automatic increment feature of the address index is selected. cd34011-b.fm 17/10/97 23 VV5300 Sensor Message interpretation All serial interface communications with the sensor must begin with a start condition. If the start condition is followed by a valid address byte then further communications can take place. The sensor will acknowledge the receipt of a valid address by driving SDA low. The state of the read/write bit (lsb of the address byte) is stored and the next byte of data can be interpreted. During a write sequence the second byte received is an address index and is used to point to one of the internal registers. The msbit of the following byte is the index auto increment flag. If this flag is set then the serial interface will automatically increment the index address by one location after each slave acknowledge. The master can therefore send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or sends a repeated start, (Sr). If the auto increment feature is used the master does not have to send indexes to accompany the data bytes. As data is received by the slave it is written bit by bit to a serial/parallel register. After each data byte has been received by the slave, an acknowledge is generated, the data is then stored in the internal register addressed by the current index. During a read message, the current index is read out in the byte following the device address byte. The next byte read from the slave device are the contents of the register addressed by the current index. The contents of this register are then parallel loaded into the serial/parallel register and clocked out of the device by scl. At the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. Although VV5300 is always considered to be a slave device, it acts as a transmitter when the bus master requests a read from the sensor. At the end of a sequence of incremental reads or writes, the terminal index value in the register will be one greater the last location read from or written to. A subsequent read will use this index to begin retrieving data from the internal registers. A message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation. The programmers model • Setup registers with bit significant functions including status (read only) bits • Exposure parameters that influence output image brightness. • System functions and test bit significant registers. Any internal register that can be written to can also be read from. cd34011-b.fm Pr There are 128, 8-bit registers within the camera, accessible by the user via the serial interface. They are grouped according to function with each group occupying a 16-byte page of the location address space. There are eight such groups, The primary categories are given below: el im 17/10/97 in ar y 24 VV5300 Sensor Index 000_0000 000_0001 000_0010 000_0011 Status 000_0100 000_0101 000_0110 000_0111 000_1000 000_1001 000_1010 000_1011 000_11xx 001_0000 001_0001 001_0010 Setup 001_0011 001_0100 001_0101 001_011x 001_1xxx 010_0000 010_0001 010_0010 010_0011 Exposure 010_0100 010_0101 010_0110 010_0111 010_1000 010_1001 010_101x 010_1xxx 111_0011 111_0101 System 111_1001 111_1010 111_1011 111_11xx Name R/W RO RO Default 1100 00002 (C0H) 0001 00102 (12H) 0000 10002 (08H) Comments Reserved System status information Current line counter value Average value of pixels in the first half of the current line. Average value of pixels in the second half of the current line. Average value of pixels in a frame. Partial frame average - bin1 Partial frame average - bin2 Partial frame average - bin4 Partial frame average - bin3 status0 unused line_count leftav rghtav frame_av bin1 bin2 bin3 bin4 unused setup0 setup1 setup2 setup3 setup4 unused unused unused unused fine unused coarse gain RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W - 0010_01112 (27H) 0111_00002 (70H) 0001_11112 (1FH) 0000_11112 (0FH) in 0000_0000 2 (00H) el im R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000_00002(00H) Pr 0111_00002 (70H) 0000_00002 (00H) 0000_00002 (00H) 0000_01112 (07H) 0101_01012 (55H) 1001_01102 (64H) 0110_01102 (73H) clk_div gn_lim tl tc th unused unused xfav dcth unused unused unused unused 1000_0000 2(80H) 1000_00002 (80H) The programmers model A detailed description of each register follows. The address indexes are shown as binary in brackets. cd34011-b.fm 17/10/97 ar Configure the digital logic Configure the digital logic Pixel counter reset value Exposure control modes FST/QCK options Fine exposure initially zero Coarse exposure Gain value Clock division Maximum allowable gain Lower exposure control threshold. Centre exposure control threshold. Upper exposure control threshold. External frame average Digital comparator threshold y 25 VV5300 Sensor Status 0 [000_00102] The loading of certain system parameters is timed to avoid disturbing the video signal part way through a frame. Bits 0-2 can be polled to check that a value written to either the exposure, gain or clock division registers has been consumed or not. Bit 3 is essentially an internal flag differentiating between consecutive frames. Bit 0 1 2 3 4 Function Exposure value update pending Clock division value update pending Gain value update pending Odd/even frame Black Calibration fail flag Default 0 0 0 0 0 Comment New exposure setting sent but not yet consumed by the exposure controller New clock division setting sent but not yet consumed by the exposure controller New gain value sent but not yet consumed by the exposure controller The flag will toggle state on alternate frames If the black calibration algorithm returns very poor black levels - outwith both the calibration and monitor windows then this flag will be set and it will stay set until the next successful calibration is complete 7:5 Unused 0 Status 0 [000_00102] Line_count [000_01002] Bits 7:0 Function Line count el im Default 0000_00002 in Comment Displays current line count Line_count [000_01002] Line_avg 0 [000_01012] & Line_avg 1 [000_01102] The exposure controller accumulates the pixel output values. On a line by line basis the accumulation is performed in two stages. The qualified pixels in the left half of the video line are accumulated and then stored in a latch. The process is then repeated during the right half of the video line. During the interline line period (up until the latch that stores the value for the left half of the line is updated during the next line) the latches will present valid average 8-bit pixel values for both halves of the line. Bits 7:0 Pr Function The video timing logic is controlled by the pixel counter and the line counter. To reduce the level of digital switching noise these counters implement a gray count sequence, where only a single counter register can change state in a clock period. However the gray count sequence is user unfriendly,e.q. 248,232,233, 235,234. A binary version of the line count is generated internally, realising a 0,1,2,3,4..... sequence, and it is this count sequence that is read by the serial interface and hence made available to the sensor user. Default 0 Line average Average pixel value for first half of current line. Line_avg 0 [000_01012] Bits 7:0 Function Line average Default 0 Average pixel value for second half of current line. Line_avg 1 [000_01102] cd34011-b.fm 17/10/97 26 ar Comment Comment y VV5300 Sensor Frame_avg [000_01112] The average pixel values stored in latches halfway through and at the end of each active video line are ultimately stored in bins that will maintain a frame sum of the pixel values. At the end of the frame the values stored in these bins are used to determine the overall pixel average for the whole frame. Bits 7:0 Function Frame average Default 0 Comment Pixel average for previous frame Frame_avg [000_01112] Bin1_avg [000_10002] Bits 7:0 Function Bin1 average Default 0 Comment Bin2_avg [000_10012] Bits 7:0 Function Bin2 average Default 0 in Bin3_avg [000_10102] Bits 7:0 Bin3 average Pr Function Function el im Default 0 Pixel average for current line Bin2_avg [000_10012] Pixel average for current line Bin3_avg [000_10102] Bin4_avg [000_10112] Bits 7:0 Default 0 Bin4 average Pixel average for current line Bin4_avg [000_10112] cd34011-b.fm 17/10/97 ar Comment Comment Comment 27 Bin1_avg [000_10002] y Pixel average for current line VV5300 Sensor Setup 0 [001_00002] Setup registers 0,1,2,3 and 4 are used to alter the operating parameters of the sensor. All of these registers can be written to and read from. Setup 0 register controls some fundamental exposure and output format parameters. Defaults are shown in Bold. Bit 0 1 Function Automatic exposure control. Off/On Clamp fine exposure Off/On Automatic gain control. Off/On Enable immediate gain update. Off/On Enable immediate clock division update. Off/On Data format select. Default 1 1 Comment Enables or disables automatic exposure control. Current exposure value is frozen when disabled. If this bit is set and aec is enabled and the coarse exposure has exceeded the clamp threshold, 16, then the fine exposure will be clamped to 0. Enables or disables automatic gain control. Current gain value is frozen when disabled. 2 3 1 0 4 0 Allow manual change to clock division to be applied immediately. 6:5 01 7 3/4 crystal clock Off/On Setup 1 [001_00012] Setup 1 register controls registers that are less likely to be modified on a regular basis. The user should note that the border pixels/lines can be disabled/enabled independently from the enabling/disabling of the custom analogue horizontal shift register. Bit 0 1 2 Pr Function el im 0 Setup0 [001_00002] Default 0 0 0 in 17/10/97 00 - 8 wire parallel output 01 - 4 wire parallel output 10 - 2 wire serial output 11 - 1 wire serial output Achieves clock division by 3 rather than 4. Enable additional black lines (3-8) Off/On Enable border pixels Off/On Enable horizontal shuffle mode. Off/On If enabled extra black lines are visible at device output Extends qualified image size to 164 x 124. Default image size is 160 x 120 The contents of the horizontal shift register are shuffled so that all the even columns then all the odd columns are read out. Setup1 [001_00012] cd34011-b.fm ar y Allow manual change to gain to be applied immediately. Comment 28 VV5300 Sensor Bit 3 Function Enable sample mode Off/On Default 0 Comment If enabled the data bus will continuously output a “96H” pattern. WIth the sensor in this mode a user can determine the best point at which to sample the data. Enables the output of serial interface status information on the data bus. By default the bottom 64 locations from the serial interface will be output. The analogue output ADC can be configured to convert to 4-bit or 8-bit resolution. The sensor will implement 60Hz like line timing by default giving reduced flicker operation with 60Hz source frequencies. If the supply frequency is 50Hz then 50Hz like timing should be selected. Normally the accumulator arithmetic logic calculates the frame average of the pixel samples. However if this bit is enabled then the user may specify a frame average. 4 Status line data output enable. Off/On 1 5 6 8-bit or 4-bit ADC select 50fps timing/60fps timing 1 1 7 Setup1 [001_00012] Setup 2 [001_00102] In many systems VV5300 will be continuously synchronised. During this synchronisation the video timing is reset to a fixed point within the frame timing. The counter reset value is definable. Bit 5:0 6 7 Function el im Default 0111112 0 0 Bit 6 0 1 0 - in Comment During synchronisation the pixel counter is reset to the defined value. Selects which system parameters are output on status line. See table below. Selects which system parameters are output on status line. See table below. Pixel counter reset value. Status information output option. Off/On Status information output option. Off/On Pr 0 0 1 Setup 2 [001_00102] Bit 7 Register Address Range 8-bit modes 00H - 3FH 40H - 7FH Status line information options cd34011-b.fm 17/10/97 29 ar Register Address Range 4-bit modes 00H - 1FH 20H - 3FH 40H - 5FH y External frame average Off/On 0 VV5300 Sensor Bit 7 1 Bit 6 1 Register Address Range 8-bit modes - Register Address Range 4-bit modes 60H - 7FH Status line information options Setup 3 [001_00112] Bit 3:0 Function Exposure control mode select. Autoload control Exposure step size Default 11112 Comment The average value for the frame that the exposure controller uses can be calculated in a number of different ways. See table below. Selects exposure step size. 1/8 for fast but jerky convergence to 1/64 for slow but smooth convergence. Default 1/16. 6:5 01 7 Unused 0 Note1: The state of this pin can affect the autoload function in a number of ways. 1. If the autoload bit is high continuously and the autoload pin is also high then an autoload will not take place. 2. If the autoload bit is initially high and is then forced low then an autoload will take place regardless of the state of the autoload pin. 3. If the autoload pin is initially high and is then forced low an autoload will take place regardless of the state of the autoload bit. 4. A low to high transition on either the autoload bit or the autoload pin while VV5300 is running will have no effect on the autoload function. Pr Bit 3 0 0 0 0 0 0 0 0 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 el im Bit 1 0 0 1 1 0 0 1 1 0 0 Bit 0 0 1 0 1 0 1 0 1 0 1 Frame Average Options cd34011-b.fm 17/10/97 in bin1 bin2 bin3 bin4 Setup 3 [001_00112] (bin1 + bin2) / 2 (bin3 + bin4) / 2 (bin1 + bin3) / 2 (bin2 + bin4) / 2 (bin1 + bin4) / 2 (bin2 + bin3) / 2 ar Function y 4 0 This bit controls the autoload feature.Note1 30 VV5300 Sensor Bit 3 1 1 Bit 2 0 0 Bit 1 1 1 Bit 0 0 1 Function (bin1 + bin2 + bin3 + bin4) / 4 (bin1 + bin2 + bin3 + bin4) / 4 Frame Average Options Bit 6 0 0 1 1 Bit 5 0 1 0 1 Step size 1/8 1/16 1/32 1/64 Comment Default Exposure step size options Setup 4 [001_01002] The QCK function has a dedicated pin assigned, however by selecting the appropriate bits the FST pin can also output QCK data. By default QCK is disabled. However by writing the appropriate message, QCK can be forced to free run, qualify the embedded coding sequences and the visible data or the visible data only. FST can also be enabled or disabled or alternatively the FST pin can output a timing signal to synchronise several VV5300 sensors or finally the FST pin can output the state of the custom analogue block successive approximation ADC output comparator. Bit 1:0 Function Pr el im Default 002 002 002 002 The data output on the serial wire or the 4 wire/8 wire busses can be qualified, if required, by an internally generated clock signal, QCK. This clock can be configured variously. Both a fast and a slow QCK can be generated. If the former is selected then the falling edge of the clock will qualify the current data nibble/byte, i.e. if the sensor is operating in 4 bit-4 wire mode then any true 8 bit data (e.g. line type code) will be qualified on a nibble basis. If the slow QCK option is preferred then both edges of this clock are used to qualify the current data nibble/byte. in FST pin 002 012 102 112 002 012 102 112 002 012 102 112 FST/QCK pin mode. ar y Mode QCK pin QCKS QCKF QCKS QCKF Normal FST Normal FST QCKF Inverted QCKF 3:2 QCK mode select disable free running validate control and image data validate image data only disable FST enable FST synchronisation pulse output (SNO) output ADC comparator output, CPO 5:4 7:6 unused FST mode select Setup 4 [001_01002] cd34011-b.fm 17/10/97 31 VV5300 Sensor Exposure Control Registers [010_00012] - [010_10012] There is a set of parameters that control the time that the sensor pixels are exposed. The parameters are as follows: fine and coarse exposure time, clock division control and finally gain control. The latter parameter does not affect the integration period rather it amplifies the video signal at the output stage of the sensor core. An internal automatic algorithm will, if enabled, continually monitor the pixel output and then, if required, use this data to correct the current exposure. Manually changing the divisor applied to the incoming crystal clock can alter the effective integration of the sensor. By slowing the internal clock down the integration period can be increased, i.e. halving the pixel clock frequency will double the integration period. If the user wishes to use the automatic exposure algorithm, the automatic exposure control (controlling fine and coarse exposure) must be enabled. Additional gain control is optional. It is also possible to change the gain manually via the serial interface even if the exposure is adjusted automatically. If a user wishes to write an external value to one of the automatic exposure algorithm registers then it is advised that the automatic control for that register be disabled prior to using the serial interface to write the external value. Each exposure parameter is subject to a maximum setting. The fine exposure setting can be clamped to a fixed value regardless of the decision made by the automatic algorithm. The clamping will occur if the coarse exposure setting exceeds a predetermined value and the clamping has been enabled via the serial interface. Bit 7:0 Function Fine exposure value Pr The automatic exposure algorithm uses a set of exposure threshold settings. These thresholds may also be modified by the user to alter the algorithm’s performance. The exposure algorithm uses these thresholds in a histogram. The three thresholds divide the histogram into 4 regions, very overexposed, overexposed, underexposed and very underexposed. The pixel data received from the sensor core is compared against the thresholds to determine the accuracy of the current exposure setting. A series of flags are set to describe the outcome of the histogram comparison and the new exposure setting can then be derived. el im Default Default Between writing the exposure data and the point at which the data is consumed by the exposure algorithm, bit 0 of the status register is set. The gain value is updated a frame later than the coarse and fine exposure parameters. The gain is applied directly at the video output stage and does not require the long set up time of the coarse and fine exposure settings. in 0000_00002 (00H) Fine Exposure Value [010_00012] Bit 7:0 Function Coarse exposure value 0111_00002 (70H) Coarse Exposure Value [010_00112] cd34011-b.fm 17/10/97 ar Note: The external exposure (coarse, fine or gain) values do not take effect immediately. Data from the serial interface is read by the exposure algorithm at the start of a video frame. If the user reads an exposure value via the serial interface then the value reported will be the data as yet unconsumed by the exposure algorithm, because the serial interface logic locally stores all the data written to the sensor. maximum fine (50Hz mode) = FFH maximum fine (60Hz mode) = A8H maximum coarse (50Hz and 60Hz modes) 91H y Comment Comment 32 VV5300 Sensor Bit 2:0 Function Gain value Default 0 Comment 8 possible gain states can be written via the serial interface Gain Value [010_01002] All 8 binary codes can be written to the core via the serial interface. Only the 4 thermometer codes 000,001,011 and 111 are selected by the automatic exposure algorithm. The 4 other codes are however still valid and will be evaluated as detailed in the table below. It is clear, from the non-linear relationship between the binary code and the actual gain applied at the analogue output stage, that care should be taken when using non thermometer code gain settings. If the user writes a gain code of 110 (real gain = 1.600) and then enables automatic gain control and the controller then decided to reduce the gain, the new gain value would be 011 (real gain = 4.000) i.e. the effective applied gain at the analogue output stage has actually been increased. Gain binary code 000 001 010 011 100 101 110 111 Actual signal gain 1.000 2.000 1.333 4.000 1.143 2.667 1.600 8.000 Bit 1:0 Pr Function Function el im Default 0 Clock divisor value System Gain in Default 7 Pixel clock = Crystal clock ÷2n+1 Clock Divisor Value [010_01012] The undivided input crystal clock is used by the clock generator circuitry, elements of the serial interface and a small number of other registers in the design. The remaining digital logic and the analogue circuitry, use internally generated clocks, namely the pixel clock and the faster ADC clocks. These clocks are all slower versions of the crystal clock. The ADC clocks may be up to half the crystal frequency, but can be further divided by factors of 2, 4 or 8. The pixel clock is in turn slower than the ADC clock. If the ADC is operating in 4 bit mode then the pixel clock is 1/4 the frequency of the ADC clock, otherwise the pixel clock will be 1/8 the frequency of the ADC clock. Bit 2:0 Gain limit Gain Limit[010_01102] cd34011-b.fm 17/10/97 33 ar Comment Comment y VV5300 Sensor Bit 7:0 Function Exposure lower threshold Default 85 Comment Exposure Lower Threshold [010_01112] Bit 7:0 Function Exposure centre threshold Default 100 Comment Exposure Centre Threshold [010_10002] Exposure Higher Threshold [010_10012] This register is read/write compatible Bit 7:0 Frame average Function el im The exposure controller normally compiles a frame average from the data received from the core. A complete frame period is required to produce a frame average. This is clearly unacceptable for simulation and test purposes. It is possible to manually force a frame average via the serial interface. This feature together with the ability to curtail the frame duration will allow the behaviour of the exposure controller to be examined in a realistic simulation period. in Default 0 Frame Average [111_00112] Pr Frame Average [111_00112] Digital Comparator Threshold [111_01012] The ADC output from the CAB can be digitally compared against a digital threshold. This threshold is fully programmable via the serial interface register. If the current ADC output is greater than or equal to the programmed threshold then the modified ADC output will be forced to the full scale output. The full scale value is mode dependent:- 224 for 8 bit ADC conversion or 14 for 4 bit conversion. If the current ADC output is less than the threshold then the modified ADC output will be forced to minimum video. The minimum video setting (the black level) is again mode dependent:- 16 for 8 bit ADC conversion or 1 for 4 bit conversion. If this feature is not enabled, (tms[7] = 0), then the ADC output will pass unaltered. As indicated above the ADC can convert to either 4 bit or 8 bit accuracy. When operating in a 4-bit mode the threshold value should be packed to the 4 most significant bits of the register i.e. if the required threshold cd34011-b.fm 17/10/97 ar Comment Allow a synthetic frame average to be written to and used by the exposure controller 7:0 Exposure higher threshold 115 y Bit Function Default Comment 34 VV5300 Sensor value is 10 then 160 should be written to the threshold register. Bit [7:0] Function Threshold for digital comparator Default 128 Comment The default has been set at the midrange video setting for 8 bit ADC conversion. The user must reprogram the register if the test is run when the ADC is converting to 4 bit accuracy. Digital Comparator Threshold [111_01012] cd34011-b.fm Pr 17/10/97 el im in 35 ar y VV5300 Sensor Types of messages This section gives guidelines on the basic operations to read data from and write data to the serial interface. The serial interface supports variable length messages. A message may contain no data bytes, one data byte or many data bytes. This data can be written to or read from common or different locations within the sensor. The range of instructions available are detailed below. • No data byte, only sets the index for a subsequent read message. • Single location multiple data write or read for monitoring for real time control • Multiple location, multiple data read or write for fast information transfers. Examples of these operations are given below. A full description of the internal registers is given in the previous section For all examples the slave address used is 00100002=3210 for writing and 00100012=3310 for reading. This corresponds to applying logical zero to both the sab0 and sab1 inputs. Single location, single data write. 00100000 A 0 S el im 0 in A A When a random value is written to the sensor, the message will look like this: ar y 010_0000 0101_0101 A P In this example, the coarse (index = 01000002=3210) exposure value has been written as 010101012. The r/ w bit is set to zero for writing and the inc bit is set to zero to disable automatic increment of the index after writing the value. The location is preserved and may be used by a subsequent read. Single location, single data read. A read message always contains the index used to get the first byte. 00100001 A S 010_0000 0101_0101 A P This example shows a coarse (index = 3210) value of 0101_01012 been read. Note that the read message is terminated with a negative acknowledge (A) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. This is because if the data sent by the slave is all zeros, the sda line cannot rise, which is part of the stop condition. cd34011-b.fm Pr 17/10/97 36 VV5300 Sensor No data write followed by same location read. When a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written first, specifying the index. The read message then completes the message sequence. To avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the write and read messages. In this example, the gain value (index = 3610) is read as 1510: No data write S 3210 A0 3610 A Sr 3310 Read index and data A0 3610 A 1510 A P As mentioned in the previous example, the read message is terminated with a negative acknowledge (A) from the master. el im 210 A 010 Write setup1 S 2016 A0 in A The message sequence indexes setup1 register and initially turns ABC off. The next two data bytes then turn ABC on and then finally off again, leaving it in the default state. ar 12810 It may be desirable to write a succession of data to a common location. This is useful when the status of a bit,(e.g. requesting a new black calibration), must be toggled. Toggle “Force Black Cal.”. A 010 AP Turn off ABC Same location multiple data read When an exposure related value (coarse, fine, acc or gain) is written, it takes effect on the output at the beginning of the next video frame, (remember that the application of the gain value is a frame later than the other exposure parameters). To signal the consumption of the written value, a flag is set when any of the exposure or gain registers are written and is reset at the start of the next frame. This flag appears in status0 register and may be monitored by the bus master. To speed up reading from this location, the sensor will repeatedly transmit the current value of the register, as long as the master acknowledges each byte read. In the next example, a fine exposure value of 0 is written, the status register is addressed (no data byte) and then constantly read until the master terminates the read message. cd34011-b.fm Pr 17/10/97 y Same location multiple data write. 37 VV5300 Sensor Write fine with zero S 2016 A 2210 0 A 0 A Sr Address the status0 reg. 2016 A 010 A Read continuously... Sr 2116 A 010 0A 1 A 1 A 1 A ...until flag reset 1 A 0 AP Multiple location write If the automatic increment bit is set, msb of the first data byte following the byte that contains the slave device address, then it is possible to write data bytes to many adjacent internal registers. A write to the black calibration parameters with their default values is shown in the following example. . Incremental write S 2016 A1 9610 A 816 in A 3310 A1 3210 ar A A Multiple location read In the same manner, multiple locations can be read with a single read message. In this example the index is written first, to ensure the exposure related registers are addressed and then all seven are read Pr No data write A1 el im 3210 A A Sr Incremental read S 3210 y 3216 A AP coarse A Incremental read fine A gain gn_lim A T1 Tc T2 A P Note that a stop condition is not required after the negative acknowledge from the master. cd34011-b.fm 17/10/97 38 VV5300 Sensor Serial Interface Autoload VVL_300 can be configured automatically at power-up with any user defined set of system parameters using the serial interface auto-load feature. An external E 2PROM is used to store the configuration data. Both shortly after power up and in response to an off-sensor ‘soft’ reset on SIN, the auto-loader will interrogate the E2PROM to determine whether or not valid data is present. If no E2 device is detected the auto-loader will shut-down and the serial interface register values will not be changed from their existing values. If, however, an E2 device is detected, the auto-loader will begin to load data into the parameter registers from starting from location zero in the E2. The first byte is a register header code which determines the destination of the following data byte. This simple index & data format allows any sub-set of the VVL_300 registers map to be configured at power-up and it allows them to be stored in the E2 in any order. If the auto-loader detects the ‘end-of-PROM-contents’ code 00h, it will then issue a STOP condition on the serial interface, raise a flag to indicate that the parameters have been loaded and close down. 00h xxh ROM empty or end of data cd34011-b.fm Pr 17/10/97 el im Parameter header into which the following byte is to be written. E2PROM header bytes in Header ROM contents ar y 39 VV5300 Sensor Serial Interface Timing stop start start stop SDA ... tbuf tlow tr tf thd;sta SCL ... Serial Interface Timing Characteristics Parameter SCL clock frequency Bus free time between a stop and a start Hold time for a repeated start LOW period of SCL HIGH period of SCL Symbol fscl tbuf in Min. 0 *** *** *** *** *** *** *** *** - ar Max. *** *** *** *** all values referred to the minimum input level (high) = 3.5V, and maximum input level (low) = 1.5V y thd;sta thd;dat thigh tsu;dat tsu;sta tsu;sto Unit kHz us us us us us us ns ns ns us pF Set-up time for a repeated start Data hold time Pr Data Set-up time Rise time of SCL, SDA Fall time of SCL, SDA Set-up time for a stop Capacitive load of each bus line (SCL, SDA) cd34011-b.fm el im thd;sta tlow thigh tsu;sta thd;dat tsu;dat tr tf tsu;sto Cb Serial Interface Timing Characteristics 17/10/97 40 VV5300 Sensor EXAMPLE SUPPORT CIRCUIT Vin +8 to +12v dc C1 IC2 C2 C3 R1 C4 19 30 14 VDD3 VDD1 VDD2 9 AVCC 13 DVDD R2 C5 R3 C6 C17 GND 0v VDD 37 40 C18 20 29 35 AUTOLOADB VSS1 VSS2 VSS3 D[0] D[1] D[2] D[3] D[4] D[5] D[6] DVSS AGND IC1 VREG (48 pin LCC) 28 27 26 y C16 8 7 VCC TEST SCL SDA 6 5 36 6 25 24 23 R4 1 47 VRT VV5300 in D[7] QCK FST SIN CE TEST HPIX SDA SCL 33 R5 C14 D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] QCK FST SIN el im VCM/VREF2V5 VCDS VBLTW VBG VBLOOM CLKO CLKI 31 R7 R8 C17 C16 32 34 C12 C13 C11 2 C7 45 C8 46 Pr C9 ar 22 21 17 16 15 38 3 4 R6 C15 44 CE TEST HPIX C10 Optional E2 for configuration autoload IC3 E2PROM A0 A1 A2 GND 1 2 3 4 SCL SDA cd34011-b.fm 17/10/97 41 VV5300 Sensor Component IC1 IC2 IC3 C3 C1,C2, C4-C11 C12, C13 C14, C15 C16, C17 C18 R1 R2 R3 R4 R5, R6 R7 R8 Part No. / Provisional Value VV5300 7805 24C01 10.0 µF 0.1 µF 4.7 µF 100pF 22pF 1nF Rating / Notes VVL camera chip (48 pin LCC) 5V regulator E2PROM SOIC (8 pin) 0Ω 33Ω 2k2Ω 1MΩ 10Ω cd34011-b.fm Pr 17/10/97 el im in 42 ar 0Ω y 0Ω VV5300 Sensor VLSI VISION LIMITED UK Headquarters USA Western Office USA Eastern Office cd34011-b.fm Pr VLSI Vision agent or distributor el im VLSI Vision Ltd. reserves the right to make changes to its products and specifications at any time. Information furnished by VISION is believed to be accurate, but no responsibility is assumed by VISION for the use of said information, nor any infringements of patents or of any other third party rights which may result from said use. No license is granted by implication or otherwise under any patent or patent rights of any VISION group company. © Copyright 1996, VLSI VISION 17/10/97 in ar Aviation House, 31 Pinkhill, EDINBURGH EH12 7BF Scotland Tel:+44 (0) 131 539 7111 Fax:+44 (0)131 539 7141 eMail: info@vvl.co.uk 1190 Saratoga Ave., Suite 180, SAN JOSE CA 95129 USA Tel: +1 408 556 1550 Fax: +1 408 556 1564 eMail: info@vvl.co.uk 571 West Lake Avenue, Suite 12, BAY HEAD NJ 08742 USA Tel: +1 732 701 1101 Fax: +1 732 701 1102 eMail: info@vvl.co.uk y 43