VV5430

VISION V V 5430 Monolithic Sensor Integrated CMOS Image Sensor with support for ADC and external control via serial interface PRODUCT DATASHEET DISTINCTIVE CHARACTERISTICS • • • • • • Complete Video Camera on a single chip EIA/CCIR standard compatible Low power operation (250mW Typical) Integral 75Ω driver Frame & line timing signals for external ADC Optional image output in four quarters, with output driver tristate option for multiplexing • • • • • • Automatic Exposure and Gain Control Automatic Black Level Calibration Linear or Gamma corrected output option Control options pin selectable for ease of use External control/configuration via serial interface Industry standard 48 pin LCC package GENERAL DESCRIPTION The VV5430 is a highly-integrated VLSI camera device based on VISION’s unique CMOS sensor technology. It is suitable for applications requiring minimum external circuitry, digitisation of the video signal or external microprocessor control. The device incorporates a 388 x 295 pixel image sensor and all the necessary support circuits to generate composite video into a 75Ω load. Additional control signals support pixel locked digitisation of the video signal. Pr BLOCK DIAGRAM el DIGITAL CONTROL LOGIC. AGC AEC RESETB LIN BKLIT CCIR im ANALOG VOLTAGE REFS. VIDEO BUFFER AVO VIDEO AMP A bi-directional serial interface and internal register set allow full control and monitoring of all camera functions. Automatic control of exposure, gain and black level give a wide range of operating conditions. All major control functions are pin selectable giving maximum flexibility with ease of use. The VV5430 offers a complete camera system ideally suited for integration into digital imaging systems. in VRT Vbloom VOFF VBG EBCK EVWT 2V7 ar Pixel Format Pixel Size Array Size Min. illumination S/N Exposure control Gain Control Power Supply Power Temperature VERTICAL SHIFT REGISTER PHOTO DIODE ARRAY CKOUT CKIN SIN CPE FST LST PV PVB ODD SDA SCL SAB0 SAB1 CLOCK CIRCUIT COLUMN SENSE AMPLIFIERS IMAGE CAPTURE SAMPLE & HOLD 5V SERIAL I/F HORIZONTAL SHIFT REGISTER cd27033c.fm y 384 x 287 (CCIR) 320 x 243 (EIA) 12µm x 12µm 4.66mm x 3.54mm 0.5 lux (Standard Clock) Typically 52dB Automatic (to 146000:1) Up to +20dB 5v ±5% < 300 mW 0oC - 40oC 1 VISION V V 5430 Sensor MAIN FEATURES The VV5430 delivers a fully-formatted composite monochrome video signal. Standards options include EIA (320 x 244) and CCIR (384 x 287). On chip signal conditioning allows user-selection of linear or gammacorrected output. Different operational modes can be selected dynamically via the external interface or configured at power up by tying the appropriate pins. Extensive use of automated operation and on chip references means that only a small number of passive components are needed to realise a complete video camera. Automatic Exposure and Gain Control The VV5430 features automatic exposure control that allows a single fixed-aperture lens to be used, and incorporates Normal and Backlit modes to give operation over a wide range of scene types. The system clock frequency can also be reduced to provide increased sensitivity. Serial Interface A bi-directional serial interface allows an external controller to set operational parameters and control exposure and gain values directly. The host can also interrogate VV5430 via the serial interface to determine the camera’s operating modes and current state. This allows alternative automatic exposure and other control algorithms to be run in an external controller if the integrated versions are not suitable. The VV5430 receives and transmits control and parametric data via a full duplex, two-wire serial interface. The host is communications master, with the camera either a slave receiver or transmitter. Messages consist of either three or five bytes of 8-bit data, with a maximum serial clock frequency of 100kHz. Since the serial clock is generated by the host, the host determines the data transfer rate. Video Output The integrated 75Ω driver eliminates the need for additional active components to drive standard loads, including double terminated lines. The video signal can also be inhibited by setting the output to a high impedance state (‘Tristated’), which enables multiplexing of a number of different sensors. This, together with vertical and horizontal ‘shuffle’ modes, means that four sensor images can be shown simultaneously on one display. Frame, line and pixel timing signals are provided to facilitate pixel locked digitisation of the analog video data. In addition to the these outputs a synchronisation input (SIN) is also provided to allow the start of frame to be synchronised to an external event. Pr el im Contents Main Features Specifications Pin List Video Standards Image Digitisation Shuffle Modes Exposure Control Serial Communication Read Data from Camera Write to Camera Example Support Circuit 2 in ar y page 2 3 7 9 12 14 17 19 21 22 31 09/04/97 Specifications SPECIFICATIONS Package Details 0.51 TYP 1.56 TYP 0.55 0.53 13.7 Glass Lid Die Base 0.5 0.86 Viewed from side The optical array is centred within the package to a tolerance of ± 0.2 mm, and rotated no more than ± 0.5o Tolerances on package dimensions ±10% 2.16 PIN 1 1.016 PITCH TYP 14.22 Viewed from below Spectral Response Normalised Response el Pr im 1.0 0.8 0.6 0.4 0.2 1000 400 500 600 700 800 900 1100 0 Wavelength nm Absolute Maximum Ratings Parameter Supply Voltage Voltage on other input pins Temperature under bias Storage Temperature Maximum DC TTL output Current Magnitude -0.5 to +7.0 volts in Value -0.5 to VDD + 0.5 volts -15oC to 85oC -30oC to 125oC 10mA (per o/p, one at a time, 1sec. duration) Note: Stresses exceeding the Absolute Maximum Ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. 09/04/97 3 ar All dimensions in millimetres y Glass lid placement is controlled so that no package overhang exists. VISION V V 5430 Sensor DC Operating Conditions Symbol VDD VIH VIL TA Parameter Operating supply voltage Input Voltage Logic “1” Input Voltage Logic “0” Ambient Operating Temperature Min. 4.75 2.4 -0.5 0 Typ. 5.0 Max. 5.25 VDD+0.5 0.8 70 Units Volts Volts Volts oC Notes Still air AC Operating Conditions Symbol CKIN CKIN SCL Parameter EIA Crystal frequency CCIR Crystal frequency Serial Data Clock Min. Typ. 12.0000 Max. Units MHz MHz KHz Notes 1 1 2 Electrical Characteristics Symbol Parameter im in Min. Typ. 10 25 35 1.22 2.4 -1 1. Pixel Clock = CKIN/2 2. Serial Interface clock must be generated by host processor. ar y 100 Max. Units mA mA mA Volts Volts Volts 0.6 Volts µA 1 µA 2.700 14.7456 Notes 1 1 1 IDCC IADD IDD VREF2V7 VBG VOH VOL Pr el Digital supply current Analog supply current Overall supply current Output Voltage Logic “1” Output Voltage Logic “0” Internal voltage reference Internal bandgap reference IOH = 2mA IOL = -2mA IILK Input Leakage current VIH on input VIL on input Typical conditions, VDD = 5.0 V, TA = 27oC 1. Digital and Analogue outputs unloaded - add output current. 4 cd27033c.fm Specifications Operating Characteristics Parameter Dark Current Signal min. typ. 50 max. units mV/Sec Note Modal pixel voltage due to photodiode leakage under zero illumination with Gain=1 (Vdark = (Vt1 - Vt2)/(t1-t2), calculated over two different frames VAve/Lux·10ms, where Lux gives 50% saturation with Gain=1 and Exposure=10ms Standard CCIR clock Variance of Vave over eight equal blocks at 66% saturation level illumination RMS variance of all pixels, at 66% saturation, over four frames Ratio of Vave of the area outside a rectangle 25 lines high illuminated at 500xV50% level to VAve of the rectangle Variation of Vave of one line from field to field at 66% saturation level illumination Sensitivity Min. Illumination Shading Random Noise Smear 6 0.5 TBA -52 TBA V/Lux·Sec Lux % dB % Flicker Lag TBA TBA % % Blooming TBA im All voltage (VA, Vave, Vsat, Vxx%) measurements are referenced to the black level, Vblack, and spot blemishes are excluded (see Blemish Specification below). Vxx% refers to the output that is xx% of saturation, that is peak white. Test Conditions Illumination Colour Temp. Pr Note: Devices are normaly not 100% tested for the above characterisation parameters, other than Dark Current Signal (see Blemish Specification below). el in ar Exposure Gain Average residual signal with no illumination in the field following one field of 66% sat. illumination Ratio of spot illumination level that produces 0.1xVsat output from immediately around the spot to the Vsat spot illumination level (pinhole target) y 3200o K Std. CCIR Maximum x1 Off Linear The sensor is tested using the example support circuit illustrated later in this document. Standard imaging conditions used for optical tests employ a tungsten halogen lamp to uniformly illuminate the sensor (to better than 0.5%), or to illuminate specific areas. A neutral density filter is used to control the level of illumination where required. Clock Frequency Auto. Gain Control (AGC) Correction mode 09/04/97 5 VISION V V 5430 Sensor Blemish Specification A Blemish is an area of pixels that produces output significantly different from its surrounding pixels for the same illumination level. The definition of a Blemish Pixel varies according to testing conditions as follows: Test 1 - Black Frame 2 - Dark Current 3 - Pixel Variation Exposure Minimum Maximum Mid range Illumination Black Black 66% Sat. Blemish Pixel output definition Differing more than ± 100 mV. from modal value. Output more than three times the modal value (see Dark Current Signal above). Differing more than ±35mV from modal value. Note: The mode of pixel values must be within ±70 mV of 66% of Vsat for all devices. Note: Gain is set to Minimum and Correction set to Linear for all tests; measurement of blemishes for Test 3 is conducted under standard illumination (see above), set to produce average output of 66% saturation level. The pixel area of the sensor is divided into the following areas to qualify the blemish specification: Area B is the remaining area of the array. Pr el Max. No. of Blemishes 0 4 1 Any number Area C is 10 vertical pixels by 10 horizontal pixels around the edge of the array. im Area A is the central area of the array as defined by the box with sides 50% of the linear height and 50% of the linear width of the array. in ar y Notes Area A Area B Area C The blemish specification is then defined as follows: Image Area Area A Area B Of up to four connected pixels (2x2 max.) Blemishes in this area are not significant, but the device shall, however, have no row or column (>50% of row or column) faults in any area. Area C This is the most critical image area Unconnected single pixels 6 cd27033c.fm Pin List Pinout Diagram RESETB CKOUT BKLIT SAB0 CCIR CKIN AGC VDD LST AEC VSS 30 29 28 27 26 25 24 23 22 21 20 19 VSS 31 PV 32 PVB 33 VDD 34 CPE 35 FST 36 Viewed from top of package ODD 37 SCI 38 SCL 39 SDA 40 VDD 41 VSS 42 LIN 18 SCE 17 SIN 16 SAB1 15 VGND 14 AVO 13 VVDD 12 AMP2 11 AMP1 10 AVSS 9 8 7 48 Pin LCC y 43 44 45 46 47 48 1 VBLWT VBLOOM VRT VREF2V7 AGND VCM EVWT EBCK AVDD ar 2 3 4 5 AVCC VBG DEC2V2 VOFF/ VPED DEC2V7 6 DNC PIN LIST Pin Name Type el 75ohm buffer supply. 75ohm buffer ground. Digital padring & logic ground. Digital padring & logic power. Core digital power. Core digital ground. im Description POWER SUPPLIES 1 7 10 13 15 24,31 27,34 41 42 48 AVCC AVDD AVSS VVDD VGND VSS VDD DVDD DVSS AGND 09/04/97 Pr PWR PWR GND PWR GND GND PWR PWR GND GND Core analogue power and reference supplies. output stage power. AVDD3 output stage logic. Output stage ground. AVSS3 output stage logic. Core analogue ground and reference supplies. in 7 VISION V V 5430 Sensor Pin Name Type Description ANALOGUE VOLTAGE REFERENCES 2 3 4 5 6 8 9 43 44 45 46 47 VBG VOFF/VPED DEC2V2 DEC2V7 EBCK EVWT VBLWT VBLOOM VRT VCM VREF2V7 OA IA OA OA DNC IA IA IA OA IA IA OA Internal bandgap reference voltage (1.22V nominal). Requires external 0.1uF capacitor. Pedestal DAC & offset comp. DAC bias. Connect to VBG or external reference. Decouple 2.2V reference. Requires external 0.1uF capacitor. Decouple 2.7V reference. Requires external 0.1uF capacitor. Do NOT connect - for test use only External black level bias. Internally generated. Decouple to VGND External white pixel threshold for exposure control. Decouple to VGND Defines white level for clamp circuitry. Requires external 0.1uF capacitor. Anti-blooming voltage reference. Requires external 0.1uF capacitor. Pixel reset voltage. Connect to VREF2V7 or external reference. Offset DAC common mode input. Connect to VREF2V7. Internally generated 2.7V reference. Requires external 4.7uF capacitor. ANALOGUE OUTPUTS 14 AVO OA Buffered Analogue video out. Can drive a doubly terminated 75ohm load. SYSTEM CLOCKS 25 26 CKOUT CKIN IMAGE CAPTURE TIMING SIGNALS 30 32 33 35 36 LST PV PVB CPE FST OD OD OD ID↓ OD 8 Pr el OD ID Oscillator output. Connect Crystal for standard timing. Oscillator input. Connect Crystal for standard timing. Line start. Active high pulse (start of active video lines). Pixel sample clock. Qualifies video output for external image capture. Pixel sample clock bar. Inverse of PV. Pixel sample clock enable. Default CPE = 0 i.e. PV/PVB disabled. Field start. Synchronises external image capture. im in ar y cd27033c.fm Pin List Pin 37 Name ODD Type OD Description Odd/even field signal. (ODD = 1 for odd fields, ODD = 0 for even) DIGITAL CONTROL SIGNALS 16 17 18 19 SAB1 SIN SCE LIN ID↓ ID↓ ID↓ ID↓ Higher bit of two least significant bits of device address on serial interface. Used to reset video timing control logic without resetting any other part of VV5430. Resets video logic on the falling edge of the SIN pulse. Scan mode enable - only relevant to test mode. Gamma corrected or Linear output. LIN = 0, gamma corrected output, LIN = 1, linear output. Default is gamma. LIN = 0 can be overridden via serial interface. Lower bit of two least significant bits of device address on serial interface. Automatic exposure control. AEC = 1, auto exposure is enabled; AEC = 0 auto exposure and auto gain control are disabled. AEC = 1 can be overridden via serial interface. Automatic gain control enable. AGC = 1, auto-gain is enabled (if AEC = 1); AGC = 0, auto-gain is disabled. AGC can be overridden via serial interface. Select default video mode for power-on. CCIR = 1 for CCIR video. EIA video mode is selected when CCIR = 0. Default is CCIR if unconnected Normal or Backlit exposure control mode. BKLIT = 0, normal mode. BKLIT = 1, backlit mode. Default is normal. BKLIT state can be overridden via serial interface. See Exposure Control for details. Active low camera reset. All camera systems are reset to power-on state. Scan chain input - only relevant to test mode. Serial bus clock (input only). Must be generated by comms. host. Serial bus data (bidirectional, open drain). 20 21 SAB0 AEC ID↓ ID↑ 22 AGC ID↑ 23 28 CCIR BKLIT ID↑ ID↓ 38 39 40 SCI SCL SDA Key: OA OD OD↓ BI Analogue output Digital output Digital output with internal pull-down Bidirectional IA ID ID↑ Analogue input Digital input Digital input with internal pull-up 09/04/97 Pr ID↓ ID↑ BI↑ 29 RESETB ID↑ el im in ar y 9 VISION V V 5430 Sensor VIDEO STANDARDS The VV5430 has 2 different video format modes, producing CCIR or EIA standard composite Monochrome video output. Line standards and frequencies are as follows: Video Mode CCIR EIA Format 4:3 4:3 Image (Pixels) 384 x 287 320 x 243 Crystal Frequency 14.7456 MHz 12.0000 MHz CCIR pin 1 0 VV5430 Video Modes Video signal Characteristics in 0.3 0.9 0.9 1.0 2.3 2.4 Symbol Parameter Min. ar y Typ. Max. Units V V V V V V The following table summarises the composite video output levels (AVO) for the two standards, which are graphically illustrated on the following pages: Notes VSync Vblank Vblack CCIR, EIA Sync. level CCIR, EIA Blanking level CCIR Black level EIA Black level Pr el CCIR Saturation level EIA Saturation level im DC reference level VSat Peak White; AVO clipped at this level Note: All measurements are made with AVO driving one 75Ω load. 10 cd27033c.fm Video Standards CCIR Timing Diagram line time reference point line period H = 64µs line sync. 4.7µs back porch 5.8µs rise times (10% - 90%) line 0.3 . µs { line blank 0.25±±001.05µs sync. front porch 1.5µs 2.3v peak white level 0.9v y field 0 2.5H black & blanking level sync. level im frame start field 1 2.5H 26H field 2 2.5H 25H el Pr field 1 2.5H 2.5H CCIR composite video signal - field level timing 09/04/97 in CCIR composite video signal - line level timing ar 2.5H 0.3v ≈ ≈ 11 VISION V V 5430 Sensor EIA Timing Diagrams line blank 0.3 . µs {line sync. 0.25±±001.05µs line time reference point line period H = 63.5µs line sync. 4.83µs back porch 4.00µs rise times (10% - 90%) front porch 1.33µs peak white level 2.4v ar y EIA composite video signal - line level timing field 0 1.0v black level 0.9v 0.3v blanking level sync. level Pr el field 1 3H ≈ 3H im 3H 3H frame start field 1 in 19H field 2 20H 3H ≈ 3H EIA composite video signal - field level timing 12 ≈ ≈ cd27033c.fm Control Signals for Image Digitisation CONTROL SIGNALS FOR IMAGE DIGITISATION The VV5430 camera can be used with an Analog-to-Digital Converter (ADC) and the necessary logic to form an image capture and processing system. The camera provides an analogue video output together with digital signals to qualify this output and synchronise image capture. The signals provided for image capture are the following:• PV,PVB: (Pixel Valid, PV Bar) Complementary signals, their leading edges qualify valid pixel levels. • LST: (Line STart) The rising edge signals the start of a visible line. • FST: (Field STart) The rising edge signals the start of a field. • ODD: Identifies an odd field within a frame. • CPE (Clock Pulse Enable): Disables generation of PV/PVB and LST signals. The state of this pin is sampled only during a system reset. Its state after reset can be overridden via the serial interface using Set-up Code_2. The following diagram illustrates the relative timing of the image capture signals. Scale is not actual but edge succession is preserved. ODD LST AVO PV PVB Pr Tfst Todd Tblank el Tlst Tpsu Tporch Tphd Tpv Tline Tfield 09/04/97 im Frame Capture signal timing FST in 13 ar y VISION V V 5430 Sensor Image Capture Control Signal Timing The time intervals given are correct for the recommended crystals: Name Crystal Frequency (FCKIN) Pixel clock period (T pck = 2/FCKIN) PV (Pixel clock) mark:space PV high period (T pv = Tpck/2) Even (first) field period (Tfield) Odd (second) field period (Tfield) FST duration (TFST) Line period (Tline) LST duration (TLST) First visible line delay (Tblank) CCIR 14.7456 MHz 135.63 nsec 1:1 67.82 nsec 20.032 msec (313 x Tline) 19.968 msec (312 x Tline) 7.73 µsec (57 x Tpck) EIA 12.0000 MHz 166.67nsec 1:1 83.34 nsec 16.7005 msec (263 x Tline) 16.637 msec (262 x Tline) 6.1 µsec (45 x Tpck) in im 30nsec 64.0 usec (472 x Tpck) 4.61 µsec (34 x Tpck) 704.949 µsec (11xTline + 7xTpck) 10.58 µsec (78 x Tpck) 52.083 µsec (384 x Tpck) 33.9 nsec Pr el First visible pixel delay (Tporch) Visible line period Max AVO to PV setup time (Tpsu) Min. PV to AVO hold time (Tphd) ODD to FST rise (TODD) ar y 63.5 µsec (381 x Tpck) 4.66 µsec (28 x Tpck) 762.833µsec (12xTline + Tpck) 8.833 µsec (53 x Tpck) 53.333 µsec (320 x Tpck) 41.7nsec 40nsec 11.500 msec (69 x Tpck) 21.700 msec (160 x Tpck) 14 cd27033c.fm Shuffle Modes SHUFFLE MODES The pixels in the VV5430 sensor array can be output to AVO as alternate columns and rows by setting bits 5 and 6 in the Setup Code_1 register (header code 0001 - see Serial Interface for details). This has the effect of generating two, or four, identical low resolution images in one field: Unshuffled Image Horizontal Shuffle Vertical Shuffle Hor. + Vert. Shuffle When this facility is combined with AVO Enable selected for the appropriate quarter, it is possible to display the images from four separate cameras on one monitor. In order to achieve four identical images in one frame (from one sensor), bits 5 and 6 of Setup Code_1 must both be set via the serial interface, that is HSHUFFLE=1 and VSHUFFLE=1. The former interleaves odd and even pixel lines in the image, and the latter interleaves pixel columns. OE[0..2] can then Enable AVO output for any one quarter of the display field. Quarter mode output Pixels Pr Sync By programming CE[0..2] different areas of the field can be enabled:. el Q2 Q4 The VV5430 video output can be Enabled in different parts of the standard field by programming bits 9..11 of Setup Code_2, that is CE[0..2]; when not enabled, the AVO output is Tristated, that is floating at high impedance. Thus, a number of different sensor AVO outputs can be connected together and selectively enabled. This feature, together with bus addressing of up to four VV5430s on one serial link, is intended for multi-sensor systems that, in conjunction with bits 5,6 of Setup Code_1, enable the images from up to four cameras to be displayed on a single monitor. Lines Q1 im in Sync + Blanking Image subdivided into 4 quarters : CCIR: 384 pixels x 287 lines: Q1,Q2 = 192 x 142 Q3, Q4 = 192 x 142 EIA: 320 pixels x 243 lines: Q1,Q2 = 160 x 120 Q3, Q4 = 160 x 120 Q3 The effect of OE[0..2] on AVO output is summarised in the following table: 09/04/97 ar y 15 VISION V V 5430 Sensor : OE[2] 0 0 0 0 1 1 1 1 OE[1] 0 0 1 1 0 0 1 1 OE[0] 0 1 0 1 0 1 0 1 Regions where AVO is enabled All (Normal operation) None (AVO permanently tristate) Sync only Sync plus Q1 image Q1 Q2 Q3 Q4 AVO Enable selection Since each of the horizontal ‘halves’ of the frame is only 142 lines (CCIR) or 120 lines (EIA), there is a ‘black band’ of three lines separating the top half from the bottom half. Similarly, for timing purposes, there is a two pixel vertical black band separating the left and right halves of the frame. (See the timing diagram below.) Multiplexing four cameras Using the quarter mode of operation, it is possible, therefore, to combine the outputs of four separate VV5430 cameras (with appropriate control logic) and display four half resolution images on one monitor: Pr el FST im SIN in Synchronisation SIN SIN SIN A A A A B B B B ar y C C AVO C C D D AVO D D AVO AVO Q1 Image + Sync. Composite Video Monitor Display A C B D Note: One VV5430 camera would normally be used as ‘master’, and provide the Sync-plus-Q1 output for the monitor or other video device. A synch. signal, at frame frequency, is required via SIN (pin 17) to keep the four cameras in step. This signal can be derived from the master camera FST output (with ‘SNO Enable’ set via Setup Code_3 bit 6), or be generated externally. 16 cd27033c.fm Shuffle Modes Quarter mode line timing. Standard Line Left Quarter Right Quarter t1 t4 t2 t3 ar CCIR Time (us) 0.1356 25.4928 0.2713 25.4928 0.1356 52.0704 EIA 142 142 y EIA pck cycles 1 158 2 158 1 320 Time (us) 0.1667 26.0052 0.3333 26.0052 0.1667 53.3440 #t pck cycles t1 Pixel timings for AVO 1/4 Mode: Description Left quarter Line Delay Duration of left quarter line Inter-quarter Interval Duration of right quarter line Right quarter border im t2 t3 t4 CCIR Duration of standard SI el In addition there are line level signals to identify the top and bottom half of the active video area of the field: . Description Start line Number of lines CCIR EIA 120 120 Top half of field Bottom half of field Pr First active line Active line 145 There is a ‘black band’ of three video lines between the valid lines in the top half of the field and the valid lines in the bottom half of the field. This ensures that both halves of the field are the same size and provides a horizontal frame line. The line level timing described above also provides a two pixel vertical black line, hence the four quarters appear to be ‘framed’ in the display. 09/04/97 in 1 190 2 190 1 384 First active line Active line 124 17 VISION V V 5430 Sensor EXPOSURE CONTROL Automatic exposure and gain control ensure operation of the VV5430 over a wide range of lighting conditions. Automatic black level control and optional ‘Backlit’ mode further ensure consistent picture quality. The VV5430 controls exposure over a range of 99,000:1 in EIA mode and 146,000:1 in CCIR mode, and operates at illumination levels as low as 0.5 lux. Note: The System Clock can be divided by up to eight times to further increase sensitivity by extending the exposure time. This, of course, also reduces the frame rate to non-standard values. Automatic exposure and gain control are enabled with AEC=1 (pin 21) and AGC=1 (pin22), but can be inhibited via the serial interface (Setup Code_1). However, If AEC is inhibited by pin 21, AGC is also inhibited and the serial interface has no control. Inhibiting AEC or AGC via the serial interface, or by taking pin 21 or 22 low, freezes the current value(s) for these, which can then be altered by writing to the exposure and gain control registers. (See Serial Interface for details.) Note: The timing of exposure and gain control is other than correctly exposed, a new value for integration time is calculated and applied for the next frame. Corrections are either ±1/8 or ±1/64, depending upon the degree of over or under exposure. If the exposure value is close to its limit (12% below max. or 25% above min.), then gain is increased or decreased by one step and exposure is set to midway in its range. Exposure is then controlled as normal. Automatic Gain Control (AGC) The VV5430 automatically increases the system gain of its output stage if with the current gain setting and maximum exposure the image is too dark. Gain can be varied from x1 to x16 in times-two steps, giving five different gain settings. If the scene is too dark and the integration period has almost reached its maximum value, the gain value is incremented by one step (times two). In the same frame period the exposure value is divided by two, halving the integration period. The exposure controller then increases the exposure value as necessary. Similarly if the image is too bright and the integration period is short then gain will be reduced by one step (divide by two) and the exposure value will be doubled. The exposure controller can then adjust the exposure value as necessary to provide a correctly exposed image. Increasing gain is limited to a programmable upper limit, for which the default value is x8. The gain upper limit is programmed by setting bits [0..3] with header code 0101, when AGC=1. If Automatic Gain Control is inhibited (AGC=0), these registers are used instead to select a gain setting up to x16. Automatic Exposure Control (AEC) Automatic exposure control is achieved by varying pixel current integration time according to the average light level on the sensor. This integration time can vary from one pixel clock period to one frame period. Pixels above a threshold white level are counted every frame, and the number at the end of the frame defines the image as overexposed, above average, correctly exposed, below average or underexposed. If the image 18 Pr el messages on the serial interface is very important. External values for exposure and gain are only applied at the start of a frame, and the serial interface must be paused until the new values are installed—no further communications will be accepted during this time. im in ar y 09/04/97 Exposure Control Backlit Mode The VV5430 can be configured to operate in two auto-exposure modes, selected by the BKLIT pin (pin28) state, or via the serial interface (Setup Code_1, bit 0). The default mode (BKLIT = 0) provides exposure control for normally illuminated scenes. For scenes where a bright background can cause the foreground subject to be severely under exposed, the ‘Backlit’ mode (BKLIT = 1) offers superior performance. ‘Backlit Mode’ (BKLIT=1) operates by using a higher threshold level for the exposure control comparator over the central area of an image, which is therefore exposed for longer and so enhanced. The area in which the higher comparator threshold is used when BKLIT=1 is illustrated below: Normal operation (BKLIT=0) 10% Higher threshold area (BKLIT=1) y ar 25% 25% 75% 30% 80% in Exposure control area 80% 90% Visible image im Higher Threshold Note: The threshold level used for the central area is a preset mutiple of the normal mode reference level, and is not alterable. 09/04/97 Pr el 19 VISION V V 5430 Sensor SERIAL COMMUNICATION The VV5430 includes a full duplex (two-wire) serial interface, and can be controlled and configured by a host processor. The base bus address for the VV5430 is 20H, but the two least significant bits of the address (SAB0, SAB1) can be selected by hard-wiring pins 20 and 16. This allows up to four separate camera devices to be controlled on one serial link, which, for example, makes multiplexing of camera outputs possible. The serial interface reads or writes data to a set of Registers that define the characterisation of the sensor, and control certain operations. Serial Communication Protocol The host must perform the role of a communications master and the camera acts as either a slave receiver or transmitters communication between host and camera takes the form of three or five byte messages of 8-bit data, with a maximum serial clock (SCL) frequency of 100kHz. Since the serial clock is generated by the host, the host determines the data transfer rate. The host processor initiates a message by forcing both Serial Data (SDA) and Serial Clock (SCL) low. The first byte addresses the required device, and defines either a READ message (four bytes to follow) or a WRITE message (two bytes to follow). After the camera has acknowledged a valid address (ACK, bit 9 of SCL), the host then either reads four bytes of data from the camera or transmits a further two bytes to the camera. The data transfer protocol on the bus is illustrated below: Start condition SDA MSB im Read/Write bit 2 7 8 9 Pr el 1 in 1 ACK SCL ar y 2 3-8 Acknowledge from receiver S 9 ACK P Stop condition Data Transfer Protocol 20 cd27033c.fm Serial Communication stop start start stop SDA ... Tbuf Tlo Tr Tf Thd;sta SCL Thd;sta Thd;dat Thi ... Tsu;dat Tsu;sta Tsu;sto Note: All values referred to the minimum input level (high) = 3.5V, and maximum input level (low) = 1.5V ar 0 Parameter SCL clock frequency Bus free time between a stop and a start Hold time for a repeated start LOW period of SCL HIGH period of SCL Set-up time for a repeated start Data hold time Symbol Fscl Tbuf Thd;sta Tlo Min. y Max. 100 1000 300 100 Unit kHz µs µs µs µs µs µs ns ns ns µs pF im Thi Tsu;sta Thd;dat Tsu;dat Tr Tf Tsu;sto Cb el Data Set-up time Pr Rise time of SCL, SDA Fall time of SCL, SDA Set-up time for a stop Capacitive load of each bus line (SCL, SDA) 1. The VV5430 internally provides a hold time of at least 300ns for the SDA signal (referred to the minimum input level (high) of the SCL signal) to bridge the undefined region of the falling edge of SCL Serial Interface Timing Characteristics 09/04/97 in 4.0 4.7 4.0 4.7 01 250 4.0 - 4.7 21 VISION V V 5430 Sensor READ DATA FROM CAMERA Information describing the current configuration and the current exposure values can be read from the camera. The data is formed into four bytes of 8 bits. Each pair of bytes is considered to be a data word and is read out msb first. Read = 1 Camera acknowledge (valid address) Master acknowledge R S ADDRESS[7:1] /W A DATA[31:24] A DATA[23:16] A 001 0 0 x x 1 Master acknowledge DATA[15:8] A DATA[7:0] AP Read Data Format 31 - 23 22 - 14 13 - 10 9 8 7 6 5 4 3-0 Pr el Fine Exposure Value (9 bits) Gain Value (4 bits) Auto Exposure Control on/off Auto Gain Control on/off Bit Function im Primary Read Data: in 17 The following tables defines the information contained in the read messages. By default, the Primary Read Data is accessed; only if a Secondary Read Select bit is set in Setup Code_2 (header code 0010) is the Secondary information read. ar y Bit 31 - 18 16 - 0 Secondary Read Data: Function Undefined Black Level monitor in progress White Pixel count (17 bits) Coarse Exposure Value (9 bits) Internal Black Calibration on/off Gamma or Linear Video Output Normal or Backlit mode1 Undefined Camera Type ID Code (4 bits) 1. Bit 5 of the Primary Read message only reflects the state of the BKLIT pin, not the combined result of the pin and the serial interface BKLIT control bit. 22 cd27033c.fm Write to Camera WRITE TO CAMERA Information to be communicated from host to camera consists of configuration data (for example automatic gain control ON), and parametric information (for example sensor integration time). The write data is formed into two bytes. A 4-bit Header Code in the first byte is used by the camera to determine the destination of the 12-bit message following the header. Write = 0 S ADDRESS[7:1] R/ W Camera acknowledge A HEADER DATA[11:8] A DATA[7:0] AP 00100xx0 Camera acknowledge (valid address) Receive Data Format The valid Header Codes and their data structures are fully described in the following pages. When an exposure or gain value has been written to the camera it is held in the interface until the camera is ready to consume the new data. For correct operation, there should be no further read or write accesses to the camera during this hold period. Normal communication between other modules connected to the serial interface will not cause problems. The minimum length of the wait period is 40ms in EIA mode and 34ms in CCIR mode from the end of the data transfer. 09/04/97 Pr el Timing Protocol im in After the camera acknowledges the receipt of a valid address the host transfers the first data byte which the camera acknowledges by pulling SDA low. The second byte is then sent followed by a final acknowledge from the camera. A stop condition is produced by the host after the second message byte. As with the read procedure, the stop condition is not absolutely necessary as the camera’s serial interface will reset automatically after two bytes have been received. ar y 23 VISION V V 5430 Sensor Header Codes The message can be a configuration word, an exposure, gain or calibration value. The camera’s interpretation of the header code and the set-up code message are given in the table below. Defaults for each control bit are built in to the camera’s reset cycle, and may be changed on-thefly under host control. Code Interpretation Comment 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Invalid Set-up code_1 (9 bits) Set-up code_2 (9 bits) Coarse exposure value (9 bits) Fine exposure value (9 bits) Gain control value (4 bits) Unused Unused Basic funtionality options Pixel control & Read Data Set AEC=0 to enable Set AEC=0 to enable Set AGC=0 to enable Exposure control T1 threshold (9 bit) Exposure control T2 threshold (9 bit) Analogue control register (8 bit) Reserved Reserved Reserved im in Not applicable to normal use Not applicable to normal use Not applicable to normal use Pixel synchronisation Not applicable to normal use cd27033c.fm Pr el Test mode select Set-up code_3 (6 bits) Header Codes Message content The following Tables contain details of the data associated with each header code, and the number of valid data bits in each of the registers. In all cases the full 12 bit message tail can be sent, the valid bits being packed to the lsb. (Normally, the unused bits would be assigned zeroes.) 24 ar y Write to Camera Setup Code_1 Header Code = 0001 Valid data bits: 11 The code_1 setup register is used to select different basic operating modes: Bit 0 Function Normal/Backlit Default 0 Comment Selects between normal and backlit exposure modes. The power-on default is normal mode. See Exposure Control for full description Selects between a linear (LIN=1) or gamma corrected video signal on AVO. The power-on default is gamma corrected. Allows automatic gain control to be inhibited. The current gain value selected is frozen. With AGC=0 a new gain value can be written to the gain register via the serial interface (header code 0101). Allows automatic black calibration to be inhibited. Allows automatic exposure control to be inhibited. The current exposure value selected is frozen. Note that if automatic exposure control is inhibited then automatic gain control is also disabled. With AEC=0 a new exposure value can be selected by writing to the coarse and fine exposure registers via the serial interface (header codes 0011 & 0100). Shuffles the read out of the horizontal shift register. Even columns read out together then odd columns. Shuffles the readout of the vertical shift register. Even lines read out together then odd lines. Requests a re-calibration of the black level while bit is low. System clock division: (see Note) 0,0=1; 0,1=÷2; 1,0=÷4; 1,1=÷8 This bit must be set(=1) for correct sensor operation 1 Linear Correction enable 0 2 Auto gain control enable 1 3 4 Inhibit black calibration Auto exposure control enable 0 1 5 6 7 8 9 10 11 Horizontal shuffle enable Vertical shuffle enable Clock divisor DIV0 Internal Register Not used Pr Force black calibration Clock divisor DIV1 el Note: Decreasing the system clock rate proportionately increases sensor sensitivity (by increasing exposure time), but also decreases frame frequency. System Clock must be x1 for standard CCIR or EIA framing. 09/04/97 im 0 0 1 0 0 1 0 Set-up code_1 in ar y 25 VISION V V 5430 Sensor Setup Code_2 Header Code = 0010 Valid data bits: 12 The code_2 setup register is used to select read data, valid pixels and video output operating modes: Bit 0 1 2 3 4 5 6 7 8 9 10 11 Function Shadow read mode (A) enable Shadow read mode (B) enable Pixel sample clock select (SEL0) Pixel sample clock select (SEL1) Not used Enable free running pixel clock Enable external pixel thresholds Not used Not used OE[0] OE[1] OE[2] Default 0 0 CPE Pixel sample clock mode (PV/PVB). See below. 0 0 0 0 0 0 0 MUST be set to 0 Comment Select shadow read mode A or B. Note: bits 0,1 are mutually exclusive. Use external algorithm thresholds in exposure controller MUST be set to 0 MUST be set to 0 The table below shows the function of SEL0 and SEL1 (Bit 2 and Bit 3); the default value of SEL0 is set by the CPE pin level: Bit 3 0 0 1 1 Bit 2 0 1 0 1 Pixel Clock (PV/PVB pins) function 26 Pr el Disable pixel clock output Qualify full image area (as defined for CCIR or EIA) Qualify central 256 x 256 pixels (CCIR only) PV/PVB active only during interline periods of visible image lines. Note. This mode is required for digitisation of standard video output. im 0 0 Setup Code_2 in AVO output enable control bits [0..2]. See Shuffle Modes above for explanation. ar y Overrides SEL0 & SEL1. cd27033c.fm Write to Camera Coarse and Fine Exposure Values. Header Code (coarse) = 0011 Header Code (fine) = 0100 Valid data bits: 9 Valid data bits: 9 The 18 bit exposure control value is formed from two 9-bit values, coarse (9 msb’s) and fine (9 lsb’s). For external exposure control (AEC = 0) the exposure value can be set via the serial interface (header codes 0011 and 0100). Values written that exceed the mode dependant maxima will be ignored and the maximum will be used. Bit 0-8 0-8 9-11 Function Coarse exposure value Fine exposure value Unused CCIR min max 0 0 310 404 min 0 0 EIA max 260 325 Comments Header code 0011 Header code 0100 Exposure Values Header Code (T1) = 1000 Header Code (T2) = 1001 el DAC The lower and upper pixel count thresholds are used by the automatic exposure controller. The power-on default values for T1 and T2 are exposure mode and video mode dependant. If the external pixel threshold control bit (bit 6 in Setup Code_2 register) is set the internal default values for T1 and T2 are overridden by the serial interface values. Note that only the most significant nine bits of each seventeen bit threshold can be controlled. Bit 0-8 0-8 9 - 11 Pr Unused im Exposure Control Thresholds T1 and T2 in Valid data bits: 9 Valid data bits: 9 Comments Header Code 1000 Header Code 1001 27 Lower Exposure control threshold (T1) Upper Exposure control threshold (T2) Pixel Count Thresholds (T1,T2) 09/04/97 ar y VISION V V 5430 Sensor Gain and Gain Ceiling Header Code = 0101 Valid data bits: 4 This register is used to select an external gain value when automatic gain control is inhibited (AGC = 0) and to set the gain ceiling while automatic gain control is active (AGC = 1). Bit 0 1 2 3 4-11 Function Gain value G[0] Gain value G[1] Gain value G[2] Gain Value G[3] Unused Default 0 0 0 0 Default gain ceiling Default gain value Comment The table below shows the valid gain codes. G[3] 0 0 0 0 1 G[2] 0 0 0 1 1 G[1] 0 0 1 1 1 G[0] 0 1 1 1 1 Gain 1 2 4 8 in Gain Values Default gain value 28 Pr el 16 im Default gain ceiling ar y Comment cd27033c.fm Gain Register Write to Camera Analogue Control Register Header Code = 1010 Valid data bits: 10 A number of parameters that are used to define internal operations can be altered by the serial interface: Bit 0 1 2 3 4 5 6 7 8 9 Internal Internal Internal Function Default 1 0 0 0 Comments Must be set(=1) for normal op. Must be 0 for normal op. Must be 0 for normal op. Disable anti-blooming protection Internal Internal Enable external black reference Enable external white threshold Internal Enable binarisation of AVO output in Control Register im 09/04/97 Pr Note: The Threshold Level above which a pixel is deemed to be WHITE is set via the serial interface, Header Codes 1001 and 1000 (Upper and Lower Exposure Control Thresholds). el ar 0 0 0 0 0 y 0 Must be 0 for normal op. Must be 0 for normal op. Must be 0 for normal op. AVO output level is either VBLACK or VWHITE for each pixel (see Note)l 29 VISION V V 5430 Sensor Setup Code_3 Header Code = 1110 Valid data bits: 7 This register stores data used during sensor synchronisation and when the pixel counter in the video timing logic is reset, either at the end of a video line or when the sensor is forced to synchronise externally. Bit 5:0 Function Video timing pixel counter offset Default 3 Comment Variable offset that is added to the fixed pixel counter preset value when the counter is reset, at the end of a video line or when an external synchronisation is applied Synchronising signal to other cameras in multi-camera applications (see Note) 6 11:7 Enable SNO Not used 0 0 Set-Up Code_3 30 Pr el im cd27033c.fm in Note: Enable SNO adjusts the timing of the FST signal (output on pin 36) to correctly synchronise external slave cameras. Alternatively, the synchronising signal for all cameras can be generated externally, which may be more useful in image processing applications. ar y Example Support Circuit EXAMPLE SUPPORT CIRCUIT AVD VDD 8 REG1 2, 3, 6, 7 1 C2 +7 to +12v dc C1 R1 C5 C3 C6 0v C4 C7 27 34 41 1 7 13 14 15 38 30 18 23 36 33 32 37 11 12 8 9 43 6 5 C19 C18 R4 MONITOR VDD1 VDD2 DVDD 24 31 VSS1 VSS2 DVSS AVSS AGND SAB1 SAB0 AVCC AVDD VVDD AVO Component IC1 REG1 C1,C2 C3 C4 - C9,C13, C15 - C19 C10 C11, C12 C14 R1 R2 R3 R4 R5 X1 Value VV5430 LM78L05 0.22 µF 68 µF (6V Tant.) 0.1 µF 4.7µF 10 pF 100pF 5R6 10R 10M 75R 33R 42 10 48 16 VDD 20 IC1 ar VV5430 SIN 17 CKIN 26 R3 C11 CKOUT 25 R2 (48 pin LCC) in 28 19 22 21 BKLIT LIN AGC AEC VBLOOM VRT VCM 44 C8 45 46 R5 C9 47 C10 39 40 VREF2V7 SCL SCL SDA SDA RESETB CPE 35 29 VDD y C12 VGND SCI LST SCE CCIR FST PVB PV ODD im el AMP2 AMP1 EBCK EVWT VBLTW Pr Crystal CCIR:14.7456 MHz EIA:12.0000 MHz C17 DNC DEC2V7 C16 C15 Use Surface Mount components throughout. DEC2V2 4 VOFF/VPED 3 VBG 2 C13 C14 X1 1. Keep nodes Supply and Ground pins low impedance and independent 2. Video output should be referred to VGND. 3. Keep circuit components close to chip pins (especially de-coupling capacitors) 09/04/97 31 VISION V V 5430 Sensor VLSI VISION LIMITED UK Office Aviation House, 31 PInkhill, Edinburgh, UK EH12 7BF Tel: +44 (0)131 539 7111 Fax: +44 (0)131 539 7140 Email: info@vvl.co.uk USA West Office 18805 Cox Avenue, Suite 260, Saratoga, California 95070, USA Tel: +1 408 374 5323 Fax: +1 408 374 4722 Email: info@vvl.co.uk USA East Office 2517 Highway 35 Bldg F, Suite 202 Manasquan New Jersey 08736 Tel: +1 908 528 2222 Fax: +1 908 528 9305 Email: info@vvl.co.uk 32 Pr el VLSI Vision agent or distributor im VLSI Vision Ltd. reserves the right to make changes to its products and specifications at any time. Information furnished by VISION is believed to be accurate, but no responsibility is assumed by VISION for the use of said information, nor any infringements of patents or of any other third party rights which may result from said use. No license is granted by implication or otherwise under any patent or patent rights of any VISION group company. © Copyright 1996, VLSI VISION in ar y cd27033c.fm