WCMA4016U1X

Y62147BV L™ Preliminary WCMA4016U1X 256K x 16 Static RAM Features • Low voltage range: 2.7V–3.6V • Ultra-low active, standby power • Easy memory expansion with CE1 and CE2 and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected • CMOS for optimum speed/power both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this datasheet for a complete description of read and write modes. Functional Description[1] The WCMA4016U1X is a high-performance CMOS static RAM organized as 262,144 words by 16 bits. This device features advanced circuit design to provide ultra-low active current and standby current. This is ideal for providing more battery life in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or Logic Block Diagram 1 BLE DATA IN DRIVERS A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O8 ROW DECODER I/O9 VSS I/O0 – I/O7 I/O8 – I/O15 VCC Pin Configurations FBGA (Top View) 2 OE BHE I/O10 I/O11 I/O12 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H 256K × 16 RAM Array 2048 × 2048 SENSE AMPS I/O14 I/O13 I/O15 COLUMN DECODER NC BHE WE A10 A11 A12 A13 A14 A15 A16 A17 OE BLE BHE BLE NC A8 CE2 CE1 Pow er Down Circuit CE2 CE1 . Weida Semiconductor, Inc. WCMA4016U1X Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V DC Input Voltage[1] .................................... −0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2100V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Device WCMA4016U1X Range Industrial Ambient Temperature –40°C to +85°C VCC 2.7V to 3.6V Product Portfolio Power Dissipation (Industrial) VCC Range Product WCMA4016U1X VCC(min.) VCC(typ.) 2.7V 3.0V [2] VCC(max.) 3.6V Power LL Speed (ns) 70 Operating (ICC) Typ.[2] 7 mA Maximum 15 mA Standby (ISB2) Typ.[2] 2 µA Maximum 20 µA Electrical Characteristics Over the Operating Range WCMA4016U1X Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled IOUT = 0 mA, f = fMAX = 1/tRC, CMOS Levels VCC = 3.6V Test Conditions IOH = –1.0 mA IOL = 2.1 mA VCC = 2.7V VCC = 2.7V VCC = 3.6V VCC = 2.7V 2.2 –0.5 –1 –1 ±1 +1 7 Min. 2.4 0.4 VCC + 0.5V 0.8 +1 +1 15 Typ.[2] Max. Unit V V V V µA µA mA IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 Automatic CE Power-Down Current— CMOS Inputs CE1 > VCC−0.3V, CE2< 0.3V VIN>VCC–0.3V, VIN VCC – 0.3V or CE2 < 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = 0, VCC = 3.60V LL 1 2 2 20 mA µA ISB2 Automatic CE Power-Down Current— CMOS Inputs LL 2 20 µA Notes: 1. VIL(min.) = –2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 2 WCMA4016U1X . Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ.) Max. 6 8 Unit pF pF Thermal Resistance Description Thermal Resistance (Junction to Ambient)[3] Thermal Resistance (Junction to Case)[3] Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Symbol ΘJA ΘJC BGA 55 16 Units °C/W °C/W AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 R1 VCC Typ 10% GND Rise TIme: 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time: 1 V/ns (a) (b) (c) Equivalent to: THÉVENIN EQUIVALENT RTH VTH OUTPUT Parameters R1 R2 RTH VTH 3.0V 1103 1554 645 1.75V Unit Ω Ω Ω V Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC= 1.0V CE1 > VCC – 0.3V, CE2 < 0.2V, VIN > VCC – 0.3V or VIN < 0.3V L LL 0 70 ns ns Conditions Min. 1.0 1 Typ.[2] Max. 3.6 10 Unit V µA tCDR[3] tR[4] Chip Deselect to Data Retention Time Operation Recovery Time Note: 3. Tested initially and after any design or process changes that may affect these parameters. 4. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 µs or stable at VCC(min.) >10 µs. 3 WCMA4016U1X Data Retention Waveform[5] DATA RETENTION MODE VCC CE1 or BHE.BLE or CE2 VCC, min. tCDR VDR > 1.0 V VCC, min. tR Switching Characteristics Over the Operating Range[6] 70 ns Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE[8] tHZBE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE [10, 11] Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[7, 9] OE HIGH to High Z[9] Z[7] Z[7, 9] CE1 LOW and CE2 HIGH to Low CE1 HIGH and CE2 LOW to High Min. 70 Max. Unit ns 70 10 70 35 5 25 10 25 0 70 70 5 25 70 60 60 0 0 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE1 LOW and CE2 HIGH to Power-Up CE1 HIGH and CE2 LOW to Power-Down BHE / BLE LOW to Data Valid BHE / BLE LOW to Low Z BHE / BLE HIGH to High Z Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Notes: 5. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. If both byte enables are toggled together this value is 10ns 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 4 WCMA4016U1X Switching Characteristics Over the Operating Range[6] (continued) 70 ns Parameter tBW tSD tHD tHZWE tLZWE Description BHE / BLE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z [7, 9] [7] Min. 60 30 0 Max. Unit ns ns ns 25 10 ns ns Switching Waveforms Read Cycle 1 (Address Transition Controlled)[12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle 2 (OE Controlled) [13, 14] ADDRESS tRC CE1 tPD tHZCE tACE CE2 BHE/BLE tDBE tLZBE OE tHZBE DATA OUT VCC SUPPLY CURRENT tDOE tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE HIGH IMPEDANCE ICC ISB DATA VALID 50% Notes: 12. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. 5 WCMA4016U1X Switching Waveforms (continued) Write Cycle 1 (WE Controlled) [10, 15, 16, 17] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tHA tPWE BHE/BLE tBW OE tSD DATA I/O See Note 17 tHD VALID DATA tHZOE Write Cycle 2 (CE1 or CE2 Controlled) [10, 15, 16, 17] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE WE tBW tHA BHE/BLE OE tSD DATA I/O See Note 17 tHD VALID DATA tHZOE Notes: 15. Data I/O is high impedance if OE = VIH. 16. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. 6 WCMA4016U1X Typical DC and AC Characteristics Normalized Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage 45 MoBL 40 35 ISB (µA) 30 20 15 10 5 2.2 2.7 3.2 SUPPLY VOLTAGE (V) 3.7 2.0 3.7 2.8 2.4 2.7 SUPPLY VOLTAGE (V) 1.4 1.2 MoBL 1.0 ICC 0.8 0.6 0.4 0.2 0.0 1.7 Access Time vs. Supply Voltage 80 70 60 50 TAA (ns) 40 30 20 10 2.0 2.4 2.8 3.7 MoBL 2.7 SUPPLY VOLTAGE (V) Truth Table CE1 H X X L L L L L L L L CE2 X L X H H H H H H H H WE X X X H H H H H H L L OE X X X L L L H H H X X BHE X X H L H L L H L L H BLE X X H L L H H L L L L Inputs/Outputs High Z High Z High Z Data Out (I/O0 – I/O15) Data Out (I/O0 – I/O7); High Z (I/O8 – I/O15) High Z (I/O0 – I/O7); Data Out (I/O8 – I/O15) High Z High Z High Z Data In (I/O0 – I/O15) Data In (I/O0 – I/O7); High Z (I/O8 – I/O15) Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) 7 WCMA4016U1X Ordering Information Speed (ns) 70 Ordering Code WCMA4016U1X-FF70 Package Name BA48 Package Type 48-Ball Fine Pitch BGA Operating Range Industrial Package Diagrams 48-Ball (7.00 mm x 8.5 mm x 1.2 mm) FBGA BA48B 51-85106-*D 8 WCMA4016U1X Document History Page Document Title: WCMA4016U1X 256K x 16 STATIC RAM Document Number: REV. ** ECN NO. Issue Date See ECN Orig. of Change AJU New Data Sheet Description of Change 9