WM8734

w Stereo Audio CODEC DESCRIPTION The WM8734 is a low power stereo CODEC ideal for MD, CD-RW machines and DAT recording applications. Stereo line inputs are provided, along with a mute function and programmable line level volume control. Stereo 24-bit multi-bit sigma delta ADCs and DACs are used with oversampling digital interpolation and decimation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 96kHz are supported. Stereo audio line level outputs are provided along with antithump mute and power up/down circuitry. The device is controlled via a 2 or 3 wire serial interface. The interface provides access to all features including level controls, mutes, de-emphasis and power management facilities. The device is available in 20-pin SSOP or 5x5mm QFN packages. • • • • • • WM8734 FEATURES • Audio Performance − 90dB SNR (‘A’ weighted @ 48kHz) ADC − 100dB SNR (‘A’ weighted @ 48kHz) DAC − 2.7 – 3.6V Digital Supply Operation − 2.7 – 3.6V Analogue Supply Operation ADC and DAC Sampling Frequency: 8kHz – 96kHz Selectable ADC High Pass Filter 2 or 3-Wire MPU Serial Control Interface Programmable Audio Data Interface Modes − I2S, Left, Right Justified or DSP − 16/20/24/32 bit Word Lengths − Master or Slave Clocking Mode Stereo Audio Inputs and Outputs 20-Pin SSOP or 5x5mm QFN Package Options APPLICATIONS • • CD and Minidisc Recorder MP3 Player / Recorder BLOCK DIAGRAM CSB SDIN MODE SCLK AVDD CONTROL INTERFACE VMID AGND W WM8734 RLINEIN VOL ADC DAC MUTE ROUT +12 to -34.5dB, 1.5dB Steps DIGITAL FILTERS LLINEIN VOL ADC DAC MUTE LOUT +12 to -34.5dB, 1.5dB Steps CLKIN DIVIDER (Div x1, x2) DIGTAL AUDIO INTERFACE MCLK DBVDD DACDAT DACLRC ADCLRC WOLFSON MICROELECTRONICS LTD www.wolfsonmicro.com ADCDAT DCVDD Advanced Information, November 2001, Rev 2.2 Copyright 2001 Wolfson Microelectronics Ltd. DGND BCLK WM8734 PIN CONFIGURATION – SSOP DGND DBVDD BCLK DACDAT DACLRC ADCDAT ADCLRC LOUT ROUT AVDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DCVDD MCLK SCLK SDIN CSB MODE LLINEIN RLINEIN VMID AGND Advanced Information ORDERING INFORMATION - SSOP DEVICE XWM8734EDS TEMP. RANGE -10 to +70oC PACKAGE 20-pin SSOP PIN DESCRIPTION - SSOP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Note: 1. Pull Up/Down only present when Control Register Interface ACTIVE = 0 to conserve power. NAME DGND DBVDD BCLK DACDAT DACLRC ADCDAT ADCLRC LOUT ROUT AVDD AGND VMID RLINEIN LLINEIN MODE CSB SDIN SCLK MCLK DCVDD TYPE Ground Supply Digital Input/Output Digital Input Digital Input/Output Digital Output Digital Input/Output Analogue Output Analogue Output Supply Ground Analogue Output Analogue Input Analogue Input Digital Input Digital Input Digital Input/Output Digital Input Digital Input Supply DESCRIPTION Digital GND Digital Buffers VDD Digital Audio Bit Clock, Pull Down, (see Note 1) DAC Digital Audio Data Input DAC Sample Rate Left/Right Clock. Pull Down (see Note 1) ADC Digital Audio Data Output ADC Sample Rate Left/Right Clock, Pull Down (see Note 1) Left Channel Line Output Right Channel Line Output Analogue VDD Analogue GND Mid-rail reference decoupling point Right Channel Line Input (AC coupled) Left Channel Line Input (AC coupled) Control Interface Selection, Pull Up (see Note 1) 3-Wire MPU Chip Select / 2-Wire MPU interface address selection, active low, Pull up (see Note 1) 3-Wire MPU Data Input / 2-Wire MPU Data Input 3-Wire MPU Clock Input / 2-Wire MPU Clock Input Master Clock Input (MCLK) Digital Core VDD w AI Rev 2.2 November 2001 2 WM8734 PIN CONFIGURATION – QFN AGND ROUT AVDD LOUT VMID NC NC Advanced Information ORDERING INFORMATION - QFN DEVICE XWM8734EFL TEMP. RANGE -10 to +70oC PACKAGE 28-pin QFN (5x5x0.9mm) 21 20 19 18 17 NC 22 RLINEIN 23 LLINEIN 24 MODE 25 CSB 26 SDIN 27 SCLK 28 1 MCLK 16 15 14 NC 13 NC 12 NC 11 ADCLRC 10 ADCDAT 9 DACLRC 8 DACDAT 2 NC 3 DCVDD 4 DGND 5 DBVDD 6 NC 7 BCLK PIN DESCRIPTION - QFN PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME MCLK NC DCVDD DGND DBVDD NC BCLK DACDAT DACLRC ADCDAT ADCLRC NC NC NC NC LOUT ROUT AVDD AGND VMID NC NC RLINEIN LLINEIN MODE CSB SDIN SCLK TYPE Digital Input Do Not Connect Supply Ground Supply Do Not Connect Digital Input/Output Digital Input Digital Input/Output Digital Output Digital Input/Output Do Not Connect Do Not Connect Do Not Connect Do Not Connect Analogue Output Analogue Output Supply Ground Analogue Output Do Not Connect Do Not Connect Analogue Input Analogue Input Digital Input Digital Input Digital Input/Output Digital Input DESCRIPTION Master Clock Input (MCLK) Test Pin, must be left unconnected Digital Core VDD Digital GND Digital Buffers VDD Test Pin, must be left unconnected Digital Audio Bit Clock, Pull Down, (see Note 1) DAC Digital Audio Data Input DAC Sample Rate Left/Right Clock. Pull Down (see Note 1) ADC Digital Audio Data Output ADC Sample Rate Left/Right Clock, Pull Down (see Note 1) Test Pin, must be left unconnected Test Pin, must be left unconnected Test Pin, must be left unconnected Test Pin, must be left unconnected Left Channel Line Output Right Channel Line Output Analogue VDD Analogue GND Mid-rail reference decoupling point Test Pin, must be left unconnected Test Pin, must be left unconnected Right Channel Line Input (AC coupled) Left Channel Line Input (AC coupled) Control Interface Selection, Pull Up (see Note 1) 3-Wire MPU Chip Select / 2-Wire MPU interface address selection, active low, Pull up (see Note 1) 3-Wire MPU Data Input / 2-Wire MPU Data Input 3-Wire MPU Clock Input / 2-Wire MPU Clock Input w AI Rev 2.2 November 2001 3 WM8734 ABSOLUTE MAXIMUM RATINGS Advanced Information Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency (see Note 4) Operating temperature range, TA Storage temperature prior to soldering Storage temperature after soldering Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) Notes: 1. 2. 3. 4. Analogue and digital grounds must always be within 0.3V of each other. MIN -0.3V -0.3V DGND -0.3V AGND -0.3V -10°C -65°C MAX +3.63V +3.63V DVDD +0.3V AVDD +0.3V 40MHz +70°C +150°C +240°C +183°C 30°C max / 85% RH max The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD) or digital supply buffer voltage (DBVDD). The digital supply buffer voltage (DBVDD) must always be less than or equal to the analogue supply voltage (AVDD). When CLKIDIV2=1. RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supply range Ground Total analogue supply current Digital supply current Standby Current Consumption SYMBOL DCVDD DBVDD AVDD DGND, AGND IAVDD IDCVDD, IDBVDD DCVDD, DBVDD, AVDD = 3.3V DCVDD, DBVDD AVDD = 3.3V TEST CONDITIONS MIN 2.7 2.7 2.7 TYP 3.3 3.3 3.3 0 16 8 5 MAX 3.6 3.6 3.6 UNIT V V V V mA mA uA w AI Rev 2.2 November 2001 4 WM8734 ELECTRICAL CHARACTERISTICS Advanced Information Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Input LOW level Input HIGH level Output LOW Output HIGH Power On Reset Threshold (DCVDD) DCVDD Threshold On -> Off Hysteresis DCVDD Threshold Off -> On Analogue Reference Levels Reference voltage Potential divider resistance Line Input to ADC Input Signal Level (0dB) SNR (Note 1,3) SNR (Note 1,3) SNR (Note 1,3) VINLINE A-weighted, 0dB gain @ fs = 48kHz A-weighted, 0dB gain @ fs = 96kHz A-weighted, 0dB gain @ fs = 48KHz, AVDD = 2.7V DNR A-weighted, -60dB full scale input -1dB input, 0dB gain PSSR 1kHz 100mVpp 20Hz to 20kHz 100mVpp ADC channel separation Programmable Gain Maximum Programmable Gain Minimum Programmable Gain Step Size Mute attenuation Input Resistance Input Capacitance RINLINE CINLINE 1kHz input 1kHz input Rsource < 50 Ohms Guaranteed Monotonic 0dB, 1kHz input 0dB gain 12dB gain 20k 10k 85 85 1.0 AVDD/3.3 90 90 88 Vrms dB dB dB VVMID RVMID AVDD/2 50k V Ohms Vth VIH VOL 0.9 0.3 0.6 V V V SYMBOL VIL VIH VOL VOH 0.9 x DBVDD 0.7 x DBVDD 0.10 x DBVDD TEST CONDITIONS MIN TYP MAX 0.3 x DBVDD UNIT V V V V Digital Logic Levels (CMOS Levels) Dynamic Range (Note 3) THD Power Supply Rejection Ratio 90 -84 50 45 90 +12 -34.5 1.5 80 30k 15k 10 -74 dB dB dB dB dB dB dB dB Ohms Ohms pF w AI Rev 2.2 November 2001 5 WM8734 Advanced Information Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER 0dBfs Full scale output voltage SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) SYMBOL TEST CONDITIONS At LINE outputs A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted, @ fs = 48kHz, AVDD = 2.7V DNR A-weighted, -60dB full scale input 1kHz, 0dBfs 1kHz, -3dBfs Power Supply Rejection Ratio PSSR 1kHz 100mVpp 20Hz to 20kHz 100mVpp DAC channel separation Notes: 1. 2. 3. Ratio of output level with 1kHz full scale input, to the output level with the input short circuited, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth using an Audio analyser. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). 85 90 MIN TYP 1.0 x AVDD/3.3 100 98 93 MAX UNIT Vrms dB dB dB Line Output for DAC Playback Only (Load = 47k ohms. 50pF) Dynamic Range (Note 3) THD 95 -88 -92 50 45 100 -80 dB dB dB dB dB dB 4. TERMINOLOGY 1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attentuation (dB) – Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple – Any variation of the frequency response in the pass-band region. 3. 4. 5. 6. w AI Rev 2.2 November 2001 6 WM8734 MASTER CLOCK TIMING t MCLKL MCLK t MCLKH t MCLKY Advanced Information Figure 1 System Clock Timing Requirements Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time MCLK Duty cycle SYMBOL TXTIH TXTIL TXTIY TEST CONDITIONS MIN 18 18 54 40:60 TYP MAX UNIT ns ns ns 60:40 DIGITAL AUDIO INTERFACE – MASTER MODE BCLK ADCLRC WM8734 CODEC DACLRC ADCDAT DACDAT DSP ENCODER/ DECODER Figure 2 Master Mode Connection w AI Rev 2.2 November 2001 7 WM8734 Advanced Information BCLK (Output) ADCLRC/ DACLRC (Outputs) tDL tDDA ADCDAT DACDAT tDST Figure 3 Digital Audio Data Timing – Master Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER ADCLRC/DACLRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLCK rising edge DACDAT hold time from BCLK rising edge SYMBOL tDL TEST CONDITIONS MIN 0 TYP MAX 10 UNIT ns tDHT Audio Data Input Timing Information tDDA tDST tDHT 0 10 10 10 ns ns ns DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK ADCLRC WM8734 CODEC DACLRC ADCDAT DACDAT DSP ENCODER/ DECODER Figure 4 Slave Mode Connection w AI Rev 2.2 November 2001 8 WM8734 tBCH BCLK tBCY DACLRC/ ADCLRC tDS DACDAT tDD ADCDAT tDH tLRH tLRSU tBCL Advanced Information Figure 5 Digital Audio Data Timing – Slave Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low DACLRC/ADCLRC set-up time to BCLK rising edge DACLRC/ADCLRC hold time from BCLK rising edge DACDAT set-up time to BCLK rising edge DACDAT hold time from BCLK rising edge ADCDAT propagation delay from BCLK falling edge SYMBOL tBCY tBCH tBCL tLRSU tLRH tDS tDH tDD TEST CONDITIONS MIN 50 20 20 10 10 10 10 0 10 TYP MAX UNIT ns ns ns ns ns ns ns ns Audio Data Input Timing Information w AI Rev 2.2 November 2001 9 WM8734 MPU INTERFACE TIMING Advanced Information tCSL CSB tSCY tSCH SCLK tSCL tSCS tCSS tCSH SDIN tDSU tDHO LSB Figure 6 Program Register Input Timing – 3-Wire MPU Serial Control Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising SYMBOL tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS TEST CONDITIONS MIN 60 80 20 20 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns Program Register Input Information w AI Rev 2.2 November 2001 10 WM8734 Advanced Information t3 SDIN t6 SCLK t1 t10 t7 t2 t5 t4 t3 t8 Figure 7 Program Register Input Timing – 2-Wire MPU Serial Control Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SCLK Frequency SCLK Low Pulsewidth SCLK High Pulsewidth Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time t1 t2 t3 t4 t5 t6 t7 t8 t10 600 900 SYMBOL TEST CONDITIONS MIN 0 600 1.3 600 600 100 300 300 TYP MAX 400 UNIT kHz ns us ns ns ns ns ns ns ns Program Register Input Information w AI Rev 2.2 November 2001 11 WM8734 DEVICE DESCRIPTION Advanced Information The WM8734 is a high performance audio CODEC designed specifically for audio applications that require recording and playback features. The CODEC includes line inputs to the on-board ADC, line outputs from the on-board DAC, a configurable digital audio interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. The CODEC includes a stereo low noise input. Line inputs have +12dB to -34dB logarithmic volume level adjustments and mute. All the required input filtering is contained within the device. The on-board stereo analogue to digital converter (ADC) is of a high quality using a multi-bit highorder oversampling architecture delivering optimum performance with low power consumption. The output from the ADC is available on the digital audio interface. The ADC includes an optional digital high pass filter to remove unwanted dc components from the audio signal. The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio interface. Digital filter de-emphasis at 32kHz, 44.1kHz and 48kHz can be applied to the digital data under software control. The DAC employs a high quality multi-bit high-order oversampling architecture to again deliver optimum performance with low power consumption. Special techniques allow the audio to be muted and the device safely placed into standby, sections of the device powered off and volume levels adjusted without any audible clicks, pops or zipper noises. Therefore standby and power off modes may be used dynamically under software control, whenever recording or playback is not required. The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz. The digital filters used for both record and playback are optimised for each sampling rate used. The digitised output is available in a number of audio data formats I2S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First, right justified. The digital audio interface can operate in both master or slave modes. The software control uses either a 2 or 3-wire MPU interface. AUDIO SIGNAL PATH LINE INPUTS The WM8734 provides Left and Right channel line inputs (RLINEIN and LLINEIN). The inputs are high impedance and low capacitance, thus ideally suited to receiving line level signals from external hi-fi or audio equipment. Both line inputs include independent programmable volume level adjustments and input mute. The scheme is illustrated in Figure 8. Passive RF and active Anti-Alias filters are also incorporated within the line inputs. These prevent high frequencies aliasing into the audio band or otherwise degrading performance. w AI Rev 2.2 November 2001 12 WM8734 Advanced Information LINEIN 12.5K VMID To ADC Figure 8 Line Input Schematic The gain between the line inputs and the ADC is logarithmically adjustable from +12dB to –34.5dB in 1.5dB steps under software control. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The gain is independently adjustable on both Right and Left Line Inputs. However, by setting the INBOTH bit whilst programming the volume control, both channels are simultaneously updated with the same value. Use of INBOTH reduces the required number of software writes required. The line inputs to the ADC can be muted in the analogue domain under software control. The software control registers are shown below. REGISTER ADDRESS 0000000 Left Line In BIT 4:0 LABEL LINVOL[4:0] DEFAULT 10111 ( 0dB ) DESCRIPTION Left Channel Line Input Volume Control 11111 = +12dB . . 1.5dB steps down to 00000 = -34.5dB Left Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute Left to Right Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of LINVOL[4:0] and LINMUTE to RINVOL[4:0] and RINMUTE 0 = Disable Simultaneous Load Right Channel Line Input Volume Control 11111 = +12dB . .1.5dB steps down to 00000 = -34.5dB Right Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute Right to Left Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of RINVOL[4:0] and RINMUTE to LINVOL[4:0] and LINMUTE 0 = Disable Simultaneous Load 7 LINMUTE 1 8 LRINBOTH 0 0000001 Right Line In 4:0 RINVOL[4:0] 10111 ( 0dB ) 7 RINMUTE 1 8 RLINBOTH 0 Table 1 Line Input Software Control w AI Rev 2.2 November 2001 13 WM8734 Advanced Information The line inputs are biased internally through the operational amplifier to VMID. Whenever the line inputs are muted or the device placed into standby mode, the line inputs are kept biased to VMID using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when re-activating the inputs. The external components required to complete the line input application is shown in the Figure 9. R1 C2 LINEIN AGND R2 C1 AGND AGND Figure 9 Line Input Application Drawing For interfacing to a typical CD system, it is recommended that the input is scaled to ensure that there is no clipping of the signal. R1 = 5K, R2 = 5K, C1 = 47pF, C2 = 470nF (10V npo ceramic type). R1 and R2 form a resistive divider to attenuate the 2 Vrms output from a CD player to a 1 Vrms level, so avoiding overloading the inputs. R2 also provides a discharge path for C2, thus preventing the input to C2 charging to an excessive voltage which may otherwise damage any equipment connected that is not suitably protected against high voltages. C1 forms an RF low pass filter for increasing the rejection of RF interference picked up on any cables. C2 forms a DC blocking capacitor to remove the DC path between the WM8734 and the driving audio equipment. C2 together with the input impedance of the WM8734 form a high pass filter. ADC The WM8734 uses a multi-bit oversampled sigma-delta ADC. A single channel of the ADC is illustrated in the Figure 10. FROM LINE INPUT ANALOG INTEGRATOR TO ADC DIGITAL FILTERS MULTI BITS Figure 10 Multi-Bit Oversampling Sigma Delta ADC Schematic w AI Rev 2.2 November 2001 14 WM8734 Advanced Information The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The device employs a pair of ADCs. The two channels cannot be selected independently. The digital data from the ADC is fed for signal processing to the ADC Filters. ADC FILTERS The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. Figure 11 illustrates the digital filter path. FROM ADC DIGITAL DECIMATOR DIGITAL DECIMATION FILTER DIGITAL HPF TO DIGITAL AUDIO INTERFACE HPFEN Figure 11 ADC Digital Filter The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass filter response detailed in Digital Filter Characteristics. When the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. By setting HPOR the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. If the dc offset changed, the stored and subtracted value will not change unless the high-pass filter is enabled. The software control is shown in Table 2. REGISTER ADDRESS 00000101 Digital Audio Path Control 4 BIT 0 LABEL ADCHPD DEFAULT 0 DESCRIPTION ADC High Pass Filter Enable (Digital) 1 = Disable High Pass Filter 0 = Enable High Pass Filter Store dc offset when High Pass Filter disabled 1 = store offset 0 = clear offset HPOR 0 Table 2 ADC Software Control There are several types of ADC filters, frequency and phase responses of these are shown in Digital Filter Characteristics. The filter types are automatically configured depending on the sample rate chosen. Refer to the sample rate section for more details. DAC FILTERS The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by the analogue DAC. Figure 12 illustrates the DAC digital filter path. w AI Rev 2.2 November 2001 15 WM8734 Advanced Information FROM DIGITAL AUDIO INTERFACE DIGITAL DE_EMPHASIS MUTE DIGITAL INTERPOLATION FILTER TO LINE OUTPUTS DEEMP DACMU Figure 12 DAC Filter Schematic The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 3. The DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This removes any abrupt step changes in the audio that might otherwise result in audible clicks in the audio outputs. REGISTER ADDRESS 0000101 Digital Audio Path Control 2:1 BIT LABEL DEEMP[1:0] 00 DEFAULT DESCRIPTION De-emphasis Control (Digital) 11 = 48KHz 10 = 44.1KHz 01 = 32KHz 00 = Disable DAC Soft Mute Control (Digital) 1 = Enable soft mute 0 = Disable soft mute 3 DACMU 1 Table 3 DAC Software Control DAC The WM8734 employs a multi-bit sigma delta oversampling digital to analogue converter. The scheme for the converter is illustrated in Figure 13. FROM DAC DIGITAL FILTERS TO LINE OUTPUT Figure 13 Multi-Bit Oversampling Sigma Delta Schematic The DAC converts the multi-level digital audio data stream from the DAC digital filters into high quality analogue audio. w AI Rev 2.2 November 2001 16 WM8734 LINE OUTPUTS Advanced Information The WM8734 provides two low impedance line outputs LLINEOUT and RLINEOUT, suitable for driving typical line loads of impedance 10K and capacitance 50pF. The line output is used to selectively sum the outputs from the DAC or/and the Line inputs in bypass mode. The LLINEOUT and RLINEOUT outputs are only available at a line output level and are not level adjustable in the analogue domain, having a fixed gain of 0dB. The level is fixed such that at the DAC full scale level the output level is Vrms at AVDD = 3.3 volts. Note that the DAC full scale level tracks directly with AVDD. The scheme is shown in Figure 14. The line output includes a low order audio low pass filter for removing out-of band components from the sigma-delta DAC. Therefore no further external filtering is required in most applications. DACSEL FROM DAC LINEOUT VMID TO HEADPHONE AMP Figure 14 Line Output Schematic The line output is muted by either muting the DAC (analogue) or Soft Muting (digital). Refer to the DAC section for more details. Whenever the DAC is muted or the device placed into standby mode the DC voltage is maintained at the line outputs to prevent any audible clicks from being present. The software control for the line outputs is shown in Table 4. REGISTER ADDRESS 0000100 Analogue Audio Path Control BIT 4 LABEL DACSEL DEFAULT 0 DESCRIPTION DAC Select 1 = Select DAC 0 = Don’t select DAC Table 4 Output Software Control The recommended external components are shown in Figure 15. R2 LINEOUT C1 R1 AGND AGND w AI Rev 2.2 November 2001 17 WM8734 Figure 15 Line Outputs Application Drawing Advanced Information Recommended values are C1 = 470nF (10V npo type), R1 = 47KOhms, R2 = 100 Ohms C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can have dramatic effects on the measured signal distortion at the output. DEVICE OPERATION DEVICE RESETTING The WM8734 contains a power on reset circuit that resets the internal state of the device to a known condition. The power on reset is applied as DCVDD powers on and released only after the voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on threshold voltage then the power on reset is re-applied. The threshold voltages and associated hysteresis are shown in the Electrical Characteristics table. The user also has the ability to reset the device to a known state under software control as shown in the table below. REGISTER ADDRESS 0001111 Reset Register BIT 8:0 LABEL RESET DEFAULT not reset DESCRIPTION Reset Register Writing 00000000 to register resets device Table 5 Software Control of Reset W hen using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the ACK signal (approximately 1 SCLK period, refer to Figure 23). CLOCKING SCHEMES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. To allow WM8734 to be used in a centrally clocked system, the WM8734 is capable of deriving the sample rate clock from this Master Clock (Master Mode) or receiving the sample rate clock from an external source (Slave Mode). CORE CLOCK The WM8734 DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by software as shown in Table 6 below. REGISTER ADDRESS 0001000 Sampling Control BIT 6 LABEL CLKIDIV2 0 DEFAULT DESCRIPTION Core Clock divider select 1 = Core Clock is MCLK divided by 2 0 = Core Clock is MCLK Table 6 Software Control of Core Clock Having a programmable MCLK divider allows the device to be used in applications where higher frequency master Clocks are available. For example the device can support 512fs master clocks whilst fundamentally operating in a 256fs mode. DIGITAL AUDIO INTERFACES W M8734 may be operated in either one of the 4 offered audio interface modes. These are: • Right justified • Left justified • I2S • DSP mode All four of these modes are MSB first and operate with data 16 to 32 bits, except right justified mode which does not support 32 bits. w AI Rev 2.2 November 2001 18 WM8734 Advanced Information The digital audio interface takes the data from the internal ADC digital filter and places it on the ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low transition. BCLK maybe an input or an output dependent on whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section. The digital audio interface also receives the digital audio data for the internal DAC digital filters on the DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section There are four digital audio interface formats accommodated by the WM8734. These are shown in the figures below. Refer to the Electrical Characteristic section for timing information. Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR or DACLRC transition. 1/fs LEFT CHANNEL DACLRC/ ADCLRC RIGHT CHANNEL BCLK DACDAT/ ADCDAT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n MSB LSB MSB LSB Figure 16 Left Justified Mode I2S mode is where the MSB is available on the 2nd rising edge of BCLK following a LRCLK transition. 1/fs LEFT CHANNEL DACLRC/ ADCLRC RIGHT CHANNEL BCLK 1 BCLK 1 BCLK 3 n-2 n-1 n 1 2 3 n-2 n-1 n DACDAT/ ADCDAT 1 2 MSB LSB MSB LSB Figure 17 I2S Mode Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a LRCLK transition, yet MSB is still transmitted first. w AI Rev 2.2 November 2001 19 WM8734 1/fs Advanced Information LEFT CHANNEL DACLRC/ ADCLRC RIGHT CHANNEL BCLK DACDAT/ ADCDAT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n MSB Figure 18 Right Justified Mode LSB MSB LSB DSP mode is where the left channel MSB is available on either the 1st or 2nd rising edge of BCLK (selectable by LRP) following a LRC transition high. Right channel data immediately follows left channel data. 1/fs 1 BCLK DACLRC/ ADCLRC BCLK LEFT CHANNEL DACDAT/ ADCDAT 1 2 3 n-2 n-1 n 1 2 RIGHT CHANNEL 3 n-2 n-1 n MSB Input Word Length (IWL) LSB Note: Input word length is defined by the IWL register, LRP = 1 Figure 19 DSP Mode In all modes DACLRC and ADCLRC must always change on the falling edge of BCLK, refer to Figure 16, Figure 17, Figure 18 and Figure 19. Operating the digital audio interface in DSP mode allows ease of use for supporting the various sample rates and word lengths. The only requirement is that all data is transferred within the correct number of BCLK cycles to suit the chosen word length. In order for the digital audio interface to offer similar support in the three other modes (Left Justified, I2S and Right Justified), the DACLRC, ADCLRC and BCLK frequencies, continuity and mark-space ratios need more careful consideration. In Slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio. BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for each DACLRC/ADCLRC transition to clock the chosen data word length. w AI Rev 2.2 November 2001 20 WM8734 Advanced Information In Master mode, DACLRC and ADCLRC will be output with a 50:50 mark-space ratio with BCLK output at 64fs. The ADC and DAC digital audio interface modes are software configurable as indicated in Table 7. Note that dynamically changing the software format may result in erroneous operation of the interfaces and is therefore not recommended. The length of the digital audio data is programmable at 16/20/24 or 32 bits. Refer to the software control table below. The data is signed 2’s complement. Both ADC and DAC are fixed at the same data length. The ADC and DAC digital filters process data using 24 bits. If the ADC is programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data. If the ADC is programmed to output 32 bits then it packs the LSBs with zeros. If the DAC is programmed to receive 16 or 20 bit data, the WM8734 packs the LSBs with zeros. If the DAC is programmed to receive 32 bit data, then it strips the LSBs. The DAC outputs can be swapped under software control using LRP and LRSWAP as shown in Table 7. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses the order of that a Left sample goes to the right DAC output and a Right sample goes to the left DAC output. LRP swaps the phasing so that a Right/Left sampled pair is expected and preserves the correct channel phase difference. To accommodate system timing requirements the interpretation of BCLK may be inverted, this is controlled vias the software shown in Table 6. This is especially appropriate for DSP mode. ADCDAT lines are always outputs. They power up and return from standby low. DACDAT is always an input. It is expected to be set low by the audio interface controller when the WM8734 is powered off or in standby. ADCLRC, DACLRC and BCLK can be either outputs or inputs depending on whether the device is configured as a master or slave. If the device is a master then the ADCLRC, DACLRC and BCLK signals are outputs that default low. If the device is a slave then the ADCLRC, DACLRC and BCLK are inputs. w AI Rev 2.2 November 2001 21 WM8734 REGISTER ADDRESS 0000111 Digital Audio Interface Format BIT 1:0 LABEL FORMAT[1:0] DEFAULT 10 Advanced Information DESCRIPTION Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I2S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits DACLRC phase control (in left, right or I2S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low (opposite phasing in I2S mode) or DSP mode A/B select (in DSP mode only) 1 = MSB is available on 2nd BCLK rising edge after ADCLRC/DACLRC rising edge 0 = MSB is available on 1st BCLK rising edge after ADCLRC/DACLRC rising edge DAC Left Right Clock Swap 1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Bit Clock Invert 1 = Invert BCLK 0 = Don’t invert BCLK 3:2 IWL[1:0] 10 4 LRP 0 5 LRSWAP 0 6 MS 0 7 BCLKINV 0 Table 7 Digital Audio Interface Control Note: If right justified 32 bit mode is selected then the WM8734 defaults to 24 bits. MASTER AND SLAVE MODE OPERATION The WM8734 can be configured as either a master or slave mode device. As a master mode device the WM8734 controls sequencing of the data and clocks on the digital audio interface. As a slave device the WM8734 responds with data to the clocks it receives over the digital audio interface. The mode is set with the MS bit of the control register as shown in Table 8. REGISTER ADDRESS 0000111 Digital Audio Interface Format 6 BIT LABEL MS DEFAULT 0 DESCRIPTION Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Table 8 Programming Master/Slave Modes w AI Rev 2.2 November 2001 22 WM8734 Advanced Information As a master mode device the WM8734 controls the sequencing of data transfer (ADCDAT, DACDAT) and output of clocks (BCLK, ADCLRC, DACLRC) over the digital audio interface. It uses the timing generated from either its on-board crystal or the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 20. ADCDAT is always an output from and DACDAT is always an input to the WM8734 independent of master or slave mode. BCLK ADCLRC WM8734 CODEC DACLRC ADCDAT DACDAT DSP ENCODER/ DECODER Figure 20 Master Mode As a slave device the WM8734 sequences the data transfer (ADCDAT, DACDAT) over the digital audio interface in response to the external applied clocks (BCLK, ADCLRC, DACLRC). This is illustrated in Figure 21. BCLK ADCLRC WM8734 CODEC DACLRC ADCDAT DACDAT DSP ENCODER/ DECODER Figure 21 Slave Mode Note that the WM8734 relies on controlled phase relationships between audio interface BCLK, DACLRC and the master MCLK. To avoid any timing hazards, refer to the timing section for detailed information. AUDIO DATA SAMPLING RATES The WM8734 provides for two modes of operation (normal and USB) to generate the required DAC and ADC sampling rates. Normal and USB modes are programmed under software control according to the table below. In Normal mode, the user controls the sample rate by using an appropriate MCLK or crystal frequency and the sample rate control register setting. The WM8734 can support sample rates from 8ks/s up to 96ks/s. In USB mode, the user must use a fixed MLCK or crystal frequency of 12MHz to generate sample rates from 8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock is at 12MHz and the WM8734 can be directly used within such systems. WM8734 can generate all the normal audio sample rates from this one Master Clock frequency, removing the need for different master clocks or PLL circuits. w AI Rev 2.2 November 2001 23 WM8734 Advanced Information Uniquely, the WM8734 offers the user the ability to sample the ADC and DAC at different rates under software control in both Normal and USB modes. The reduces the burden on any controlling DSP. However, the signal processing in the ADC and DAC over-sampling filters is tightly coupled together in order to minimise power consumption. To this end, only the combinations of sample rates listed in the following sections are supported. Note that these rates supported are anticipated to be the likely combinations used in typical audio systems. REGISTER ADDRESS 0001000 Sampling Control BIT 0 LABEL USB/ NORMAL BOSR DEFAULT 0 DESCRIPTION Mode Select 1 = USB mode (250/272fs) 0 = Normal mode (256/384fs) Base Over-Sampling Rate USB Mode 0 = 250fs 1 = 272fs 5:2 SR[3:0] 0000 Normal Mode 0 = 256fs 1 = 384fs 1 0 ADC and DAC sample rate control; See USB Mode and Normal Mode Sample Rate sections for operation Table 9 Sample Rate Control SAMPLE RATE SETTING In normal mode MCLK/crystal oscillator is set up according to the desired sample rates of the ADC and DAC. For ADC or DAC sampling rates of 8, 32, 48 or 96KHz, MCLK frequencies of either 12.288MHz (256fs) or 18.432MHz (384fs) can be used. For ADC or DAC sampling rates of 8, 44.1 or 88.2KHz from MCLK frequencies of either 11.2896MHz (256fs) or 16.9344MHz (384fs) can be used. The table below should be used to set up the device to work with the various sample rate combinations. For example if the user wishes to use the WM8734 in normal mode with the ADC and DAC sample rates at 48KHz and 48KHz respectively then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 12.288MHz MCLK or with BOSR = 1, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 18.432MHz MCLK. The ADC and DAC will then operate with a Digital Filter of type 1, refer to Digital Filter Characteristics section for an explanation of the different filter types. w AI Rev 2.2 November 2001 24 WM8734 SAMPLING RATE ADC KHz 48 48 8 8 32 96 44.1 44.1 8 (Note 1) DAC KHz 48 8 48 8 32 96 44.1 8 (Note 1) 44.1 MHz 12.288 18.432 12.288 18.432 12.288 18.432 12.288 18.432 12.288 18.432 12.288 18.432 11.2896 16.9344 11.2896 16.9344 11.2896 16.9344 11.2896 16.9344 11.2896 16.9344 BOSR 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS SR3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 SR2 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 SR1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 Advanced Information DIGITAL FILTER TYPE SR0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 2 1 1 1 1 2 1 1 1 1 1 8 8 (Note 1) (Note 1) 88.2 88.2 Table 10 Normal Mode Sample Rate Look-up Table Notes: 1. 2. 8k not exact, actual = 8.018kHz All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid The BOSR bit represents the base over-sampling rate. This is the rate that the WM8734 digital signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at 256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the actual audio data rate produced by the ADC and required by the DAC. Example scenarios are: 1. with a requirement that the ADC data rate is 8KHz and DAC data rate is 48KHz, then choosing MCLK = 12.288MHz the device is programmed with BOSR = 0 (256fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0.The ADC output data rate will then be exactly 8KHz (derived from 12.288MHz/256 x1/6) and the DAC expects data at exactly 48KHz (derived from 12.288MHz/256) with a requirement that ADC data rate is 8KHz and DAC data rate is 44.1KHz, then choosing MCLK = 16.9344MHz the device is programmed with BOSR = 1 (384fs), SR3 = 1, SR2 = 0, SR1 = 0, SR0 = 1. The ADC will no longer output data at exactly 8.000KHz, instead it will be 8.018KHz (derived from 16.9344MHz/384 x 2/11), the DAC still is at exactly 44.1KHz (derived from 16.9344MHz/384). A slight (sub 0.5%) pitch shift will therefore result in the 8KHz audio data and (importantly) the user must ensure that the data across the digital interface is correctly synchronised at the 8.018KHz rate. 2. w AI Rev 2.2 November 2001 25 WM8734 Advanced Information The exact sample rates achieved are defined by the relationships in Table 11 below. TARGET SAMPLING RATE MCLK=12.288 KHz 8 32 44.1 48 88.2 96 KHz 8 12.288MHz/256 x 1/6 ACTUAL SAMPLING RATE BOSR=0 (256fs) MCLK=11.2896 KHz 8.018 11.2896MHz/256 x 2/11 BOSR=1 (384fs) MCLK=18.432 KHz 8 18.432MHz/384 x 1/6 MCLK=16.9344 KHz 8.018 16.9344MHz/384 x 2/11 32 12.288MHz/256 x 2/3 not available 44.1 11.2896MHz/256 32 18.432MHz/384x 2/3 not available 44.1 16.9344MHz /384 not available 48 12.288MHz/256 not available 48 18.432MHz/384 not available 88.2 11.2896MHz/384 x 2 not available 88.2 16.9344MHz /384 x 2 not available 96 12.288MHz/256 x 2 not available 96 18.432MHz/384 x 2 not available not available Table 11 Normal Mode Actual Sample Rates 128/192fs NORMAL MODE The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the WM8734 is also capable of being clocked from a 128 or 192fs MCLK for application over limited sampling rates as shown in the table below. SAMPLING RATE ADC KHz 48 44.1 DAC KHz 48 44.1 MHz 6.144 9.216 5.6448 8.4672 BOSR 0 1 0 1 MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS SR3 0 0 1 1 SR2 1 1 1 1 SR1 1 1 1 1 SR0 1 1 1 1 2 2 DIGITAL FILTER TYPE Table 12 128fs Normal Mode Sample Rate Look-up Table 512/768fs NORMAL MODE 512 fs and 768 fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384 fs internally and the device otherwise operates as in Table 8 but with MCLK at twice the specified rate. See Table 6 for software control. w AI Rev 2.2 November 2001 26 WM8734 USB MODE SAMPLE RATES In USB mode the MCLK/crystal oscillator input is 12MHz only. SAMPLING RATE ADC KHz 48 DAC KHz 48 MHz 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 BOSR 0 1 0 1 0 1 0 1 0 0 1 MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS SR3 0 1 0 1 0 1 0 1 0 0 1 SR2 0 0 0 0 0 0 0 0 1 1 1 SR1 0 0 0 0 1 1 1 1 1 1 1 Advanced Information DIGITAL FILTER TYPE SR0 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 3 2 44.1 44.1 (Note 2) (Note 2) 48 8 44.1 8 (Note 2) (Note 1) 8 48 8 44.1 (Note 1) (Note 2) 8 8 8 8 (Note 1) (Note 1) 32 32 96 96 88.2 88.2 (Note 3) (Note 3) Table 13 USB Mode Sample Rate Look-ip Table Notes: 1. 2. 3. 4. 8k not exact, actual = 8.021kHz 44.1k not exact, actual = 44.118kHz 88.1k not exact, actual = 88.235kHz All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid The table above can be used to set up the device to work with various sample rate combinations. For example if the user wishes to use the WM8734 in USB mode with the ADC and DAC sample rates at 48KHz and 48KHz respectively then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0. The ADC and DAC will then operate with a Digital Filter of type 0, refer to Digital Filter Characteristics section for an explanation of the different filter types. The BOSR bit represents the base over-sampling rate. This is the rate that the WM8734 digital signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB mode, with BOSR = 0, the base over-sampling rate is defined at 250fs, with BOSR = 1, the base oversampling rate is defined at 272fs. This can be used to determine the actual audio sampling rate produced by the ADC and required by the DAC. Example scenarios are, :1. with a requirement that the ADC data sampling rate is 8KHz and DAC data sampling rate is 48KHz the device is programmed with BOSR = 0 (250fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0.The ADC will then be exactly 8KHz ( derived from 12MHz/250 x 1/6 ) and the DAC expects data at exactly 48KHz ( derived from 12MHz/250 ). with a requirement that ADC data rate is 8KHz and DAC data rate is 44.1KHz the device is programmed with BOSR = 0 (272fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will not output data at exactly 8KHz, instead it will be 8.021KHz ( derived from 12MHz/272 x 2/11 ) and the DAC at 44.118KHz ( derived from 12MHz/272 ). A slight (sub 0.5%) pitch shift will therefore results in the 8KHz and 44.1KHz audio data and (more importantly) the user must ensure that 2. w AI Rev 2.2 November 2001 27 WM8734 Advanced Information the data across the digital interface is correctly synchronised at the 8.021KHz and 44.117KHz rates. The exact sample rates supported for all combinations are defined by the relationships in Table 14 below. TARGET SAMPLING RATE KHz 8 32 44.1 48 88.2 96 ACTUAL SAMPLING RATE BOSR=0 ( 250fs) KHz 8 12MHz/(250 x 48/8) BOSR=1 (272fs) KHz 8.021 12MHz/(272 x 11/2) 32 12MHz/(250 x 48/32) not available 44.117 12MHz/272 not available 48 12MHz/250 not available 88.235 12MHz/136 not available 96 12MHz/125 not available Table 14 USB Mode Actual Sample Rates ACTIVATING DSP AND DIGITAL AUDIO INTERFACE To prevent any communication problems from arising across the Digital Audio Interface the Audio Interface is disabled (tristate with weak 100k pulldown). Once the Audio Interface and the Sampling Control has been programmed it is activated by setting the ACTIVE bit under Software Control. REGISTER ADDRESS 0001001 Active Control 0 BIT LABEL ACTIVE 0 DEFAULT DESCRIPTION Activate Interface 1 = Active 0 = Inactive Table 15 Activating DSP and Digital Audio Interface It is recommended that between changing any content of Digital Audio Interface or Sampling Control Register that the active bit is reset then set. SOFTWARE CONTROL INTERFACE The software control interface may be operated using either a 3-wire (SPI-compatible) or 2-wire MPU interface. Selection of interface format is achieved by setting the state of the MODE pin. In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two addresses. Unused register bits should always be set to ‘0’ unless specified otherwise. SELECTION OF SERIAL CONTROL MODE The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved by setting the state of the MODE pin. MODE 0 1 INTERFACE FORMAT 2 wire 3 wire Table 16 Control Interface Mode Selection w AI Rev 2.2 November 2001 28 WM8734 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE Advanced Information The WM8734 can be controlled using a 3-wire serial interface. SDIN is used for the program data, SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire interface protocol is shown in Figure 22. CSB SCLK SDIN B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Figure 22 3-Wire Serial Interface Notes: 1. 2. B[15:9] are Control Address Bits B[8:0] are Control Data Bits 2-WIRE SERIAL CONTROL MODE The WM8734 supports a 2-wire MPU serial interface. The device operates as a slave device only. The WM8734 has one of two slave addresses that are selected by setting the state of pin 10, (CSB). SDIN SCLK START R ADDR R/W ACK DATA B15-8 ACK DATA B7-0 ACK STOP Figure 23 2-Wire Serial Interface Notes: 1. 2. B[15:9] are Control Address Bits B[8:0] are Control Data Bits Address 0011010 0011011 CSB STATE (Default = LOW) 0 1 Table 17 2-Wire MPU Interface Address Selection To control the WM8734 on the 2-wire bus the master control device must initiate a data transfer by establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high. This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of two available addresses for this device (see table 24). If the correct address is received and the R/W bit is ‘0’, indicating a write, then the WM8734 will respond by pulling SDIN low on the next clock pulse (ACK). The WM8734 is a write only device and will only respond to the R/W bit indicating a write. If the address is not recognised the device will return to the idle condition and wait for a new start condition and valid address. Once the WM8734 has acknowledged a correct address, the controller will send eight data bits (bits B[15]-B[8]). WM8734 will then acknowledge the sent data by pulling SDIN low for one clock pulse. The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8734 will then acknowledge again by pulling SDIN low. w AI Rev 2.2 November 2001 29 WM8734 Advanced Information A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a start or stop condition is detected out of sequence at any point in the data transfer then the device will jump to the idle condition. After receiving a complete address and data sequence the WM8734 returns to the idle state and waits for another start condition. Each write to a register requires the complete sequence of start condition, device address and R/W bit followed by the 16 register address and data bits. Note that the 16 bit control word is made up of 7 address bits, B[15:9], and 9 data bits, B[8:0]. These are transmitted as 2 blocks of 8 bits. The first block contains 7 address bits and the data HSB. The second block contains the 8 data LSBs. POWER DOWN MODES The WM8734 contains power conservation modes in which various circuit blocks may be safely powered down in order to conserve power. This is software programmable as shown in the table below. REGISTER ADDRESS 0000110 Power Down Control 0 BIT LABEL LINEINPD DEFAULT 1 DESCRIPTION Line Input Power Down 1 = Enable Power Down 0 = Disable Power Down ADC Power Down 1 = Enable Power Down 0 = Disable Power Down DAC Power Down 1 = Enable Power Down 0 = Disable Power Down Line Output Power Down 1 = Enable Power Down 0 = Disable Power Down Power Off Device 1 = Device Power Off 0 = Device Power On 2 ADCPD 1 3 DACPD 1 4 OUTPD 1 7 POWEROFF 1 Table 18 Power Conservation Modes Software Control W hen writing to the powerdown register bits 1,5 & 6 should be set to ‘1’. The power down control can be used to either a) permanently disable functions when not required in certain applications or b) to dynamically power up and down functions depending on the operating mode, e.g.: during playback or record. Please follow the special instructions below if dynamic implementations are being used. LINEINPD: Simultaneously powers down both the Line Inputs. This can be done dynamically without any audible effects either on the ADC or to the Line Outputs in Bypass mode. This is of use when the device enters Playback, Pause or Stop modes or the Microphone input has been selected. ADCPD: Powers down the ADC and ADC Filters. If this is done dynamically then audible pops will result if any signals were present through the ADC. To overcome this whenever the ADC is to be powered down, either mute the Microphone Input (MUTEIN) or MUTELINEIN, then change ADCPD. This is of use when the device enters Playback, Pause or Stop modes regardless of whether Microphone or Line Inputs are selected. DACPD: Powers down the DAC and DAC Digital Filters. If this is done dynamically then audible pops will result unless the following guidelines are followed. In order to prevent pops, the DAC should first be soft-muted (DACMU), the output should then be de-selected from the line and headphone output (DACSEL), then the DAC powered down (DACPD). This is of use when the device enters Record, Pause, Stop or Bypass modes. The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry under software control as shown in Table 18. Provision has been made to independently power off these areas according to Table 19. w AI Rev 2.2 November 2001 30 WM8734 POWER OFF DESCRIPTION OUTPD Advanced Information LINEINPD DACPD ADCPD 0 1 1 1 1 STANDBY Table 19 Standby Mode In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue circuitry remain active. The active analogue includes the analogue VMID reference so that the analogue line inputs, line outputs and headphone outputs remain biased to VMID. This reduces any audible effects caused by DC glitches when entering or leaving STANDBY mode. The device can be powered off by writing to the POWEROFF bit of the Power Down register. In POWEROFF mode the Control Interface and a small portion of the digital remain active. The analogue VMID reference is disabled. POWER OFF DESCRIPTION LINEINPD DACPD ADCPD OUTPD 1 X X X X POWEROFF Table 20 Poweroff Mode w AI Rev 2.2 November 2001 31 WM8734 REGISTER MAP Advanced Information The complete register map is shown in Table 21. The detailed description can be found in the relevant text of the device description. There are 8 registers with 9 bits per register. These can be controlled using either the 2 wire or 3 wire MPU interface. REGISTER ADDRESS 0000000 Left Line In BIT 4:0 LABEL LINVOL[4:0] DEFAULT 10111 ( 0dB ) DESCRIPTION Left Channel Line Input Volume Control 11111 = +12dB . . 1.5dB steps down to 00000 = -34.5dB Left Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute Left to Right Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of LINVOL[4:0] and LINMUTE to RINVOL[4:0] and RINMUTE 0 = Disable Simultaneous Load Right Channel Line Input Volume Control 11111 = +12dB . .1.5dB steps down to 00000 = -34.5dB Right Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute Right to Left Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of RINVOL[4:0] and RINMUTE to LINVOL[4:0] and LINMUTE 0 = Disable Simultaneous Load DAC Select 1 =Select DAC 0 = Don’t select DAC ADC High Pass Filter Enable 1 = Enable High Pass Filter 0 = Disable High Pass Filter De-emphasis Control 11 = 48KHz 10 = 44.1KHz 01 = 32KHz 00 = Disable DAC Soft Mute Control 1 = Enable soft mute 0 = Disable soft mute Store dc offset when High Pass Filter disabled 1 = store offset 0 = clear offset 7 LINMUTE 1 8 LRINBOTH 0 0000001 Right Line In 4:0 RINVOL[4:0] 10111 ( 0dB ) 7 RINMUTE 1 8 RLINBOTH 0 0000100 Analogue Audio Path Control 0000101 Digital Audio Path Control 4 DACSEL 0 0 ADCHPD 0 2:1 DEEMP[1:0] 00 3 DACMU 1 4 HPOR 0 w AI Rev 2.2 November 2001 32 WM8734 REGISTER ADDRESS 0000110 Power Down Control BIT 0 LABEL LINEINPD DEFAULT 1 Advanced Information DESCRIPTION Line Input Power Down 1 = Enable Power Down 0 = Disable Power Down ADC Power Down 1 = Enable Power Down 0 = Disable Power Down DAC Power Down 1 = Enable Power Down 0 = Disable Power Down Line Output Power Down 1 = Enable Power Down 0 = Disable Power Down POWEROFF mode 1 = Enable POWEROFF 0 = Disable POWEROFF Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I2S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits DACLRC phase control (in left, right or I2S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low (opposite phasing in I2S mode) or DSP mode A/B select (in DSP mode only) 1 = MSB is available on 2nd BCLK rising edge after ADCLRC/DACLRC rising edge 0 = MSB is available on 1st BCLK rising edge after ADCLRC/DACLRC rising edge DAC Left Right Clock Swap 1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Bit Clock Invert 1 = Invert BCLK 0 = Don’t invert BCLK 2 ADCPD 1 3 DACPD 1 4 OUTPD 1 7 POWEROFF 1 0000111 Digital Audio Interface Format 1:0 FORMAT[1:0] 10 3:2 IWL[1:0] 10 4 LRP 0 5 LRSWAP 0 6 MS 0 7 BCLKINV 0 w AI Rev 2.2 November 2001 33 WM8734 REGISTER ADDRESS 0001000 Sampling Control BIT 0 LABEL USB/ NORMAL BOSR DEFAULT 0 Advanced Information DESCRIPTION Mode Select 1 = USB mode (250/272fs) 0 = Normal mode (256/384fs) Base Over-Sampling Rate 0 = 256fs 1 = 384fs ADC and DAC sample rate control Core Clock divider select 1 = Core Clock is MCLK divided by 2 0 = Core Clock is MCLK Activate Interface 1 = Active 0 = Inactive 1 0 5:2 6 SR[3:0] CLKIDIV2 0000 0 0001001 Active Control 0 ACTIVE 0 Table 21 Register Map Description Note: Unused register bits should be set to ‘0’ except when writing to Register 0000110, when bits 1,5 and 6 should be set to ‘1’. DIGITAL FILTER CHARACTERISTICS The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. PARAMETER Passband Passband Ripple Stopband Stopband Attenuation Passband Passband Ripple Stopband Stopband Attenuation High Pass Filter Corner Frequency f > 0.5465fs -3dB -0.5dB -0.1dB +/- 0.03dB -6dB Passband Ripple Stopband Stopband Attenuation Passband Passband Ripple Stopband Stopband Attenuation Table 22 Digital Filter Characteristics f > 0.5465fs 0.5465fs -50 dB f > 0.584fs +/- 0.03dB -6dB DAC Filter Type 1 (USB mode, 272fs or Normal mode operation) 0 0.5fs +/- 0.03 dB 0.4535fs 0.584fs -50 dB 0 0.5fs +/-0.03 dB 0.5465fs -60 3.7 10.4 21.6 0.416fs dB Hz f > 0.584fs +/- 0.05dB -6dB ADC Filter Type 1 (USB mode, 272fs or Normal mode operation) 0 0.5fs +/- 0.05 dB 0.4535fs 0.584fs -60 dB TEST CONDITIONS +/- 0.05dB -6dB MIN 0 0.5fs +/- 0.05 dB TYP MAX 0.416fs UNIT ADC Filter Type 0 (USB Mode, 250fs operation) DAC Filter Type 0 (USB mode, 250fs operation) Passband w AI Rev 2.2 November 2001 34 WM8734 TERMINOLOGY 1. 2. Advanced Information Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple – any variation of the frequency response in the pass-band region DAC FILTER RESPONSES 0.04 0 0.03 -20 0.02 Response (dB) Response (dB) 0.01 0 -0.01 -0.02 -40 -60 -80 -0.03 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 Figure 24 DAC Digital Filter Frequency Response –Type 1 Figure 25 DAC Digital Filter Ripple –Type 1 0.02 0 0.01 -20 0 Response (dB) Response (dB) -0.01 -0.02 -0.03 -0.04 -40 -60 -80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 26 DAC Digital Filter Frequency Response –Type 2 Figure 27 DAC Digital Filter Ripple –Type 2 ADC FILTER RESPONSES 0.02 0 0.01 -20 0 Response (dB) Response (dB) -0.01 -0.02 -0.03 -0.04 -40 -60 -80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 w AI Rev 2.2 November 2001 35 WM8734 Figure 28 ADC Digital Filter Frequency Response –Type 1 Advanced Information Figure 29 ADC Digital Filter Ripple –Type 1 0.02 0 0.01 -20 0 Response (dB) Response (dB) -0.01 -0.02 -0.03 -0.04 -40 -60 -80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25 Figure 30 ADC Digital Filter Frequency Response –Type 2 Figure 31 ADC Digital Filter Ripple –Type 2 ADC HIGH PASS FILTER The WM8734 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial. H(z) = 1 – z-1 1 – 0.9995 z-1 DIGITAL DE-EMPHASIS CHARACTERISTICS 0 0.4 0.3 -2 0.2 Response (dB) Response (dB) -4 0.1 0 -0.1 -0.2 -6 -8 -0.3 -10 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000 -0.4 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000 Figure 32 De-Emphasis Frequency Response (32kHz) 0 Figure 33 De-Emphasis Error (32kHz) 0.4 0.3 -2 0.2 Response (dB) Response (dB) -4 0.1 0 -0.1 -0.2 -6 -8 -0.3 -10 0 5000 10000 Frequency (Fs) 15000 20000 -0.4 0 5000 10000 Frequency (Fs) 15000 20000 w AI Rev 2.2 November 2001 36 WM8734 Figure 34 De-Emphasis Frequency Response (44.1kHz) 0 Advanced Information Figure 35 De-Emphasis Error (44.1kHz) 0.4 0.3 -2 0.2 Response (dB) Response (dB) -4 0.1 0 -0.1 -0.2 -6 -8 -0.3 -10 0 5000 10000 15000 Frequency (Fs) 20000 -0.4 0 5000 10000 15000 Frequency (Fs) 20000 Figure 36 De-Emphasis Frequency Response (48kHz) Figure 37 De-Emphasis Error (48kHz) w AI Rev 2.2 November 2001 37 WM8734 RECOMMENDED EXTERNAL COMPONENTS 3.3V 2 Advanced Information 3.3V + 1 DGND AGND 11 0.4µF 10µF 0.1µF 20 + 3.3V DCVDD 5KΩ 5KΩ + 14 LLINEIN 470nF 47pF 5KΩ 5KΩ + 13 + RLINEIN 470nF 47pF LOUT 8 100Ω 47kΩ 470nF WM8734 Codec 5 4 + ROUT 9 100Ω 47kΩ Audio Serial Data I/F 6 7 3 DACLRC DACDAT ADCDAT ADCLRC BCLK 470nF 3-wire Interface 2-wire Interface 3.3V 10k Ω 15 16 3-wire or 2-wire MPU Interface 17 18 MODE CSB SDIN SCLK MCLK 19 VMID 12 0.1µF + Figure 38 External Components Diagram w AI Rev 2.2 November 2001 38 + 10µF 10µF DBVDD AVDD 10 WM8734 PACKAGE DIMENSIONS (SSOP) DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm) Advanced Information DM0015.A b 20 e 11 E1 E GAUGE PLANE 1 10 Θ D 0.25 c A A2 A1 -C0.10 C SEATING PLANE L Symbols A A1 A2 b c D e E E1 L θ REF: MIN ----0.05 1.65 0.22 0.09 6.90 7.40 5.00 0.55 o 0 Dimensions (mm) NOM --------1.75 --------7.20 0.65 BSC 7.80 5.30 0.75 o 4 JEDEC.95, MO-150 MAX 2.0 ----1.85 0.38 0.25 7.50 8.20 5.60 0.95 o 8 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. w AI Rev 2.2 November 2001 39 WM8734 PACKAGE DIMENSIONS (QFN) FL: 28 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH TOP VIEW D2 B 22 D2/2 27 28 L INDEX AREA (D/2 X E/2) D Advanced Information DM023.C 21 1 2 E2/2 A A E2 E 15 7 SEE DETAIL B 2X 14 e 13 B 8 b ccc M C A B 2X aaa C aaa C DETAIL B DATUM ccc C A 0.08 C A1 (A3) SEATING PLANE R C e TERMINAL TIP 1 Symbols A A1 A3 b D D2 E E2 e L R aaa ccc REF: MIN 0.80 0 0.18 3.2 3.2 0.35 b(min)/2 Tolerances of Form and Position 0.15 0.10 JEDEC.95, MO-220, VARIATION VHHD-1 Dimensions (mm) NOM MAX 0.90 1.00 0.02 0.05 0.2 REF 0.23 0.30 5.00 BSC 3.3 3.4 5.00 BSC 3.3 3.4 0.5 BSC 0.4 0.45 NOTE 2 1 2 2 NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC.95, MO-220 WITH THE EXCEPTION OF D2, E2, A3: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION A3: NOMINAL VALUE LESS THAN JEDEC 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. w AI Rev 2.2 November 2001 40 WM8734 Advanced Information REVISION HISTORY Revision 2.2 Originator EV Change Date 19/11/2001 History Front Page: Added mention of QFN package; changed SCLK to input only in Block Diagram (was previously drawn as I/O) Page 3: Added QFN pinout diagram, pin description, and order info Pages 2/3, pin descriptions: SDIN changed to I/O (was input only) Page 41: Added QFN package diagram Page 42: Added Revision history w AI Rev 2.2 November 2001 41 WM8734 IMPORTANT NOTICE Advanced Information W olfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: W olfson Microelectronics Ltd 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom Tel :: +44 (0)131 667 9386 Fax :: +44 (0)131 667 5176 Email :: sales@wolfsonmicro.com w AI Rev 2.2 November 2001 42