97632-11

Advance Information PE97632 Product Description Peregrine’s PE97632 is a high performance fractional-N PLL capable of frequency synthesis up to 3.2 GHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with the existing commercial space PLLs. The PE97632 features a 10/11 dual modulus prescaler, counters, a delta sigma modulator, and a phase comparator as shown in Figure 1. Counter values are programmable through either a serial interface or directly hard-wired. The PE97632 is optimized for commercial space applications. Single Event Latch up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit / day. Fabricated in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS technology, the PE97632 offers excellent RF performance and intrinsic radiation tolerance. 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications Features • 3.2 GHz operation • ÷10/11 dual modulus prescaler • Phase detector output • Serial or Direct mode access • Frequency selectivity: Comparison frequency / 218 • Low power — 50 mA at 3.3 V • Rad-Hard • Ultra-low phase noise • 68-lead CQFJ Figure 1. Block Diagram Fin Fin M8:0 A3:0 R5:0 Pre_en Sdata Primary 21-bit Latch Prescaler 10/11 Main Counter 13 20 Secondary 20-bit Latch Auxiliary 20-bit Latch + 13 20 18 DSM 19 4 6 6 PD_U Phase Detector PD_D fr 18 K17:0 Direct R Counter Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 16 PE97632 Advance Information Figure 2. Pin Configuration and package photo RAND_EN MS2_SEL GND GND 61 ENH VDD VDD 63 NC FR 62 R5 R4 R3 R2 R1 R0 K1 K0 68 67 65 66 64 9 7 6 4 2 8 5 3 1 VDD 10 K2 K3 11 12 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 V DD 28 GND 29 M 0 30 M 1 31 M 2 32 M3 33 M4 34 M5 35 M6 36 M7 37 M8 38 A0 39 A1 40 A2 41 A3 42 DIRECT 43 PRE_EN VDD VDD GND PD_U NC PD_D GND VDD DOUT LD CEXT GND FIN FIN VDD GND VDD K4 13 K5 14 K6 15 K7 16 K8 17 K9 18 K10 K11 K12 K13 19 20 21 22 K14 23 K15 24 K16 25 K17 26 Table 1. Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin Name R0 R1 R2 R3 R4 R5 K0 K1 GND VDD K2 K3 K4 K5 K6 Valid Mode Direct Direct Direct Direct Direct Direct Direct Direct Type Input Input Input Input Input Input Input Input Downbond (Note 1) R Counter bit0 (LSB). R Counter bit1. R Counter bit2. R Counter bit3. R Counter bit4. R Counter bit5 (MSB). K Counter bit0 (LSB). K Counter bit1. Ground Digital core VDD. K Counter bit2. K Counter bit3. K Counter bit4. K Counter bit5. K Counter bit6. Description Direct Direct Direct Direct Direct Input Input Input Input Input ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 16 Document No. 70-0205-02 │ U ltraCMOS™ RFIC Solutions PE97632 Advance Information Pin No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 VDD GND M0 M1 M2 M3 M4 Valid Mode Direct Direct Direct Direct Direct Direct Direct Direct Direct Direct Direct Type Input Input Input Input Input Input Input Input Input Input Input (Note 1) Downbond K Counter bit7. K Counter bit8. K Counter bit9. K Counter bit10. K Counter bit11. K Counter bit12. K Counter bit13. K Counter bit14. K Counter bit15. K Counter bit16. K Counter bit17 (MSB). Digital core VDD. Ground M C ounter bit0 (LSB). M C ounter bit1. M C ounter bit2 M C ounter bit3. M C ounter bit4. Description Direct Direct Direct Direct Direct Serial Direct Serial Direct Serial Direct Direct Direct Direct Serial Direct Direct Both Direct Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input (Note 1) Downbond 33 S_WR M5 34 SDATA M6 35 SCLK 36 37 38 M7 M8 A0 A1 39 E_WR 40 41 42 43 44 45 A2 A3 DIRECT Pre_en VDD GND Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are transferred to the secondary register on S_WR or Hop_WR rising edge. M C ounter bit5. Binary serial data input. Input data entered MSB first. M C ounter bit6. Serial clock input. SDATA is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. M C ounter bit7. M C ounter bit8 (MSB). A Counter bit0 (LSB). A Counter bit1. Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. A Counter bit2. A Counter bit3 (MSB). Direct mode select. “High” enables direct mode. “Low” enables serial mode. Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. Digital core VDD. Ground Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 16 PE97632 Advance Information Pin No. 46 47 48 49 50 Pin Name VDD Fin Fin GND CEXT Valid Mode Type (Note 1) Prescaler VDD. Description Both Both Input Input Downbond Output Prescaler input from the VCO. 3.2 GHz max frequency. Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected in series with a 50 Ω resistor directly to the ground plane. Ground Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). Data out function, enabled in enhancement mode. Output driver/V DD. Ground PD_D pulses down when fp leads fc . PD_U is driven to GND when CPSEL = “High”. No Connect Both Both Both 51 52 53 54 55 56 57 58 59 60 61 62 63 64 LD DOUT VDD GND PD_D NC PD_U GND VDD VDD GND fr VDD VDD GND Output Output (Note 1) Downbond Both Both Both Output Output Downbond (Note 1) (Note 1) Downbond PD_U pulses down when fc leads fp. PD_D is driven to GND when CPSEL = “High”. Ground Output driver/V DD. Phase detector VDD. Ground Reference frequency input. Reference VDD. Digital core VDD. Ground Enhancement mode. When asserted low (“0”), enhancement register bits are functional. No Connect Both Input (Note 1) (Note 1) Downbond 65 66 67 68 Note 1: Note 2: ENH NC MS2_SEL RND_SEL Both Both Both Input Input Input MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode. K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit is the phase detector comparison frequency / 219. Both All VDD pins are connected by diodes and must be supplied with the same positive voltage level. All digital input pins have 70 k Ω pull-down resistors to ground. ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 16 Document No. 70-0205-02 │ U ltraCMOS™ RFIC Solutions PE97632 Advance Information Table 2. Absolute Maximum Ratings Symbol VDD VI II IO Tstg Electrostatic Discharge (ESD) Precautions Units V V mA mA °C 4.0 Parameter/Conditions Supply voltage Voltage on any input DC into any input DC into any output Storage temperature range Min -0.3 -0.3 -10 -10 -65 Max VDD + 0.3 +10 +10 150 When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 3. Operating Ratings Symbol VDD TA Parameter/Conditions Supply voltage Operating ambient temperature range Min 2.85 -40 Max 3.45 85 Units V °C Table 4. ESD Ratings Symbol VESD Parameter/Conditions ESD voltage human body model (Note 1) Level 1000 Units V Note 1: P eriodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2 Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 16 PE97632 Advance Information Table 5. DC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol IDD Parameter Operational supply current; Prescaler enabled Operational supply current; Prescaler disabled Conditions VDD = 2.85 to 3.45 V Min Typ 50 Max Units mA IDD VDD = 2.85 to 3.45 V 10 mA All Digital inputs: K[17:0], R[5:0], M[8:0], A[3:0], Direct, Pre_en, Rand_en, M2_sel, Cpsel, Enh (contains a 70 kΩ pull-down resistor) VIH VIL IIH IIL High level input voltage Low level input voltage High level input current Low level input current VDD = 2.85 to 3.45 V VDD = 2.85 to 3.45 V VIH = VDD = 3.45 V VIL = 0, VDD = 3.45 V -1 0.7 x VDD 0.3 x VDD +100 V V µA µA µA µA Reference Divider input: fr IIHR IILR High level input current Low level input current VIH = VDD = 3.45 V VIL = 0, VDD = 3.45 V -100 +100 Counter and phase detector outputs: PD_D , PD_U VOLD VOHD Output voltage LOW Output voltage HIGH Iout = 6 mA Iout = - 3 mA Iout = 200 µA Iout = - 200 µA VDD - 0.4 VDD - 0.4 0.4 V V Digital test outputs: Dout VOLD VOHD Output voltage LOW Output voltage HIGH 0.4 V V Lock detect outputs: (Cext, LD) VOLC VOHC VOLLD Output voltage LOW, Cext Output voltage HIGH, Cext Output voltage LOW, LD Iout = 0.1 mA Iout = - 0.1 mA Iout = 1 mA VDD - 0.4 0.4 0.4 V V V ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 16 Document No. 70-0205-02 │ U ltraCMOS™ RFIC Solutions PE97632 Advance Information Table 6. AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol fClk tClkH tClkL tDSU tDHLD tPW tCWR tCE tWRC tEC Fin PFin Fin PFin fr Pfr fc ΦN ΦN Note 1: Note 2: Note 3: Note 4: Parameter Serial data clock frequency Serial clock HIGH time Serial clock LOW time Sdata set-up time to Sclk rising edge Sdata hold time after Sclk rising edge S_WR pulse width Sclk rising edge to S_WR rising edge Sclk falling edge to E_WR transition S_WR falling edge to Sclk rising edge E_WR transition to Sclk rising edge Conditions Control Interface and Latches (see Figures 3, 4) (Note 1) Min Typ Max 10 Units MHz ns ns ns ns ns ns ns ns ns 30 30 10 10 30 30 30 30 30 275 External AC coupling -5 50 External AC coupling Reference Divider (Note 3) Single ended input Phase Detector (Note 3) 1 kHz Offset 10 kHz Offset -97 -102 -2 50 -5 3200 5 300 5 100 Main Divider (Including Prescaler) (Note 4) Operating frequency Input level range Operating frequency Input level range Operating frequency Reference input power (Note 2) Comparison frequency Phase Noise Phase Noise Main Divider (Prescaler Bypassed) (Note 4) MHz dBm MHz dBm MHz dBc/Hz dBc/Hz MHz dBm SSB Phase Noise (Fin = 1.9 GHz, fr = 20 MHz, fc = 20 MHz, LBW = 50 kHz, VDD = 3.3 V, Temp = 25° C) (Note 4) fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80mV/ns. Parameter is guaranteed through characterization only and is not tested. Parameter below are not tested for die sales. These parameters are verified during the element evaluation per the die flow. Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 16 PE97632 Advance Information Functional Description The PE97632 consists of a prescaler, counters, an 18-bit delta-sigma modulator (DSM) and a phase detector. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters “R” and “M” divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter (“A”) is used in the modulus select logic. The DSM modulates the “A” counter outputs in order to achieve the desired fractional step. The phase-frequency detector generates up and down frequency control signals. Data is written into the internal registers via the three wire serial bus. There are also various operational and test modes and a lock detect output. Figure 3. Functional Block Diagram fr R C ounter (6-bit) fc R(5:0) M(8:0) PD_U Phase D etector Sdata C ontrol Pins C ontrol Logic K(17:0) A(3:0) PD_D DSM + Logic LD Modulus S elect C ext 2 kΩ Fin Fin 10/11 Prescaler M C ounter (9-bit) fp ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 16 Document No. 70-0205-02 │ U ltraCMOS™ RFIC Solutions PE97632 Advance Information Main Counter Chain Normal Operating Mode Setting the Pre_en control bit “low” enables the ÷10/11 prescaler. The main counter chain then divides the RF input frequency (Fin) by an integer or fractional number derived from the values in the “M”, “A” counters and the DSM input word K. The accumulator size is 18 bit, so the fractional value is fixed from the ratio K/218. There is an additional bit in the DSM that acts like an extra bit (19th bit). This bit is enabled by asserting the pin RAND_SEL to “high”. Enabling this bit has the benefit of reducing the spurious levels. However, a small frequency offset will occur. This positive frequency offset is calculated with the following equation. foffset = (fr / (R + 1)) / 219 (1) In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. The following equation relates Fin to the reference frequency fr: Fin = (M + 1) x (fr / (R+1)) where 1 ≤ M ≤ 511 (*) Only integer mode (4) In frequency bypass mode, neither A counter or K counter is used. Therefore, only integer-N operation is possible. Reference Counter The reference counter chain divides the reference frequency fr down to the phase detector comparison frequency fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: fc = fr / (R + 1) where 0 ≤ R ≤ 63 (5) All of the following equations do not take into account this frequency offset. If this offset is important to a specific frequency plan, appropriate account needs to be taken. In the normal mode, the output from the main counter chain (fp) is related to the VCO frequency (Fin) by the following equation: fp = Fin / [10 x (M + 1) + A + K/218] where A ≤ M + 1, 1 ≤ M ≤ 511 (2) Note that programming R with “0” will pass the reference frequency (fr) directly to the phase detector. Register Programming Serial Interface Mode While the E_WR input is “low” and the S_WR input is “low”, serial input data (Sdata input), B0 to B20, are clocked serially into the primary register on the rising edge of Sclk, MSB (B0) first. The LSB is used as address bit. When “0”, the contents from the primary register are transferred into the secondary register on the rising edge of either S_WR according to the timing diagrams shown in Figure 4. When “1”, data is transferred to the auxiliary register according to the same timing diagram. The secondary register is used to program the various counters, while the auxiliary register is used to program the DSM. Data are transferred to the counters as shown in Table 8 on page 10. When the loop is locked, Fin is related to the reference frequency (fr) by the following equation: Fin = [10 x (M + 1) + A + K/218] x (fr / (R+1)) where A ≤ M + 1, 1 ≤ M ≤ 511 (3) A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. The A counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in M. Programming the M counter with the minimum allowed value of “1” will result in a minimum M counter divide ratio of “2”. Prescaler Bypass Mode (*) Setting the frequency control register bit Pre_en “high” allows Fin to bypass the ÷10/11 prescaler. Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 16 PE97632 Advance Information While the E_WR input is “high” and the S_WR input is “low”, serial input data (Sdata input), B0 to B7, are clocked serially into the enhancement register on the rising edge of Sclk, MSB (B0) first. The enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of E_WR according to the timing diagram shown in Figure 4. After the falling edge of E_WR, the data provide control bits as shown in Table 9 on page 10 will have their bit functionality enabled by asserting the Enh input “low”. Direct Interface Mode Direct Interface Mode is selected by setting the “Direct” input “high”. Counter control bits are set directly at the pins as shown in Table 7 and Table 8. Table 7. Secondary Register Programming Interface M ode Direct S erial* Enh 1 1 R5 R5 B0 R4 R4 B1 M8 M8 B2 M7 M7 B3 Pre_en Pre_en B4 M6 M6 B5 M5 M5 B6 M4 M4 B7 M3 M3 B8 M2 M2 B9 M1 M1 B10 M0 M0 B11 R3 R3 B12 R2 R2 B13 R1 R1 B14 R0 R0 B15 A3 A3 B16 A2 A2 B17 A1 A1 B18 A0 A0 B19 Addr X 0 *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. MSB (first in) (last in) LSB Table 8. Auxiliary Register Programming Interface M ode Direct S erial* Enh 1 1 K17 K17 B0 K16 K16 B1 K15 K15 B2 K14 K14 B3 K13 K13 B4 K12 K12 B5 K11 K11 B6 K10 K10 B7 K9 K9 B8 K8 K8 B9 K7 K7 B10 K6 K6 B11 K5 K5 B12 K4 K4 B13 K3 K3 B14 K2 K2 B15 K1 K1 B16 K0 K0 B17 Rsrv X B18 Rsrv X B19 Addr X 1 *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. MSB (first in) (last in) LSB Table 9. Enhancement Register Programming Interface Mode Serial* Enh 0 Reserved B0 Reserved B1 fp output B2 Power Down B3 Counter load B4 MSEL output B5 fc output B6 LD Disable B7 *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge. (last in) LSB MSB (first in) ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 16 Document No. 70-0205-02 │ U ltraCMOS™ RFIC Solutions PE97632 Advance Information Figure 4. Serial Interface Mode Timing Diagram Sdata E_WR tEC tCE Sclk S_WR tDSU tDHLD tClkH tClkL tCWR tPW tWRC Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 10. Enhancement Register Bit Functionality Bit Function Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 ** Program to 0 Reserve ** Reserve ** fp output Power down Counter load MSEL output fc output LD Disable Reserved. Reserved. Drives the M counter output onto the Dout output. Power down of all functions except programming interface. Immediate and continuous load of counter programming. Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Drives the reference counter output onto the Dout output. Disables the LD pin for quieter operation. Description Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 16 PE97632 Advance Information Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, namely PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “low”. If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses “low”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. For the UP and DOWN mode, PD_U and PD_D drive an active loop filter which controls the VCO tune voltage. The phase detector gain is equal to VDD / 2 п. PD_U pulses cause an increase in VCO frequency and PD_D pulses cause a decrease in VCO frequency, for a positive Kv VCO. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2 kΩ resistor. Connecting Cext to an external shunt capacitor provides low pass filtering of this signal. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. Figure 5. Typical Phase Noise A typical phase noise plot is shown below. “Trace 1” is the smoothed average, and “Trace 2” is the raw data. Test Conditions: A typical phase noise plot is shown below. “Trace 1” is the smoothed average, and “Trace 2” is the raw data. Test Conditions: Fout = 1.9204 GHz in MASH 1-1 mode, Fcomparison = 20 MHz, VDD = 3.3 V, Temp = 25 C, Loop bandwidth = 50 kHz. ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 16 Document No. 70-0205-02 │ U ltraCMOS™ RFIC Solutions PE97632 Advance Information Figure 6. Typical Spurious Plot Test Conditions: Frequency step = 400 KHz, Loop bandwidth = 50 kHz, Fout = 1.9204 GHz, Fcomparison = 20 MHz, MASH 1-1, VDD = 3.3 V, Temp = 25C. Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 16 PE97632 Advance Information Figure 7. PE97632 Cobalt-60 Radiation Effect on Phase Noise (Fvco = 1.92 GHz, Fcomp = 20 MHz, LBW = 100 kHz, VDD = 3.3) -85 Pre-Rad 25C 100 kRad 25C Phase Noise (dBc/Hz) -90 -95 -100 -105 0.1 1 Frequency Offset from Carrier ( kHz ) 10 ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 14 of 16 Document No. 70-0205-02 │ U ltraCMOS™ RFIC Solutions PE97632 Advance Information Figure 8. Package Drawing Package dimensions: 68-lead CQFJ Table 11. Ordering Information Order Code 97632-01 97632-11 97632-00 Part Marking PE97632 ES PE97632 Description Engineering Samples Flight Units E valuation Kit Packaging 68-lead CQFJ 68-lead CQFJ Shipping Method Tray Tray 1/Box Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 15 of 16 PE97632 Advance Information Sales Offices The Americas Peregrine Semiconductor Corporation 9450 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Peregrine Semiconductor, Asia Pacific (APAC) Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Space and Defense Products Americas: Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 16 of 16 Document No. 70-0205-02 │ U ltraCMOS™ RFIC Solutions