BC352239A-IVQ-E4

Device Features ! Fully Qualified Bluetooth system ! Bluetooth v1.2 Specification Compliant ! Kalimba DSP Open Platform Co-Processor ! Full Speed Bluetooth Operation with Full Piconet Support _äìÉ`çêÉ»PJjìäíáãÉÇá~= bñíÉêå~ä Single Chip Bluetooth® v1.2 System Production Information Data Sheet For BC352239A November 2004 ! Scatternet Support ! Low Power 1.8V Operation ! 7 x 7mm 120-ball VFBGA Package ! Minimum External Components ! Integrated 1.8V regulator ! Dual UART Ports ! 16-bit Stereo Audio CODEC ! I2S and SPDIF Interfaces ! RoHS Compliant General Description BlueCore3-Multimedia External is a single chip radio and baseband IC for Bluetooth 2.4GHz systems. BC352239A interfaces to 8Mbit of external Flash memory. When used with the CSR Bluetooth software stack, it provides a fully compliant Bluetooth system to v1.2 of the specification for data and voice communications. Applications ! ! ! ! ! ! Stereo Headphones Automotive Hands-Free Kits Echo Cancellation High Performance Telephony Headsets Enhanced Audio Applications A/V Profile Support RAM External Memory FLASH BlueCore3-Multimedia External contains the Kalimba DSP, an open platform digital signal processor (DSP) coprocessor supporting enhanced audio applications. BlueCore3-Multimedia External has been designed to reduce the number of external components required, ensuring that production costs are minimised. The device incorporates auto-calibration and built-in self-test (BIST) routines to simplify development, type approval and production test. All hardware and device firmware is fully compliant with the Bluetooth v1.2 Specification. S PI Baseband DSP UART/USB RF IN RF OUT MCU 2.4 GHz Radio I/O PIO Audio In/Out Kalimba DSP PCM / I2S / SPDIF XTAL BlueCore3-Multimedia External System Architecture BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 1 of 116 Contents Contents Status Information ................................................................................................................................................ 7 Advance Information ............................................................................................................................................ 7 Pre-Production Information.................................................................................................................................. 7 Production Information ........................................................................................................................................ 7 Life Support Policy and Use in Safety-Critical Applications ............................................................................. 7 RoHS Compliance ................................................................................................................................................. 7 Trademarks, Patents and Licenses ..................................................................................................................... 7 1 2 Key Features .................................................................................................................................................. 8 7 x 7 VFBGA Package Information ............................................................................................................... 9 2.1 2.2 3 4 BlueCore3-Multimedia External Pinout Diagram................................................................................ 9 Device Terminal Functions .............................................................................................................. 10 _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet Electrical Characteristics ............................................................................................................................ 15 Radio Characteristics .................................................................................................................................. 22 4.1 Temperature +20°C ......................................................................................................................... 22 4.1.1 Transmitter ................................................................................................................................. 22 4.1.2 Receiver ..................................................................................................................................... 23 Temperature -40°C .......................................................................................................................... 24 4.2.1 Transmitter ................................................................................................................................. 24 4.2.2 Receiver ..................................................................................................................................... 24 Temperature -25°C .......................................................................................................................... 25 4.3.1 Transmitter ................................................................................................................................. 25 4.3.2 Receiver ..................................................................................................................................... 25 Temperature +85°C ......................................................................................................................... 26 4.4.1 Transmitter ................................................................................................................................. 26 4.4.2 Receiver ..................................................................................................................................... 26 Temperature +105°C ....................................................................................................................... 27 4.5.1 Transmitter ................................................................................................................................. 27 4.5.2 Receiver ..................................................................................................................................... 27 Power Consumption ........................................................................................................................ 28 4.2 4.3 4.4 4.5 4.6 5 6 Device Diagram ............................................................................................................................................ 29 Description of Functional Blocks ............................................................................................................... 30 6.1 RF Receiver..................................................................................................................................... 30 6.1.1 Low Noise Amplifier ................................................................................................................... 30 6.1.2 Analogue to Digital Converter .................................................................................................... 30 RF Transmitter................................................................................................................................. 30 6.2.1 IQ Modulator .............................................................................................................................. 30 6.2.2 Power Amplifier .......................................................................................................................... 30 6.2.3 Auxiliary DAC ............................................................................................................................. 30 RF Synthesiser ................................................................................................................................ 30 Clock Input and Generation ............................................................................................................. 30 Baseband and Logic ........................................................................................................................ 31 6.5.1 Memory Management Unit ......................................................................................................... 31 6.5.2 Burst Mode Controller ................................................................................................................ 31 6.5.3 Physical Layer Hardware Engine DSP....................................................................................... 31 6.5.4 RAM ........................................................................................................................................... 31 6.5.5 Kalimba DSP RAM..................................................................................................................... 31 6.5.6 External Memory Driver ............................................................................................................. 32 6.5.7 USB............................................................................................................................................ 32 6.5.8 Synchronous Serial Interface ..................................................................................................... 32 6.5.9 UART ......................................................................................................................................... 32 Microcontroller ................................................................................................................................. 32 6.6.1 Programmable I/O...................................................................................................................... 32 © Cambridge Silicon Radio Limited 2004 Production Information Page 2 of 116 6.2 6.3 6.4 6.5 6.6 BC352239A-ds-001Pc Contents 6.7 6.8 Kalimba DSP ................................................................................................................................... 33 7 Audio Interface................................................................................................................................. 34 6.8.1 Audio Input and Output .............................................................................................................. 34 6.8.2 Digital Audio Interface ................................................................................................................ 34 CSR Bluetooth Software Stacks ................................................................................................................. 35 7.1 BlueCore HCI Stack ........................................................................................................................ 35 7.1.1 Key Features of the HCI Stack - Standard Bluetooth Functionality ............................................ 36 7.1.2 Key Features of the HCI Stack - Extra Functionality .................................................................. 37 Stand-Alone BlueCore3-Multimedia External and Kalimba DSP Applications ................................. 38 Host-Side Software.......................................................................................................................... 39 Device Firmware Upgrade ............................................................................................................... 39 BCHS Software................................................................................................................................ 39 Additional Software for Other Embedded Applications .................................................................... 39 CSR Development Systems ............................................................................................................ 39 RF Ports .......................................................................................................................................... 40 8.1.1 TX_A and TX_B ......................................................................................................................... 40 8.1.2 Transmit Port Impedances for 7 x 7 VFBGA Package (2.4-2.5GHz vs. Temperature)............... 41 8.1.3 Receive Port Impedances for 7 x 7 VFBGA Package (2.4-2.5GHz vs. Temperature)................ 44 8.1.4 Transmit S Parameters .............................................................................................................. 45 8.1.5 Balanced Receive S Parameters ............................................................................................... 46 8.1.6 Single-Ended Input (RF_IN) ....................................................................................................... 47 8.1.7 Transmit RF Power Control for Class 1 Applications (TX_PWR) ............................................... 47 8.1.8 Control of External RF Components .......................................................................................... 48 External Reference Clock Input (XTAL_IN) ..................................................................................... 49 8.2.1 External Mode ............................................................................................................................ 49 8.2.2 XTAL_IN Impedance in External Mode ...................................................................................... 49 8.2.3 Clock Timing Accuracy............................................................................................................... 49 8.2.4 Clock Start-Up Delay.................................................................................................................. 50 8.2.5 Input Frequencies and PS Key Settings..................................................................................... 51 Crystal Oscillator (XTAL_IN, XTAL_OUT) ....................................................................................... 52 8.3.1 XTAL Mode ................................................................................................................................ 52 8.3.2 Load Capacitance ...................................................................................................................... 53 8.3.3 Frequency Trim .......................................................................................................................... 53 8.3.4 Transconductance Driver Model ................................................................................................ 54 8.3.5 Negative Resistance Model ....................................................................................................... 54 8.3.6 Crystal PS Key Settings ............................................................................................................. 54 8.3.7 Crystal Oscillator Characteristics ............................................................................................... 55 Off-Chip Program Memory............................................................................................................... 58 8.4.1 Minimum Flash Specification ..................................................................................................... 59 8.4.2 Common Flash Interface............................................................................................................ 60 8.4.3 Memory Timing .......................................................................................................................... 61 UART Interface ................................................................................................................................ 63 8.5.1 UART Bypass............................................................................................................................. 65 8.5.2 UART Configuration While RESET is Active.............................................................................. 65 8.5.3 UART Bypass Mode................................................................................................................... 65 8.5.4 Current Consumption in UART Bypass Mode ............................................................................ 65 USB Interface .................................................................................................................................. 66 8.6.1 USB Data Connections .............................................................................................................. 66 8.6.2 USB Pull-Up Resistor................................................................................................................. 66 8.6.3 Power Supply ............................................................................................................................. 66 8.6.4 Self-Powered Mode.................................................................................................................... 67 8.6.5 Bus-Powered Mode.................................................................................................................... 68 8.6.6 Suspend Current ........................................................................................................................ 69 8.6.7 Detach and Wake_Up Signalling................................................................................................ 69 8.6.8 USB Driver ................................................................................................................................. 69 8.6.9 USB 1.1 Compliance.................................................................................................................. 70 8.6.10 USB 2.0 Compatibility ................................................................................................................ 70 Serial Peripheral Interface ............................................................................................................... 70 © Cambridge Silicon Radio Limited 2004 Production Information _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet 7.2 7.3 7.4 7.5 7.6 7.7 8 8.1 Device Terminal Descriptions..................................................................................................................... 40 8.2 8.3 8.4 8.5 8.6 8.7 BC352239A-ds-001Pc Page 3 of 116 Contents 8.7.1 Instruction Cycle......................................................................................................................... 70 8.7.2 Writing to BlueCore3-Multimedia External ................................................................................. 71 8.7.3 Reading from BlueCore 3-Multimedia External .......................................................................... 71 8.7.4 Multi Slave Operation................................................................................................................. 71 8.8 Stereo Audio Interface ..................................................................................................................... 72 8.8.1 Stereo CODEC Setup ................................................................................................................ 73 8.8.2 ADC ........................................................................................................................................... 73 8.8.3 ADC Sample Rate Selection and Warping................................................................................. 73 8.8.4 ADC Gain ................................................................................................................................... 73 8.8.5 DAC ........................................................................................................................................... 75 8.8.6 DAC Sample Rate Selection and Warping................................................................................. 75 8.8.7 DAC Gain ................................................................................................................................... 75 8.8.8 Mono Operation ......................................................................................................................... 76 8.8.9 PCM CODEC Interface .............................................................................................................. 77 8.8.10 PCM Interface Master/Slave ...................................................................................................... 78 8.8.11 Long Frame Sync....................................................................................................................... 79 8.8.12 Short Frame Sync ...................................................................................................................... 79 8.8.13 Multi Slot Operation.................................................................................................................... 80 8.8.14 GCI Interface.............................................................................................................................. 80 8.8.15 Slots and Sample Formats ......................................................................................................... 81 8.8.16 Additional Features .................................................................................................................... 81 8.8.17 PCM Timing Information ............................................................................................................ 82 8.8.18 PCM Slave Timing ..................................................................................................................... 84 8.8.19 PCM_CLK and PCM_SYNC Generation.................................................................................... 86 8.8.20 PCM Configuration..................................................................................................................... 87 8.8.21 Digital Audio Bus........................................................................................................................ 89 8.8.22 IEC 60958 Interface ................................................................................................................... 92 8.8.23 Audio Input Stage....................................................................................................................... 93 8.8.24 Microphone Input ....................................................................................................................... 94 8.8.25 Line Input ................................................................................................................................... 94 8.8.26 Output Stage .............................................................................................................................. 95 8.9 I/O Parallel Ports.............................................................................................................................. 95 8.9.1 PIO Defaults for BTv1.2 HCI Level Bluetooth Stack................................................................... 96 8.10 I2C Interface..................................................................................................................................... 96 8.11 8.12 TCXO Enable OR Function ............................................................................................................. 97 RESET and RESETB ...................................................................................................................... 97 8.12.1 Pin States on Reset ................................................................................................................... 98 8.12.2 Status after Reset ...................................................................................................................... 98 8.13 Power Supply................................................................................................................................... 99 8.13.1 Voltage Regulator ...................................................................................................................... 99 8.13.2 Sequencing ................................................................................................................................ 99 8.13.3 Sensitivity to Disturbances ......................................................................................................... 99 Typical Audio CODEC Performance......................................................................................................... 100 9.1 Output............................................................................................................................................ 100 _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet 9 10 Application Schematic............................................................................................................................... 108 11 Package Dimensions ................................................................................................................................. 109 11.1 12.1 13.1 7 x 7 VFBGA 120-Ball Package .................................................................................................... 109 Solder Re-flow Profile for Devices with Lead-Free Solder Balls .................................................... 110 BlueCore3-Multimedia External ..................................................................................................... 111 12 Solder Profiles............................................................................................................................................ 110 13 Ordering Information ................................................................................................................................. 111 14 Contact Information ................................................................................................................................... 112 15 Document References ............................................................................................................................... 113 Acronyms and Definitions................................................................................................................................ 114 Record of Changes ........................................................................................................................................... 116 BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 4 of 116 Contents List of Figures Figure 2.1: BlueCore3-Multimedia External Device Pinout ..................................................................................... 9 Figure 5.1: BlueCore3-Multimedia External Device Diagram ................................................................................ 29 Figure 6.1: Kalimba DSP Interface to Internal Functions ...................................................................................... 33 Figure 6.2: Audio Interface .................................................................................................................................... 34 Figure 7.1: BlueCore HCI Stack ............................................................................................................................ 35 Figure 7.2: Kalimba DSP Stack............................................................................................................................. 38 Figure 8.1: Circuit TX/RX_A and TX/RX_B ........................................................................................................... 40 Figure 8.2: TX_A Output at Power Setting 35 ....................................................................................................... 41 Figure 8.3: TX_A Output at Power Setting 50 ....................................................................................................... 41 Figure 8.4: TX_A Output at Power Setting 63 ....................................................................................................... 42 Figure 8.5: TX_B Output at Power Setting 35 ....................................................................................................... 42 Figure 8.6: TX_B Output at Power Setting 50 ....................................................................................................... 43 Figure 8.7: TX_B Output at Power Setting 63 ....................................................................................................... 43 Figure 8.8: RX_A Balanced Receive Input Impedance ......................................................................................... 44 Figure 8.9: RX_B Balanced Receive Input Impedance ......................................................................................... 44 Figure 8.10: First Stage of ADC Analogue Amplifier Block Diagram ..................................................................... 74 Figure 8.11: BlueCore3-Multimedia External as PCM Interface Master ................................................................ 78 Figure 8.12: BlueCore3-Multimedia External as PCM Interface Slave .................................................................. 78 Figure 8.13: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................... 79 Figure 8.14: Short Frame Sync (Shown with 16-bit Sample) ................................................................................ 79 Figure 8.15: Multi Slot Operation with Two Slots and 8-bit Companded Samples ................................................ 80 Figure 8.16: GCI Interface..................................................................................................................................... 80 Figure 8.17: 16-Bit Slot Length and Sample Formats ........................................................................................... 81 Figure 8.18: PCM Master Timing Long Frame Sync ............................................................................................. 83 Figure 8.19: PCM Master Timing Short Frame Sync............................................................................................. 83 Figure 8.20: PCM Slave Timing Long Frame Sync ............................................................................................... 85 Figure 8.21: PCM Slave Timing Short Frame Sync .............................................................................................. 85 Figure 8.22: Digital Audio Interface Modes ........................................................................................................... 89 Figure 8.23: Digital Audio Interface Slave Timing ................................................................................................. 90 Figure 8.24: Digital Audio Interface Master Timing ............................................................................................... 91 Figure 8.25: Example Circuit for SPDIF Interface with Coaxial Output ................................................................. 92 Figure 8.26: Example Circuit for SPDIF Interface with Coaxial Input .................................................................... 92 Figure 8.27: Example Circuit for SPDIF Interface with Optical Output .................................................................. 93 Figure 8.28: Example Circuit for SPDIF Interface with Optical Input ..................................................................... 93 Figure 8.29: Microphone Biasing (Left Channel Shown) ....................................................................................... 94 Figure 8.30: Differential Input (Left Channel Shown) ............................................................................................ 94 Figure 8.31: Single Ended Input (Left Channel Shown) ........................................................................................ 94 Figure 8.32: Speaker Output (Left Channel Shown) ............................................................................................. 95 Figure 8.33: Example EEPROM Connection ........................................................................................................ 96 Figure 8.34: Example TXCO Enable OR Function ................................................................................................ 97 Figure 10.10.1: Relative Level of 2nd Harmonic to Fundamental, PL = 600Ω ....................................................... 100 Figure 10.10.2: Relative Level of 3rd Harmonic to Fundamental, PL = 600Ω ...................................................... 101 Figure 10.10.3: Relative Level of 2nd Harmonic to Fundamental, PL = 32Ω ......................................................... 102 Figure 10.10.4: Relative Level of 3rd Harmonic to Fundamental, PL = 32Ω ......................................................... 103 Figure 10.10.5: Relative Level of 2nd Harmonic to Fundamental, PL = 22Ω ......................................................... 104 _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 5 of 116 Contents Figure 10.10.6: Relative Level of 3rd Harmonic to Fundamental, PL = 22Ω ......................................................... 105 Figure 10.10.7: Noise Floor................................................................................................................................. 106 Figure 10.10.8: THD+N ....................................................................................................................................... 107 Figure 11.11.1: Application Circuit for Radio Characteristics Specification with 7 x 7 VFBGA Package ............. 108 Figure 12.12.1: BlueCore3-Multimedia External 120-Ball VFBGA Package Dimensions.................................... 109 Figure 13.13.1: Typical Lead-Free Re-flow Solder Profile................................................................................... 110 _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet List of Tables Table 6.1: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface .................................... 34 Table 8.1: Transmit S Parameters ........................................................................................................................ 45 Table 8.2: Balanced Receiver S Parameters ........................................................................................................ 46 Table 8.3: DAC Digital Gain Rate Selection.......................................................................................................... 75 Table 8.4: DAC Analogue Gain Settings ............................................................................................................... 76 Table 8.5: PCM Master Timing.............................................................................................................................. 82 Table 8.6: PCM Slave Timing................................................................................................................................ 84 Table 8.7: PSKEY_PCM_CONFIG32 Description................................................................................................. 87 Table 8.8: PSKEY_PCM_LOW_JITTER_CONFIG Description ............................................................................ 88 Table 8.9: Digital Audio Interface Slave Timing .................................................................................................... 90 Table 8.10: Digital Audio Interface Master Timing................................................................................................. 91 Table 8.11: PIO Defaults....................................................................................................................................... 96 Table 8.12: Pin States of BlueCore3-Multimedia External on Reset ..................................................................... 98 List of Equations Equation 8.1: Output Voltage with Load Current ≤ 10mA...................................................................................... 47 Equation 8.2: Output Voltage with No Load Current ............................................................................................. 47 Equation 8.3: Load Capacitance ........................................................................................................................... 53 Equation 8.4: Trim Capacitance ............................................................................................................................ 53 Equation 8.5: Frequency Trim ............................................................................................................................... 53 Equation 8.6: Pullability......................................................................................................................................... 53 Equation 8.7: Transconductance Required for Oscillation .................................................................................... 54 Equation 8.8: Equivalent Negative Resistance ..................................................................................................... 54 Equation 8.9: Baud Rate ....................................................................................................................................... 64 Equation 8.10: PCM_CLK Frequency When Being Generated Using the Internal 48MHz clock .......................... 86 Equation 8.11: PCM_SYNC Frequency Relative to PCM_CLK ............................................................................ 86 BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 6 of 116 Status Information Status Information The status of this Data Sheet is Production Information. CSR Product Data Sheets progress according to the following format: _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet Advance Information Information for designers concerning CSR product in development. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice. Pre-Production Information Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All electrical specifications may be changed by CSR without notice. Production Information Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications. Production Data Sheets supersede all previous document versions. Life Support Policy and Use in Safety-Critical Applications CSR’s products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications. RoHS Compliance BlueCore3-Multimedia External devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). Trademarks, Patents and Licenses BlueCore™, BlueLab™, Casira™, CompactSira™ and MicroSira™ are trademarks of CSR. Bluetooth® and the Bluetooth logos are trademarks owned by Bluetooth SIG Inc, USA and are licensed to CSR. Windows®, Windows 98™, Windows 2000™, Windows XP™ and Windows NT™ are registered trademarks of the Microsoft Corporation. I2C™ and I2S are registered trademarks of the Philips Corporation and SPDIF is the registered trademark of the Sony Corporation and Philips Corporation. All other product, service and company names are trademarks, registered trademarks or service marks of their respective owners. The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR Ltd. CSR reserves the right to make technical changes to its products as part of its development programme. While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors. BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 7 of 116 Key Features 1 Key Features Kalimba DSP ! DSP co-processor, 32MIPs, 24-bit fixed point DSP core matching; eliminates external antenna switch Radio ! Common TX/RX terminal simplifies external ! BIST minimises production test time. No external trimming is required in production _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet ! Single cycle MAC; 24 x 24-bit multiply and 56-bit accumulator ! Full RF reference designs available ! Bluetooth v1.2 Specification compliant ! 32-bit instruction word, dual 24-bit data memory ! 4Kword program memory, 2 x 8Kword data memory Transmitter ! +6dBm RF transmit power with level control from on-chip 6-bit DAC over a dynamic range >30dB ! Flexible interfaces to BlueCore3 subsystem Baseband and Software ! External 8Mbit Flash for complete system solution ! Internal 32Kbyte RAM, allows full speed data transfer, mixed voice and data, and full piconet operation ! Class 2 and Class 3 support without the need for an external power amplifier or TX/RX switch ! Class1 support using external power amplifier, with RF power controlled by an internal 8-bit DAC Receiver ! Integrated channel filters ! Digital demodulator for improved sensitivity and co-channel rejection ! Logic for forward error correction, header error control, access code correlation, CRC, demodulation, encryption bit stream generation, whitening and transmit pulse shaping ! Transcoders for A-law, µ-law and linear voice from host and A-law, µ-law and CVSD voice over air ! Real time digitised RSSI available on HCI interface ! Fast AGC for enhanced dynamic range Physical Interfaces ! Synchronous serial interface up to 4Mbaud for system debugging Synthesiser ! Fully integrated synthesiser requires no external VCO, varactor diode, resonator or loop filter ! UART interface with programmable baud rate up to 1.5Mbaud with an optional bypass mode ! Compatible with crystals between 8 and 32MHz (in multiples of 250kHz) or an external clock ! Full speed USB v1.1 interface supports OHCI and UHCI host interfaces ! Accepts 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz TCXO frequencies for GSM and CDMA devices with sinusoidal or logic level signals ! Bi-directional serial programmable audio interface supporting PCM, I2S and SPDIF formats ! Optional I2C™ compatible interface Auxiliary Features ! Crystal oscillator with built-in digital trimming ! Power management includes digital shut down and wake up commands with an integrated low power oscillator for ultra-low power Park/Sniff/Hold mode Stereo Audio CODEC ! 16-bit resolution, standard sample rates of 8kHz, 11.025kHz, 16kHz, 22.05kHz, 32kHz, 44.1kHz and 48kHz (DAC only) ! Dual ADC and DAC for stereo audio ! Integrated amplifiers for driving microphone and speakers with minimum external components ! ‘Clock request’ output to control an external clock ! On-chip linear regulator; 1.8V output from a 2.2-4.2V input ! Compatible with Kalimba DSP ! Power-on-reset cell detects low supply voltage ! Arbitrary power supply sequencing permitted ! 8-bit ADC and DAC available to applications Bluetooth Stack CSR’s Bluetooth Protocol Stack runs on the on-chip MCU in a variety of configurations: Package Options ! 120-ball VFBGA, 7 x 7 x 1mm, 0.5mm pitch ! Standard HCI (UART or USB) ! Fully embedded RFCOMM ! Customised builds with embedded application code BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 8 of 116 7 x 7 VFBGA Package Information 2 2.1 7 x 7 VFBGA Package Information BlueCore3-Multimedia External Pinout Diagram Orientation from top of device _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 A B C D E F G H J K L M N A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3 G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 Figure 2.1: BlueCore3-Multimedia External Device Pinout BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 9 of 116 7 x 7 VFBGA Package Information 2.2 Radio AUX_DAC Device Terminal Functions Ball D2 C1 Pad Type Analogue Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Analogue Analogue Analogue Description Voltage DAC output Control output for external Tx/Rx switch (if fitted) Control output for external PA (If fitted) Single ended receiver input Transmitter output/switched receiver input Complement of TX_A PIO[0]/RXEN _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet PIO[1]/TXEN B1 RF_IN TX_A TX_B Synthesiser and Oscillator XTAL_IN XTAL_OUT USB and UART UART_TX UART_RX UART_RTS UART_CTS USB_DP USB_DN PCM Interface PCM_OUT PCM_IN PCM_SYNC PCM_CLK Note: (1) (1) E1 G1 F1 Ball N1 N2 Ball J12 K11 L12 K12 L13 K13 Ball G13 J11 H11 H13 Pad Type Analogue Analogue Pad Type CMOS output, tri-state, with weak internal pull-up CMOS input with weak internal pull-down CMOS output, tri-state, with weak internal pull-up CMOS input with weak internal pull-down Bi-directional Bi-directional Pad Type CMOS output, tri-state, with weak internal pull-down CMOS input, with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Description For crystal or external clock input Drive for crystal Description UART data output UART data input UART request to send active low UART clear to send active low USB data plus with selectable internal 1.5kΩ pull-up resistor USB data minus Description Synchronous data output Synchronous data input Synchronous data sync Synchronous data clock Pin names may be redefined dependent on chosen interface; see Table 6.1. BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 10 of 116 7 x 7 VFBGA Package Information PIO Port PIO[11] Ball A3 Pad Type Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional Bi-directional Bi-directional Bi-directional Pad Type CMOS input with weak internal pull-down CMOS input with weak internal pull-up CMOS input with weak internal pull-up CMOS input with weak internal pull-down CMOS input with weak internal pull-down CMOS output, tri-state, with weak internal pull-down CMOS input with strong internal pull-down Description Programmable input/output line PIO[10] B3 Programmable input/output line _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet PIO[9] C3 Programmable input/output line PIO[8] PIO[7]/UART_RX(1)/ CLK_OUT PIO[6]/CLK_REQ/ UART_CTS (1) D3 Programmable input/output line Programmable input/output line or programmable frequency clock output PIO line or clock request output to enable external clock for external clock line PIO line or chip detaches from USB when this input is high PIO or USB on (input senses when VBUS is high, wakes BlueCore3-Multimedia External) PIO or output goes high to wake up PC when in USB mode or clock request input from host controller PIO or external clock request Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line Description Reset if high. Input debounced so must be high for >5ms to cause a reset Reset if low. Input debounced so must be low for >5ms to cause a reset Chip select for Synchronous Serial Interface active low Serial Peripheral Interface clock Serial Peripheral Interface data input Serial Peripheral Interface data output For test purposes only (leave unconnected) G11 F13 PIO[5]/USB_DETACH/ UART_RTS (1) F11 PIO[4]/USB_ON/ UART_TX (1) F12 PIO[3]/USB_WAKE_UP/ HOST_CLK_REQ PIO[2]/CLK_REQ AIO[0] AIO[1] AIO[2] AIO[3] Test and Debug RESET RESETB SPI_CSB SPI_CLK SPI_MOSI SPI_MISO TEST_EN B2 C2 N3 L4 M4 N4 Ball B12 E12 C11 C13 D12 B13 B11 BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 11 of 116 7 x 7 VFBGA Package Information CODEC AUDIO_IN_P_RIGHT AUDIO_IN_N_RIGHT AUDIO_IN_P_LEFT AUDIO_IN_N_LEFT AUDIO_OUT_N_RIGHT AUDIO_OUT_P_RIGHT AUDIO_OUT_N_LEFT AUDIO_OUT_P_LEFT External Memory Address Interface A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] Ball L3 M3 J3 K3 L2 M2 L1 M1 Ball N9 M8 A11 M12 N12 L11 M11 N11 L10 M10 N10 N8 L7 M7 M6 L5 M5 N5 C4 Pad Type Analogue Analogue Analogue Analogue Analogue Analogue Analogue Analogue Pad Type CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state Description Microphone input positive (right side) Microphone input negative (right side) Microphone input positive (left side) Microphone input negative (left side) Speaker output negative (right side) Speaker output positive (right side) Speaker output negative (left side) Speaker output positive (left side) Description Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 12 of 116 7 x 7 VFBGA Package Information External Memory Data Interface D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Ball A10 C10 B9 A8 C8 B7 A6 B5 B10 A9 C9 B8 A7 B6 A5 C5 Pad Type Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Pad Type CMOS output, tri-state with internal weak pull-up CMOS output, tri-state with internal weak pull-up CMOS output, tri-state with internal weak pull-up Description Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet External Memory Interface REB WEB CSB Ball A4 L9 B4 Description Read enable for external memory (active low) Write enable for external memory (active low) Chip select for external memory (active low) BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 13 of 116 7 x 7 VFBGA Package Information Power Supplies and Control VREG_IN VDD_RADIO VDD_LO VDD_CORE Ball N7 H2 D1 J2 C7 E13 L8 K2 Pad Type VDD/Regulator input VDD/Regulator sense VDD VDD Description Linear regulator input Positive supply for RF circuitry _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet Positive supply for local oscillator circuitry Positive supply for internal digital circuitry Positive supply for analogue circuitry and 1.8V regulated output. For optimum performance, regulator decoupling and loads should be connected to this ball Positive supply for analogue circuitry and 1.8V regulated output Positive supply for external memory, AIO and extended PIO ports Positive supply for all other digital Input/Output ports (3) Positive supply for PIO and AUX DAC(2) Positive supply for UART/USB ports VDD_ANA VDD/Regulator output VDD_ANA VDD_MEM VDD_PADS VDD_PIO VDD_USB N6 A13 N13 D11 A2 M13 E2 F2 E3 H1 G2 G3 J1 C6 E11 M9 H3 K1 L6 A1 A12 J13 F3 VDD/Regulator output VDD VDD VDD VDD VSS_RADIO VSS Ground connections for RF circuitry VSS_LO VSS_CORE VSS_ANA VSS_PADS VSS Notes: (1) (2) (3) VSS VSS VSS VSS VSS Ground connection for local oscillator Ground connections for internal digital circuitry Ground connections for analogue circuitry Ground connections for digital Input/Output ports Ground connection for internal package shield Transparent UART port maps directly to main UART port. Positive supply for PIO[3:0] and PIO[11:8]. Positive supply for SPI/PCM ports and PIO[7:4]. Ball C12, D13, G12, H12 Description Leave unconnected Unconnected Terminals BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 14 of 116 Electrical Characteristics 3 Electrical Characteristics Minimum -40°C -0.4V -0.4V -0.4V VSS-0.4V Maximum +150°C 2.2V 3.7V 5.6V VDD+0.4V Absolute Maximum Ratings Rating Storage Temperature Supply Voltage: VDD_RADIO, VDD_LO, VDD_ANA and VDD_CORE Supply Voltage: VDD_MEM, VDD_PADS, VDD_PIO and VDD_USB Supply Voltage: VREG_IN Other Terminal Voltages Recommended Operating Conditions Operating Condition Operating Temperature Range Guaranteed RF performance range (1) _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet Minimum -40°C -25°C 1.7V 1.7V 2.2V Maximum +105°C +85°C 1.9V 3.6V 4.2V(2) Supply Voltage: VDD_RADIO, VDD_LO, VDD_ANA and VDD_CORE Supply Voltage: VDD_MEM, VDD_PADS, VDD_PIO and VDD_USB Supply Voltage: VREG_IN Notes: (1) (2) Typical figures are given for RF performance between -40°C and +105°C. The device will operate without damage with VREG_IN as high as 5.6V, however the RF performance is not guaranteed above 4.2V. BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 15 of 116 Electrical Characteristics Input/Output Terminal Characteristics Linear Regulator Normal Operation Output Voltage (Iload = 70 mA) Temperature Coefficient Output Noise(1)(2) Load Regulation (Iload < 100 mA) Settling Time (1)(3) Minimum Typical Maximum Unit 1.70 -250 140 5 25 1.78 35 1.85 +250 1 50 50 4.2(6) 350 50 V ppm/°C mV rms mV/A µs mA µA V mV µA _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet Maximum Output Current Minimum Load Current Input Voltage Dropout Voltage (Iload = 70 mA) Quiescent Current (excluding Ioad, Iload < 1mA) Low Power Mode(4) Quiescent Current (excluding Ioad, Iload < 100µA) Disabled Mode (5) 4 7 10 µA Quiescent Current Notes: 1.5 2.5 3.5 µA For optimum performance the VDD_ANA ball adjacent to VREG_IN should be used for regulator ouput. (1) (2) (3) (4) (5) (6) Regulator output connected to 47nF pure and 4.7µF 2.2Ω ESR capacitors. Frequency range 100Hz to 100kHz. 1mA to 70mA pulsed load. Low power mode is entered and exited automatically when the chip enters/leaves Deep Sleep mode. Regulator is disabled when VREG_IN is either open circuit or driven to the same voltage as VDD_ANA. Operation up to 5.6V is permissible without damage and without the output voltage rising sufficiently to damage the rest of BlueCore3, but output regulation and other specifications are no longer guaranteed at input voltages in excess of 4.2V. BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 16 of 116 Electrical Characteristics Input/Output Terminal Characteristics (Continued) Digital Terminals Input Voltage Levels Minimum Typical Maximum Unit _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet VIL input logic level low VIH input logic level high Output Voltage Levels VOL output logic level low, (lo = 4.0mA), 2.7V ≤ VDD ≤ 3.0V VOL output logic level low, (lo = 4.0mA), 1.7V ≤ VDD ≤ 1.9V VOH output logic level high, (lo = -4.0mA), 2.7V ≤ VDD ≤ 3.0V VOH output logic level high, (lo = -4.0mA), 1.7V ≤ VDD ≤ 1.9V Input and Tri-state Current with: Strong pull-up Strong pull-down Weak pull-up Weak pull-down I/O pad leakage current CI Input Capacitance 2.7V ≤ VDD ≤ 3.0V 1.7V ≤ VDD ≤ 1.9V -0.4 -0.4 0.7VDD - +0.8 +0.4 VDD+0.4 V V V VDD-0.2 VDD-0.4 - 0.2 0.4 - V V V V -100 +10 -5.0 +0.2 -1 1.0 -40 +40 -1.0 +1.0 0 - -10 +100 -0.2 +5.0 +1 5.0 µA µA µA µA µA pF BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 17 of 116 Electrical Characteristics Input/Output Terminal Characteristics (Continued) USB Terminals VDD_USB for correct USB operation Input threshold VIL input logic level low VIH input logic level high Input leakage current VSS_PADS < VIN < VDD_USB(1) CI Input capacitance Output Voltage levels To correctly terminated USB Cable VOL output logic level low VOH output logic level high Input/Output Terminal Characteristics (Continued) Power-on reset VDD_CORE falling threshold VDD_CORE rising threshold Hysteresis Input/Output Terminal Characteristics (Continued) Crystal Oscillator Crystal frequency Digital trim range Trim step size (5) (4) (5) Minimum 3.1 0.7VDD_USB -1 2.5 Typical Maximum 3.6 Unit V _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet 1 - 0.3VDD_USB 5 10.0 V V µA pF 0.0 2.8 - 0.2 VDD_USB V V Minimum 1.40 1.50 0.05 Typical 1.50 1.60 0.10 Maximum 1.60 1.70 0.15 Unit V V V Minimum 8.0 5.0 2.0 870 Typical 6.2 0.1 1500 Maximum 32.0 8.0 2400 Unit MHz pF pF mS Ω Transconductance Negative resistance(6) External Clock Input frequency(7) Clock input level Allowable jitter XTAL_IN input impedance XTAL_IN input capacitance (8) 7.5 0.2 - 7 40.0 VDD_ANA 15 - MHz V pk-pk ps rms kΩ pF BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 18 of 116 Electrical Characteristics Input/Output Terminal Characteristics (Continued) Auxiliary ADC Resolution Input voltage range (LSB size = VDD_ANA/255) Accuracy (Guaranteed monotonic) Offset Gain Error Input Bandwidth Conversion time Sample rate (2) Minimum 0 INL DNL -1 0 -1 -0.8 - Typical 100 2.5 - Maximum 8 VDD_ANA 1 1 1 0.8 700 Unit Bits V LSB LSB LSB % kHz µs Samples/s _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet Input/Output Terminal Characteristics (Continued) Auxiliary DAC Resolution Average output step size(3) Output Voltage Voltage range (IO=0mA) Current range Minimum output voltage (IO=100mA) Maximum output voltage (IO=10mA) High Impedance leakage current Offset Integral non-linearity(3) Settling time (50pF load) VSS_PADS -10.0 0.0 VDD_PIO-0.3 -1 -220 -2 Minimum 12.5 Typical 14.5 monotonic (3) Maximum 8 17.0 VDD_PIO +0.1 0.2 VDD_PIO +1 +120 +2 10 Unit Bits mV V mA V V µA mV LSB µs BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 19 of 116 Electrical Characteristics Input/Output Terminal Characteristics (Continued) Stereo Audio CODEC Input Stage/Microphone Amplifier Input full scale at maximum gain Input full scale at minimum gain Gain resolution Distortion at 1kHz Input referenced rms noise in 15kHz bandwidth 3dB Bandwidth Input impedance THD+N (microphone input) @ 30mV rms input Analogue to Digital Converter Resolution Input sample rate Signal / (Noise + Distortion), 0 - Fsample /2, with full scale 1kHz tone Fsample = 8kHz Fsample = 11.025kHz Fsample = 16kHz Fsample = 22.050kHz Fsample = 32kHz Fsample = 44.1kHz Digital Gain Digital to Analogue Converter Resolution Output sample rate Gain Resolution Signal / (Noise + Distortion), 0 – 20 kHz, with full scale 1kHz tone Fsample = 8kHz Fsample = 11.025kHz Fsample = 16kHz Fsample = 22.050kHz Fsample = 32kHz Fsample = 44.1kHz Fsample = 48kHz Digital Gain -24 79 78 79 88 90 90 89 21.5 dB dB dB dB dB dB dB dB 8 3 16 48 bits kHz dB -24 84 83 84 83 80 74 21.5 dB dB dB dB dB dB dB 8 16 44.1 bits kHz 8 17 20 -66 4 400 3 -74 mV rms mV rms dB dB µV rms kHz kΩ dB Minimum Typical Maximum Unit _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 20 of 116 Electrical Characteristics Input/Output Terminal Characteristics (Continued) Output Stage/Loudspeaker Driver Output power into 32Ω Output voltage full scale swing Output current drive (at full scale swing) (9) (9) Minimum 10 16 - Typical 30 2.0 20 75 -75 - Maximum 40 O.C. 500 Unit mW pk V pk-pk mA mA dBc Ω pF _äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet Output full scale current (at reduced swing) Allowed Load: resistive Allowed Load: capacitive Notes: Distortion and noise (relative to full scale), THD VDD_CORE, VDD_RADIO, VDD_LO and VDD_ANA are at 1.8V unless shown otherwise. VDD_PADS, VDD_PIO and VDD_USB are at 3.0V unless shown otherwise. The same setting of the digital trim is applied to both XTAL_IN and XTAL_OUT. Current drawn into a pin is defined as positive, current supplied out of a pin is defined as negative. (1) (2) Internal USB pull-up disabled. Access of ADC is through VM function and therefore sample rate given is achieved as part of this function. Specified for an output voltage between 0.2V and VDD_PIO -0.2V. Integer multiple of 250kHz. The difference between the internal capacitance at minimum and maximum settings of the internal digital trim. XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF. Clock input can be any frequency between 8 and 40MHz in steps of 250kHz plus CDMA/3G TCXO frequencies of 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz. Clock input can either be sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or above VDD_ANA a DC blocking capacitor is required between the signal and XTAL_IN. For specified THD. Much greater current can be supplied by the loudspeaker driver with compromised THD. (3) (4) (5) (6) (7) (8) (9) BC352239A-ds-001Pc © Cambridge Silicon Radio Limited 2004 Production Information Page 21 of 116 Radio Characteristics 4 4.1 4.1.1 Radio Characteristics Temperature +20°C Transmitter VDD = 1.8V Temperature = +20°C Min Typ 6.5 35 0.5 800 -40 -45 165 145 0.9 10 8 9 10 Typ -143 -138 -131 -135 -135 -137 -132 -135 Max Max Bluetooth Specification -6 to +4(4) ≥16 ≤1000 ≤-20 ≤-40 140